Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD3 (single, post-index, S)

Test 1: uops

Code:

  ld3 { v0.s, v1.s, v2.s }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.003

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 3.003

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)0f18191e1f3a3f43464951schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f60696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)c2c9cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
64005293792282204000030468528603010169235000100030001000100030001000500050023573018022768290202910371050001000300020006000290152906711610011000100001002031001001100121000130419356693331430382014132193796632312840310001605713200143031000300010002909129069291072915829172
64004291352260202000014988463928764011170205003100030031000100030001000500050003572521022770291032911931050001000300020006000290812900011610011000100001000031001101100120000132059361693131590322020932363811834372850010001605913045141311000300010002915329047291872905829137
64004291662260002000000461528778010168875003100030031000100030001000500050003574715022792291072922431050001000300020006000291732913311610011000100001000001000001100121300129959292693231110352015032363801729352841510001593413140142201000300010002913029064291422917229201
64004291952260101000000463328811011171095000100030031000100030001000500050003574311022839290832919031050001000300020006000290302905311610011000100001000001000000100021300131209455692231250312017732643799935262844810001600313125142231000300010002924229235291062916429218
6400429145226010000003045732876801017076500310003003100010003000100050005000357246022877290802908431050001000300020006000291362904011610011000100001000021000000100020300132269413692331600342027932243814534332834910001609413290142061000300010002914929208292042921829227
6400429296228030100003046312882900017082500010003003100010003000100050005000357176022824291052919931050001000300020006000290682909611610011000100011000001001001100020300129939355679131701352027332013813638352850310001610812943144321000300010002917929164292462907829288
64004291792270102000000473228866011169975003100030031000100030001000500050003580211022811290992909531050001000300020006000292382907611610011000100001000001000000100032300132009277687631031322025433183808930312845310001605212794138651000300010002915929267292382922829251
64004291452270203000030471328752000169295003100030031000100030001000500050003575915022819290972923831050001000300020006000290592911011610011000100001000031000000100130300131489472697231101372024932453806529282856010001620513188142901000300010002922629262292252927429167
64004292702270001000000456128728001170015003100030031000100030001000500050003580010022819290642911931050001000300020006000290992905311610011000100011000031000001100000300129469404692731951362029132443809629342843910001593113140142771000300010002919129219292072924429232
64004292002260102000030466528786010170985000100030031000100030001000500050003578760227962903529267310500010003000200060002904929207116100110001000010000010000001000003001321193766996316903020234324538131131302844610001620413346143021000300010002929729285292762915829271

Test 2: throughput

Count: 8

Code:

  ld3 { v0.s, v1.s, v2.s }[1], [x6], x8
  ld3 { v0.s, v1.s, v2.s }[1], [x6], x8
  ld3 { v0.s, v1.s, v2.s }[1], [x6], x8
  ld3 { v0.s, v1.s, v2.s }[1], [x6], x8
  ld3 { v0.s, v1.s, v2.s }[1], [x6], x8
  ld3 { v0.s, v1.s, v2.s }[1], [x6], x8
  ld3 { v0.s, v1.s, v2.s }[1], [x6], x8
  ld3 { v0.s, v1.s, v2.s }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f233a3f4346494e51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
320205160473128900110075108752800160516106159455260401468805652403248052280564241512804064162974068562278364701601421605071603547964538004840010020080000240000200160000480000160041160041118020110099100100800008000011008000000800100003800100110000511011711160038180000668000024000080100160056160056160056160056160056
32020416005512850000000113200016009816615983850400106801582400068005880100240000800004804994010562279271601600781601001601147989014800154003842008000024017420016011648000016012516005521802011009910010080000800000100800000080010102108006660101700512311711160052180058668000024000080100160057160115160056160056160056
32020416011412850000110015010160040066159872254001068010024000080000801002400008000048049940008222792716016003616005516005579923380037400100200800002400002001600004800001600411600411180201100991001008000080000010080057018800120021080009600000511011711160052080000068000024000080100160056160056160042160056160042
320204160041128500001100132000160099166159818130400258801582400008000080158240000800004591304010382279271601600761601141600557992314800374001002008000024034820016023248034816032316011451802011009910010080000800000100800000188007301019800146100005110217111601381800581308000024000080100160060160042160102160057160060
3202041600411286010011003400016016410615982525400258801002400428011680100240000800004426564010812279316901600801601191600597992738003540010020080000240000200160116480000160059160056218020110099100100800008000001008000021880057010168007361160025110117141600971800000108000024000080100160060160119160119160060160042
32020416006012860100010148880016004410615983825400106801002400428000080100240000800004557584000982279206301600401600411600597984325800414001002008000024017420016000048000016004116005621802011009910010080000800000100800590188007301301980000611320005149117111600561800581308000024000080100160100160042160121160102160060
320204160060128500100001328801160165166159873504002588010024000680058801002401688000048049940106722791234016004016017316010179909380041400670200800002401742001601164806961600591600561180201100991001008000080000010080057008007301097880014011400051231171116013518005813108000024000080100160101160042160060160177160118
3202041600591286010000312987920016002616615987625400106801002400068000080100240000800004804994000902279296501600401601181600597992838004140066820080000240000200160000480000160060160056118020110099100100800008000001008057020805330127753804726014200052801106641600791800001308000024000080100160060160060160060160060160057
3202041600591285000000001501016004100615987625400106801002400008000080100240000800004804994000912279296501600221600591600417992738002340010020080000240000200160000480000160041160056118020110099100100800008000011008000000800180101380013611318005110117111600380800000138000024000080100160060160042160042160060160057
32020416005912850000110025010160044060159838254001068010024000080000801002400008000048049940009122792965016004016005916005979927380041400100200800002400002001600004800001600591600561180201100991001008000080000010080000018800000001580015001400051101171116005618000013108000024000080100160060160042160042160042160060

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)0309l2 tlb miss data (0b)0e18191e1f2223243f4346494e51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
3200251600551241100011801001600991661598382540001680010240006801168006824000080000480049400085227893450160036160055160114799233800444000102080000240000201600004800001600561600551180021109101080000800001108000001380013001080013611017005020617146160052180058068000024000080010160042160056160056160114160056
320024160055124000100132000016004010615987225400016800682400068000080010240000800004800494000912279271601600361600551600417992325800374000102080000240000201600004806961600551600551180021109101080000800000108000001780013001380013011300050206171516160053080058068000024000080010160116160056160042160042160042
3200241601141241001013130000160026166159872254000168012624000680000800102400008000048004940008222792716016003616005516005579923158003740029420800002400002016000048072616005616004121800211091010800008000001080000013800130210800136112170250201517137160052080058068000024000080010160115160056160056160056160056
3200241601161240000235472640001601001661597231304004728024224007880232801842405048017443836640298422791000016015616023216023479824368001440114620820882460902016011648104416017316023341800211091010800008000001080114408024102289280126510000502015171516160052180000998000024000080010160056160056160056160056160042
320024160055124100000190000160040166159872254000168001024000680000800102400008000048004940008322792716016003616005516005579923380037400010208000024000020160000480000160055160041118002110910108000080000010800000080000001280009610170050201617156160052180000998000024000080010160056160056160056160056160042
32002416005512410000019010016004016615987225400016800102400068000080010240000800004800494000922278934501600361600551600557992338003740001020800002400002016000048000016005516005511800211091010800008000001080000013800131016800136112170050201117616160038080000908000024000080010160056160042160056160042160042
32002416005512400000030010016002610015987225400016800102400068000080010240000800004800494000832279271601600361600551600557992338003740001020800002400002016000048000016005516005511800211091010800008000001080000013800130016800136112130050207171413160052080000998000024000080010160042160042160042160056160056
320024160041124000000001001600401601598722540001680010240006800008001024000080000480049400088227927160160036160055160055799233800374000102080000240000201600004800001600551600551180021109101080000800000108000001380013001080012611300050201517146160052180000968000024000080010160056160056160056160056160056
32002416005512410000019010016004000015987225400016800102400068000080010240000800004800494000932279271601600361600551600417990938003740001020800002400002016000048000016005516005511800211091010800008000001080000013800101013800136112170050206171514160052180000998000024000080010160056160056160042160056160042
32002416005512410000000000160040166159872254000168001024000680000800102400008000048004940008822792716016003616004116004179923380037400010208000024000020160000480000160055160055118002110910108000080000110800000138001310128001261101700502015171515160052180000668000024000080010160042160042160056160042160056