Firestorm: LD4R (16B) measurements

Code:

  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.012

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.012

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
65005	29489	229	0	18	0	0	19	0	0	0	3	0	0	0	4681	28905	0	0	0	16980	5008	4012	1000	4000	1000	5000	47577	4	22903	29089	29285	3	10	5000	1000	4000	1000	4000	29114	29119	1	1	61001	1000	1000	0	1000	0	2	1000	0	0	0	0	1000	2	0	0	0	0	0	12882	9255	6911	3038	10	51	20326	3086	3817	9	55	49	28359	16492	13511	15083	1000	4000	29390	29334	29383	29435	29333
65004	29245	220	0	17	0	0	13	0	1	0	3	1	0	0	4568	28998	0	0	0	16963	5000	4012	1000	4000	1000	5000	47518	2	22936	29171	29372	3	10	5000	1000	4000	1000	4000	29158	29174	1	1	61001	1000	1000	0	1000	0	2	1000	0	0	0	3	1000	2	0	2	0	0	0	12859	9134	6818	3252	6	51	20236	3114	3821	16	56	54	28338	16014	14023	14476	1000	4000	29366	29254	29283	29347	29333
65004	29376	220	0	12	0	0	17	0	0	0	3	1	0	0	4600	28793	0	0	0	16937	5000	4008	1000	4000	1000	5000	47546	0	22880	29198	29315	3	10	5000	1000	4000	1000	4000	29268	29200	1	1	61001	1000	1000	0	1000	0	0	1000	0	0	0	0	1000	2	0	0	0	0	0	13477	9194	6901	3063	14	48	20233	3099	3817	13	56	46	28294	16250	14115	15165	1000	4000	29317	29382	29340	29371	29312
65004	29252	220	0	15	0	0	15	0	0	0	3	1	0	0	4648	28698	0	0	0	17086	5008	4012	1000	4000	1000	5000	47504	0	22862	29153	29341	3	10	5000	1000	4000	1000	4000	29227	29226	1	1	61001	1000	1000	0	1000	0	2	1000	0	0	0	0	1000	2	0	2	0	0	0	12874	9201	7003	3025	10	48	20248	3072	3824	11	53	49	28511	16381	13736	14999	1000	4000	29345	29464	29355	29423	29324
65004	29217	220	0	17	0	0	16	0	0	0	0	1	0	0	4562	28781	0	0	0	16994	5008	4008	1000	4000	1000	5000	47514	5	22918	29062	29273	3	10	5000	1000	4000	1000	4000	29129	29237	1	1	61001	1000	1000	0	1000	0	2	1001	0	0	0	0	1000	2	0	2	0	0	0	12924	9171	6821	3250	7	48	20169	3120	3815	8	52	48	28369	16380	13814	14488	1000	4000	29285	29316	29246	29362	29278
65004	29325	220	0	13	0	0	11	0	0	0	3	1	0	0	4573	28777	0	1	0	17032	5012	4008	1000	4000	1000	5000	47438	7	22888	29078	29370	3	10	5000	1000	4000	1000	4000	29208	29202	1	1	61001	1000	1000	0	1000	0	2	1000	0	0	0	0	1000	2	0	2	0	0	0	12912	9163	6838	3069	7	48	20308	3040	3813	12	53	56	28599	15712	13963	15134	1000	4000	29411	29324	29269	29360	29265
65004	29290	220	0	13	0	0	11	0	0	0	3	1	0	0	4646	28738	0	0	0	16966	5008	4008	1000	4000	1000	5000	47526	3	22854	29117	29384	3	10	5000	1000	4000	1000	4000	29153	29273	1	1	61001	1000	1000	0	1000	0	2	1000	0	0	0	0	1000	2	0	2	0	0	0	12833	9643	6821	3270	8	43	20256	3081	3818	14	54	53	28340	16122	14075	14861	1000	4000	29268	29331	29246	29338	29313
65004	29312	220	0	16	0	0	20	0	0	0	3	1	0	0	4919	28996	0	0	0	17007	5008	4008	1000	4000	1000	5000	47406	5	22883	29124	29259	3	10	5000	1000	4000	1000	4000	29208	29206	1	1	61001	1000	1000	0	1000	0	2	1000	0	0	0	0	1000	2	0	3	0	0	0	12837	9705	7062	3045	10	46	20342	3113	3820	8	51	49	28431	16392	14037	14539	1000	4000	29250	29351	29260	29361	29295
65004	29469	238	0	18	0	0	13	0	0	0	0	0	0	0	4545	28731	0	0	0	17024	5000	4012	1000	4000	1000	5000	47396	6	22873	29103	29360	3	10	5000	1000	4000	1000	4000	29265	29174	1	1	61001	1000	1000	0	1000	0	2	1000	0	0	0	0	1001	2	0	2	0	0	0	13499	9050	7038	3025	8	44	20246	3105	3818	17	52	58	28670	16294	13840	14580	1000	4000	29327	29312	29288	29358	29225
65004	29325	220	0	16	0	0	14	0	0	0	3	1	0	0	4870	28817	0	0	0	16973	5008	4008	1000	4000	1000	5000	47603	5	22843	29071	29286	3	10	5000	1000	4000	1000	4000	29104	29205	1	1	61001	1000	1000	0	1000	0	3	1000	0	0	0	0	1000	2	0	2	0	0	0	12784	9994	6799	3078	8	47	20298	3177	3816	12	63	45	28383	16550	13974	14440	1000	4000	29232	29264	29286	29300	29313

Count: 8

Code:

  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	80069	600	0	0	0	0	0	18	0	0	0	80039	1	6	6	25	400152	100	320052	80000	100	320000	80000	500	400010	7680008	1	80035	0	80054	80056	0	3	38	400100	200	80000	320000	200	80000	320000	80054	80055	1	1	80201	100	99	100	100	80000	80000	0	100	80000	15	80011	1	10	80011	6	0	11	15	0	0	0	0	5109	2	17	1	1	80051	0	6	6	80000	320000	100	80055	80042	80055	80055	80055
400204	80054	599	0	0	0	0	0	17	0	1	0	80039	1	0	6	25	400152	100	320052	80000	100	320000	80000	500	400000	7680008	1	80035	0	80054	80054	0	3	36	400100	200	80000	320000	200	80000	320000	80054	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	15	80011	0	11	80011	5	0	11	15	0	0	0	0	5109	1	17	1	1	80051	0	6	6	80000	320000	100	80055	80055	80055	80042	80055
400204	80041	600	0	0	0	0	0	17	0	1	0	80039	1	6	6	25	400100	100	320052	80000	100	320000	80000	500	400008	7680008	0	80035	0	80041	80054	0	3	36	400100	200	80000	320000	200	80000	320000	80041	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	15	80011	0	0	80011	6	0	11	15	0	0	0	0	5109	1	17	1	1	80051	1	6	6	80000	320000	100	80055	80055	80055	80055	80055
400204	80054	599	0	0	0	0	0	17	0	1	0	80039	1	6	6	25	400152	100	320052	80000	100	320180	80000	500	400021	7680008	0	80035	0	80054	80041	0	3	36	400100	200	80000	320000	200	80000	320000	80041	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	15	80011	0	0	80011	0	0	10	15	0	0	0	0	5109	1	17	1	1	80051	0	0	6	80000	320000	100	80042	80055	80055	80042	80042
400204	80054	600	0	0	0	0	0	0	0	1	0	80026	1	6	6	25	400152	100	320052	80000	100	320000	80000	500	400007	7680008	0	80035	0	80041	80054	0	3	36	400100	200	80000	320000	200	80000	320000	80056	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80010	0	13	80010	6	0	11	15	0	1	0	0	5109	1	17	1	1	80208	0	6	0	80000	320000	100	80772	80045	80042	80042	80042
400204	80054	599	0	0	0	0	0	16	0	1	0	80026	0	0	6	25	400152	100	320052	80000	100	320000	80000	500	400007	7680008	0	80035	3	80046	80054	0	3	36	400100	200	80000	320000	200	80000	320000	80054	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	15	80000	0	11	80011	0	0	0	0	0	0	0	0	5109	1	17	1	1	80051	1	6	6	80000	320000	100	80060	80055	80042	80055	80055
400204	80054	599	0	1	0	0	0	17	0	1	0	80039	1	6	6	25	400152	100	320000	80000	100	320000	80000	500	400000	7680008	0	80035	0	80054	80054	0	3	36	400100	200	80000	320000	200	80000	320000	80054	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	15	80011	1	0	80000	6	0	11	15	0	0	0	0	5109	1	17	1	1	80053	1	0	6	80000	320000	100	80055	80055	80055	80042	80057
400204	80041	600	0	0	0	0	0	0	0	1	0	80041	1	6	6	153	400100	100	320052	80000	100	320000	80000	500	400000	7680008	0	80035	0	80041	80054	0	3	23	400100	200	80000	320000	200	80000	320000	80054	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	15	80014	1	10	80011	6	0	11	15	0	0	0	0	5109	1	17	1	1	80051	0	6	6	80000	320000	100	80055	80055	80055	80057	80055
400204	80054	599	0	0	0	0	0	37	0	1	0	80039	1	0	6	25	400152	100	320052	80000	100	320000	80000	500	400007	3840000	0	80035	0	80054	80054	0	3	36	400100	200	80000	320000	200	80000	320000	80041	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	15	80011	0	0	80000	6	0	11	15	0	0	0	0	5109	1	17	1	1	80051	0	6	0	80000	320000	100	80057	80055	80055	80042	80055
400204	80054	600	0	0	0	0	0	0	0	1	0	80039	1	6	0	25	400152	100	320000	80000	100	320000	80000	500	400011	7680008	0	80022	0	80054	80054	0	3	23	400100	200	80000	320000	200	80000	320000	80054	80054	1	1	80201	100	99	100	100	80000	80000	1	100	80000	15	80011	0	10	80011	6	0	11	15	0	0	0	0	5109	1	17	1	1	80123	0	6	6	80000	320000	100	80055	80055	80055	80055	80055

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80460	602	1	0	1	1	0	1	0	1	0	0	31	176	1	0	0	0	80047	0	0	6	0	25	400062	10	320052	80000	10	320000	80000	50	400065	10240016	0	80043	80062	80047	0	3	44	400010	20	80000	320000	20	80000	320000	80062	80062	1	1	80021	10	9	10	10	80000	80000	1	10	80007	6	23	80027	0	0	1	26	80020	0	1	25	0	6	1	0	5019	0	21	17	5	16	80059	1	0	0	0	0	80000	320000	10	80063	80289	80331	80048	80063
400024	80062	599	1	0	1	0	0	1	0	0	0	0	7	0	1	0	0	1	80032	0	0	0	0	25	400062	10	320052	80000	10	320000	80000	50	400033	5440024	0	80098	80062	80100	0	3	44	400010	20	80000	320000	20	80000	320000	80062	80062	1	1	80021	10	9	10	10	80000	80000	0	10	80007	7	23	80028	0	1	1	6	80018	0	1	25	0	6	1	0	5019	0	8	17	8	17	80059	0	0	0	9	2	80000	320000	10	80063	80063	80063	80048	80063
400024	80062	600	1	0	1	1	0	1	0	0	0	0	32	0	1	0	0	0	80047	0	6	0	0	25	400062	10	320052	80000	10	320000	80000	50	400033	10240016	0	80043	80062	80062	0	3	29	400010	20	80000	320000	20	80000	320000	80062	80062	1	1	80021	10	9	10	10	80000	80000	0	10	80006	8	23	80007	0	0	1	7	80019	0	1	26	0	7	1	0	5019	0	18	17	8	17	80059	0	0	9	9	2	80000	320000	10	80048	80048	80063	80063	80063
400024	80062	599	1	0	1	1	0	0	0	0	0	0	6	0	1	0	0	0	80032	1	0	6	0	25	400058	10	320052	80000	10	320000	80000	50	400039	10240016	0	80028	80047	80062	0	3	29	400200	20	80000	320000	20	80000	320000	80062	80062	1	1	80021	10	9	10	10	80000	80000	0	10	80006	7	0	80028	0	2	2	26	80020	0	1	7	23	7	1	0	5019	0	17	17	18	6	80059	0	0	9	9	0	80000	320000	10	80048	80063	80063	80063	80063
400024	80062	600	1	0	1	1	0	1	0	0	0	0	95	0	1	0	0	1	80047	0	6	6	0	25	400062	10	320048	80000	10	320000	80000	50	400002	10240016	0	80043	80047	80062	0	3	44	400010	20	80000	320000	20	80000	320000	80062	80062	1	1	80021	10	9	10	10	80000	80000	0	10	80008	7	23	80027	0	0	1	38	80020	6	0	27	23	7	0	0	5019	0	6	17	17	8	80044	0	0	9	9	2	80000	320000	10	80048	80048	80063	80063	80048
400024	80062	599	1	0	0	0	0	0	0	0	0	0	31	0	1	0	0	0	80032	1	0	6	0	25	400034	10	320048	80000	10	320000	80000	50	400003	5440028	0	80028	80062	80047	0	3	29	400010	20	80000	320000	20	80000	320000	80062	80062	1	1	80021	10	9	10	10	80000	80000	1	10	80007	8	24	80026	0	0	0	26	80018	6	1	7	0	7	2	0	5019	0	12	17	17	17	80044	1	0	9	9	0	80000	320000	10	80048	80063	80063	80048	80048
400024	80062	601	1	0	1	1	0	1	0	0	0	0	7	0	0	0	0	0	80047	0	0	0	0	25	400058	10	320048	80000	10	320000	80000	50	400039	5440028	0	80043	80062	80062	0	3	29	400010	20	80000	320000	20	80000	320000	80062	80048	1	1	80021	10	9	10	10	80000	80000	1	10	80007	7	24	80028	0	0	0	29	80020	6	1	26	24	7	0	0	5019	0	6	17	6	17	80044	0	0	9	9	0	80000	320000	10	80063	80063	80063	80063	80048
400024	80062	600	1	0	1	1	0	1	0	0	0	0	31	0	1	0	0	1	80047	0	6	0	0	25	400034	10	320052	80000	10	320000	80000	50	400039	10240016	0	80043	80062	80062	0	3	44	400010	20	80000	320000	20	80000	320000	80062	80062	1	1	80021	10	9	10	10	80000	80000	0	10	80007	8	24	80026	0	0	0	26	80018	0	1	25	0	6	0	0	5019	0	17	17	17	17	80059	0	0	9	0	2	80000	320000	10	80048	80063	80063	80063	80063
400024	80047	599	1	0	1	1	0	1	0	0	0	0	32	0	1	0	0	0	80032	1	6	6	0	25	400058	10	320052	80000	10	320000	80000	50	400040	10240016	0	80043	80062	80062	0	3	44	400010	20	80000	320000	20	80000	320000	80062	80062	1	1	80021	10	9	10	10	80000	80000	0	10	80008	8	23	80058	1	0	0	26	80020	0	1	26	23	7	1	0	5019	0	6	17	17	8	80044	0	0	9	9	2	80000	320000	10	80063	80048	80048	80063	80063
400024	80047	600	1	0	1	1	0	0	1	0	0	0	7	0	1	0	0	0	80032	1	6	6	0	25	400062	10	320024	80000	10	320000	80000	50	400033	10240016	0	80043	80062	80047	0	3	29	400010	20	80000	320000	20	80000	320000	80062	80062	1	1	80021	10	9	10	10	80000	80000	0	10	80009	7	24	80025	0	0	0	6	80018	6	1	26	24	7	1	0	5019	0	16	17	6	17	80059	1	0	9	0	2	80000	320000	10	80063	80063	80063	80063	80063

LD4R (16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations