Firestorm: LD4R (1D) measurements

Code:

  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.012

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.012

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
66005	29285	219	3	1	0	1	0	0	38	1	0	4584	28963	0	0	0	16866	6008	4000	2000	4000	2000	10003	47576	5	0	0	23013	29100	29065	3	10	6000	2000	4000	2000	8000	29125	29111	1	1	61001	1000	1000	0	2000	0	4	2000	0	1	0	1	2002	2	0	6	0	0	13137	9122	6928	3141	46	20097	3068	3810	9	40	36	28389	16379	13582	14988	2000	4000	29085	29291	29274	29206	29224
66004	29276	218	0	1	1	1	1	0	38	1	0	4610	28869	0	0	1	16843	6016	4004	2000	4000	2000	10000	47564	7	0	0	22957	29037	29164	3	10	6000	2000	4000	2000	8000	29024	29025	1	1	61001	1000	1000	0	2002	4	6	2006	0	0	0	6	2002	4	4	6	2	2	12763	9392	6879	3040	32	19911	3012	3813	6	32	34	28409	16410	13181	14959	2000	4000	29239	29241	29281	29139	29154
66004	29169	219	0	1	0	1	0	0	332	1	0	4558	28784	0	0	1	16794	6004	4020	2000	4000	2000	10002	47620	12	0	0	22993	29059	29243	3	10	6000	2000	4000	2000	8000	29167	29072	1	1	61001	1000	1000	0	2003	3	6	2003	0	0	1	6	2000	4	2	0	2	1	12912	9266	6894	3086	38	20037	3039	3813	9	37	37	28407	16031	13336	14775	2000	4000	29230	29251	29215	29213	29172
66004	29243	218	0	1	1	1	0	0	431	1	0	4559	28782	0	0	0	16821	6016	4016	2000	4000	2000	10000	47576	13	0	0	23037	29157	29296	3	10	6000	2000	4000	2000	8000	29265	29059	1	1	61001	1000	1000	0	2003	3	6	2003	0	1	1	6	2000	4	2	0	2	2	12998	9166	6882	3104	38	20000	3042	3820	10	37	34	28369	16530	13344	14780	2000	4000	29157	29264	29214	29211	29244
66004	29286	219	1	1	1	1	0	0	2	0	0	4620	28763	0	2	0	16917	6012	4016	2000	4000	2000	10000	47544	6	0	0	23010	29057	29275	3	10	6000	2000	4000	2000	8000	29064	29085	1	1	61001	1000	1000	0	2004	3	4	2004	0	0	2	2	2000	4	4	6	2	0	12838	9214	6919	3033	37	20043	3056	3810	7	40	38	28455	16166	13227	14948	2000	4000	29244	29211	29349	29327	29211
66004	29080	219	1	1	0	1	0	0	479	0	0	4612	28823	2	0	0	16815	6012	4020	2000	4000	2000	10000	47594	6	0	0	23018	29082	29191	3	10	6000	2000	4000	2000	8000	29134	29080	1	1	61001	1000	1000	0	2002	3	6	2003	1	0	0	2	2000	4	2	4	2	0	12907	9257	6885	3032	41	20055	3041	3821	12	41	33	28326	16420	13297	14837	2000	4000	29302	29309	29216	29391	29153
66004	29240	219	0	1	1	0	0	0	41	1	0	4617	28818	0	0	0	16855	6004	4012	2000	4000	2000	10000	47580	6	0	0	23029	29074	29165	3	10	6000	2000	4000	2000	8000	29101	29038	1	1	61001	1000	1000	0	2003	4	6	2003	1	0	0	2	2000	4	4	6	2	0	12971	9182	6862	3043	32	20039	3104	3818	4	36	37	28331	16391	13301	14764	2000	4000	29277	29239	29256	29225	29199
66004	29157	218	0	1	1	1	0	0	317	0	0	4586	28865	2	0	0	16807	6012	4004	2000	4000	2000	10000	47662	11	0	0	23014	29067	29248	3	10	6000	2000	4000	2000	8000	29206	29005	1	1	61001	1000	1000	0	2004	2	4	2002	0	0	0	2	2000	4	2	4	2	0	13043	9184	6850	3063	32	20044	3127	3820	11	35	39	28406	16228	13333	15084	2000	4000	29191	29171	29167	29197	29166
66004	29241	219	0	1	1	1	0	0	472	1	0	4580	28793	0	0	0	16922	6012	4016	2000	4000	2000	10000	47450	5	0	0	22987	29048	29170	3	10	6000	2000	4000	2000	8000	29109	29062	1	1	61001	1000	1000	1	2002	3	6	2005	0	0	1	4	2000	0	4	0	2	1	12837	9139	6878	3129	36	20159	3085	3822	8	41	35	28356	16427	13520	14758	2000	4000	29251	29190	29239	29226	29184
66004	29264	219	0	1	1	0	0	0	7	1	0	4604	28849	2	2	0	16830	6004	4020	2000	4000	2000	10000	47558	5	0	0	22995	28988	29209	3	10	6000	2000	4000	2000	8000	29059	29048	1	1	61001	1000	1000	1	2003	3	4	2004	0	0	0	2	2000	4	6	4	2	0	12884	9153	6837	3047	44	20053	3135	3814	7	39	38	28384	16299	13365	14704	2000	4000	29176	29257	29242	29123	29442

Count: 8

Code:

  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480205	80065	600	1	1	0	1	1	0	21	0	0	2	80050	2	16	16	1	0	25	480124	100	320024	160000	100	320000	160000	500	800964	5440024	1	80046	80047	80065	0	0	3	47	480100	200	160000	320000	200	160000	640000	80065	80065	1	1	80201	100	99	100	100	80000	80000	0	100	160014	14	42	0	160051	1	0	1	12	160038	6	0	51	42	12	0	0	5109	1	17	1	1	80044	0	9	0	160000	320000	100	80066	80066	80066	80048	80048
480204	80065	600	1	1	0	0	0	0	56	0	0	2	80032	2	16	0	0	0	25	480176	100	320060	160000	100	320000	160000	500	800964	10880152	1	80028	80065	80065	0	0	3	47	480100	200	160000	320000	200	160000	640000	80047	80065	1	1	80201	100	99	100	100	80000	80000	0	100	160014	15	42	0	160051	0	0	0	51	160000	6	1	13	42	13	0	0	5109	1	17	1	1	80044	9	9	2	160000	320000	100	80066	80066	80048	80048	80048
480204	80065	599	1	1	1	0	0	0	57	1	0	2	80032	3	16	0	1	0	25	480168	100	320024	160000	100	320000	160000	500	800970	10880156	1	80046	80065	80065	0	0	3	29	480100	200	160000	320000	200	160000	640000	80065	80065	1	1	80201	100	99	100	100	80000	80000	0	100	160014	13	0	0	160013	0	0	0	53	160038	6	1	13	0	12	0	0	5109	1	17	1	1	80044	9	9	2	160000	320000	100	80048	80048	80066	80048	80048
480204	80047	600	1	0	1	0	0	0	57	1	0	2	80032	2	16	16	1	0	25	480168	100	320068	160000	100	320000	160000	500	800970	10880152	1	80046	80065	80065	0	0	3	29	480100	200	160000	320000	200	160000	640000	80065	80047	1	1	80201	100	99	100	100	80000	80000	0	100	160013	12	42	0	160052	0	0	0	51	160038	6	1	51	42	13	1	0	5109	1	17	1	1	80062	9	9	0	160000	320000	100	80066	80066	80066	80066	80066
480204	80065	599	1	1	1	0	0	0	66	0	0	2	80032	2	0	16	0	0	25	480168	100	320024	160000	100	320000	160000	500	800970	10880152	1	80046	80065	80047	0	0	3	47	480100	200	160000	320000	200	160000	640000	80047	80047	1	1	80201	100	99	100	100	80000	80000	0	100	160014	14	0	0	160012	0	0	0	13	160038	6	1	50	42	12	2	0	5109	1	17	1	1	80062	9	0	0	160000	320000	100	80066	80066	80048	80066	80048
480204	80047	599	1	1	0	0	0	0	57	0	0	2	80050	0	16	0	1	0	25	480124	100	320024	160000	100	320000	160000	500	800042	10880152	0	80028	80047	80047	0	0	3	47	480100	200	160000	320000	200	160000	640000	80065	80065	1	1	80201	100	99	100	100	80000	80000	0	100	160014	14	0	0	160051	0	0	2	51	160038	6	0	50	42	13	1	0	5109	1	17	1	1	80062	0	9	2	160000	320000	100	80048	80066	80048	80048	80066
480204	80047	600	1	1	1	0	0	0	57	1	0	2	80050	2	0	16	0	0	25	480160	100	320028	160000	100	320000	160000	500	800042	10880152	1	80028	80065	80065	0	0	3	47	480100	200	160000	320000	200	160000	640000	80048	80065	1	1	80201	100	99	100	100	80000	80000	0	100	160014	14	42	0	160051	0	0	0	51	160038	6	0	51	0	13	0	0	5109	1	17	1	1	80044	0	9	2	160000	320000	100	80048	80066	80066	80066	80066
480204	80047	600	1	0	1	0	1	1	57	0	0	2	80032	2	16	0	1	0	25	480172	100	320076	160000	100	320000	160000	500	801083	10880152	1	80046	80065	80065	0	0	57	29	480100	200	160000	320000	200	160000	640000	80065	80065	1	1	80201	100	99	100	100	80000	80000	0	100	160013	13	42	5	160052	0	0	3	1122	160298	0	0	51	0	13	2	0	5109	1	17	1	1	80062	0	9	2	160000	320000	100	80048	80048	80066	80066	80066
480204	80065	599	1	1	1	0	0	0	13	1	0	2	80032	0	0	16	1	0	25	480168	100	320068	160000	100	320296	160000	500	800959	10880152	1	80046	80065	80065	0	0	3	47	480100	200	160000	320000	200	160000	640000	80047	80065	1	1	80201	100	99	100	100	80000	80000	0	100	160014	13	42	0	160051	0	0	1	50	160038	6	0	51	42	13	2	0	5109	1	17	1	1	80062	9	0	0	160000	320000	100	80066	80048	80066	80066	80066
480204	80047	600	1	1	0	0	1	0	69	0	0	2	80050	2	16	16	0	0	25	480168	100	320024	160000	100	320000	160000	500	800970	10880152	1	80028	80065	80065	0	0	3	47	480100	200	160000	320000	200	160000	640000	80065	80065	2	1	80201	100	99	100	100	80000	80000	0	100	160012	13	42	0	160314	1	0	3	13	160000	6	1	50	42	13	0	0	5109	1	17	1	1	80062	9	0	2	160000	320000	100	80066	80066	80048	80066	80048

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	22	23	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480025	80060	599	0	0	1	0	0	1	0	58	0	0	2	80054	2	0	0	0	25	480086	10	320084	160000	10	320000	160000	50	801179	10880752	0	80050	0	80069	80069	0	3	51	480010	20	160000	320000	20	160000	640000	80047	80069	1	1	80021	10	9	10	10	80000	80000	0	10	160013	14	43	160014	0	2	13	160000	6	0	13	0	13	1	0	5019	0	2	17	7	4	80066	13	0	5	160000	320000	10	80070	80070	80070	80071	80070
480024	80069	600	1	0	0	0	1	0	0	58	0	0	0	80032	2	5	0	5	25	480034	10	320024	160000	10	320000	160000	50	800071	10880752	1	80028	0	80069	80069	3	3	29	480010	20	160000	320000	20	160000	640000	80047	80069	1	1	80021	10	9	10	10	80000	80000	0	10	160014	15	43	160052	0	1	13	160000	6	1	52	0	13	0	0	5019	0	3	17	3	3	80066	0	0	5	160000	320000	10	80071	80048	80070	80071	80070
480024	80047	600	1	1	0	1	1	1	0	58	0	0	2	80054	2	5	5	0	25	480070	10	320024	160000	10	320000	160000	50	801181	5440032	1	80050	0	80069	80070	0	3	51	480010	20	160000	320000	20	160000	640000	80069	80047	1	1	80021	10	9	10	10	80000	80000	1	10	160013	14	43	160052	0	1	12	160039	6	0	52	43	12	0	0	5019	0	4	17	3	4	80066	13	13	5	160000	320000	10	80048	80070	80048	80070	80070
480024	80069	599	1	1	0	1	1	0	0	13	1	0	2	80054	2	0	5	0	25	480082	10	320024	160000	10	320000	160000	50	801179	10880752	0	80051	0	80047	80047	3	3	51	480010	20	160000	320000	20	160000	640000	80069	80069	1	1	80021	10	9	10	10	80000	80000	0	10	160014	12	43	160053	0	2	60	160039	6	1	12	43	13	0	0	5019	0	4	17	5	5	80066	13	13	0	160000	320000	10	80070	80070	80070	80070	80070
480024	80166	600	1	1	1	1	1	0	0	19	1	0	2	80054	0	5	5	0	25	480082	10	320024	160000	10	320000	160000	50	800048	10880752	1	80050	0	80047	80069	3	3	51	480010	20	160000	320000	20	160000	640000	80047	80069	1	1	80021	10	9	10	10	80000	80000	0	10	160013	13	43	160013	0	1	52	160000	6	1	52	43	13	0	0	5019	0	4	17	4	4	80066	13	13	5	160000	320000	10	80070	80070	80070	80048	80048
480024	80069	599	1	1	1	1	0	0	0	58	0	0	2	80054	2	5	5	5	25	480034	10	320072	160000	10	320000	160000	50	801187	5760028	0	80050	0	80069	80069	0	3	51	480010	20	160000	320000	20	160000	640000	80069	80069	1	1	80021	10	9	10	10	80000	80000	0	10	160014	13	43	160053	0	0	52	160039	6	1	51	0	13	1	0	5019	0	5	17	5	5	80066	13	0	4	160000	320000	10	80050	80070	80048	80070	80070
480024	80069	600	1	1	1	1	0	0	0	58	0	0	0	80032	2	0	0	5	25	480082	10	320064	160000	10	320000	160000	50	801183	10880752	1	80050	0	80069	80069	3	3	51	480010	20	160000	320000	20	160000	640000	80069	80069	1	1	80021	10	9	10	10	80000	80000	0	10	160013	14	43	160053	0	1	52	160039	0	1	52	43	13	0	0	5019	0	4	17	3	3	80066	13	13	0	160000	320000	10	80070	80070	80048	80070	80070
480024	80047	600	1	1	0	1	1	1	0	12	1	0	2	80033	2	5	5	5	25	480086	10	320024	160000	10	320000	160000	50	801181	10880752	1	80050	0	80069	80069	3	3	51	480010	20	160000	320000	20	160000	640000	80047	80069	1	1	80021	10	9	10	10	80000	80000	0	10	160015	15	0	160052	1	1	52	160000	6	1	52	43	13	0	0	5019	0	5	17	4	4	80066	13	13	5	160000	320000	10	80070	80048	80070	80070	80070
480024	80069	600	1	1	0	0	0	0	0	57	0	0	2	80054	2	5	5	5	45	480034	10	320064	160000	10	320000	160000	50	800042	10880752	0	80050	0	80069	80069	3	3	51	480010	20	160000	320000	20	160000	640000	80069	80069	1	1	80021	10	9	10	10	80000	80000	0	10	160012	13	43	160052	0	1	51	160039	6	1	52	43	13	0	0	5019	0	4	17	5	5	80044	13	0	4	160000	320000	10	80070	80048	80070	80070	80048
480024	80047	600	1	1	0	1	1	0	0	57	0	0	2	80054	2	5	0	5	25	480034	10	320072	160000	10	320000	160000	50	800040	10880752	1	80050	0	80069	80069	3	3	51	480010	20	160000	320000	20	160000	640000	80069	80069	1	1	80021	10	9	10	10	80000	80000	1	10	160012	13	43	160052	1	0	52	160000	0	1	52	43	12	1	0	5019	0	5	17	3	3	80066	13	0	0	160000	320000	10	80070	80070	80070	80048	80070

LD4R (1D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations