Firestorm: LD4R (2D) measurements

Code:

  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.012

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.012

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
66005	29408	220	0	29	0	0	21	0	1	0	0	0	0	4554	28793	0	0	0	16876	6012	4016	2000	4000	2000	10000	47618	6	23019	29151	29452	3	10	6000	2000	4000	2000	8000	29180	29156	1	1	61001	1000	1000	1	2000	6	2002	0	2	2002	4	0	6	12938	9190	6811	3030	13	87	19962	3089	3808	12	61	57	28405	16118	13046	15015	2000	4000	29252	29279	29241	29393	29241
66004	29208	219	0	24	0	0	25	0	0	0	7	0	0	4525	28749	0	0	0	16828	6012	4012	2000	4000	2000	10000	47816	7	23027	29038	29237	3	10	6000	2000	4000	2000	8000	29193	29170	1	1	61001	1000	1000	1	2000	0	2000	0	5	2000	0	2	4	12836	9106	6805	3045	10	53	20111	3076	3805	15	55	59	28386	16190	13449	14826	2000	4000	29293	29233	29233	29280	29225
66004	29251	219	0	25	0	0	29	0	0	0	0	1	0	4604	28924	0	0	0	16903	6012	4000	2000	4000	2000	10000	47576	4	22990	29133	29228	3	10	6000	2000	4000	2000	8000	29140	29179	1	1	61001	1000	1000	1	2000	6	2002	1	2	2002	4	2	6	12923	9038	6802	3070	11	60	20147	3087	3815	18	61	56	28452	16471	13313	14985	2000	4000	29313	29128	29262	29260	29309
66004	29350	220	0	23	0	0	18	0	0	0	6	0	0	4553	28812	0	2	0	16942	6012	4016	2000	4000	2000	10000	47598	7	23003	29196	29357	3	10	6000	2000	4000	2000	8000	29177	29094	1	1	61001	1000	1000	0	2000	6	2002	0	2	2000	4	0	6	12774	9105	6846	2986	10	65	20090	3104	3815	15	53	58	28391	16421	13256	14927	2000	4000	29206	29263	29217	29209	29367
66004	29234	219	0	24	0	0	24	0	0	0	8	0	0	4469	28725	0	0	2	16860	6012	4012	2000	4000	2000	10000	47602	3	22993	29131	29294	3	10	6000	2000	4000	2000	8000	29056	29142	1	1	61001	1000	1000	1	2000	6	2000	0	2	2002	0	0	6	12801	9076	6829	3011	11	62	20131	3063	3806	15	60	58	28424	16457	13298	14934	2000	4000	29163	29296	29227	29296	29330
66004	29289	219	0	23	0	0	24	0	0	0	6	0	0	4537	28808	0	2	0	16913	6012	4012	2000	4000	2000	10000	47600	6	22989	29066	29244	3	10	6000	2000	4000	2000	8000	29209	29157	1	1	61001	1000	1000	1	2000	6	2000	0	0	2002	0	0	6	12991	9212	6849	3032	9	55	20065	3054	3809	13	65	64	28417	16247	13476	14832	2000	4000	29272	29287	29356	29256	29371
66004	29259	219	0	25	0	0	18	0	0	0	15	0	0	4604	28759	0	0	2	16874	6008	4012	2000	4000	2000	10003	47426	3	22955	28994	29143	3	10	6000	2000	4000	2000	8000	29130	29047	1	1	61001	1000	1000	1	2000	6	2002	0	3	2000	4	0	6	12977	9026	6864	3035	8	64	20066	3084	3809	11	53	56	28397	16293	13227	14826	2000	4000	29251	29238	29287	29341	29214
66004	29254	219	0	21	0	0	24	0	0	1	7	0	0	4581	28851	0	0	0	16867	6008	4012	2000	4000	2000	10000	47647	9	23038	29027	29239	3	10	6000	2000	4000	2000	8000	28727	29133	1	1	61001	1000	1000	1	2000	6	2000	0	0	2004	4	2	6	12887	9122	6794	3113	8	58	20044	3050	3815	14	60	56	28388	16277	13140	14801	2000	4000	29314	29352	29281	29277	29197
66004	29315	219	0	25	0	0	19	0	0	0	7	1	0	4602	28824	0	2	0	16929	6012	4008	2000	4000	2000	10000	47612	8	23007	29104	29319	3	10	6000	2000	4000	2000	8000	29124	29025	1	1	61001	1000	1000	1	2000	6	2000	0	2	2004	4	2	6	12876	9023	6782	3095	10	58	20175	3045	3816	13	68	62	28510	16149	13354	14866	2000	4000	29254	29284	29328	29354	29232
66004	29214	219	0	30	0	0	18	0	0	0	8	0	0	4573	28742	0	2	0	16983	6008	4012	2000	4000	2000	10000	47516	3	22993	28995	29254	3	10	6006	2000	4000	2000	8000	29158	29119	1	1	61001	1000	1000	1	2000	4	2000	0	0	2002	0	0	0	12763	9259	6900	3095	9	65	20189	3043	3813	10	59	60	28446	16220	13287	14609	2000	4000	29262	29201	29350	29299	29237

Count: 8

Code:

  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480205	80069	600	0	0	0	0	0	0	0	1	0	0	80026	2	12	0	0	25	480184	100	320084	160000	100	320000	160000	500	800000	9600000	1	80041	80060	80064	0	0	3	42	480100	200	160000	320000	200	160000	640000	80041	80060	1	1	80201	100	99	100	100	80000	80000	0	100	160013	13	43	0	160052	0	0	1	52	160000	6	1	0	0	0	5109	1	17	1	1	80061	0	0	0	10	160000	320000	100	80061	80042	80065	80065	80065
480204	80060	599	0	0	0	0	0	42	0	0	0	2	80050	0	0	0	0	25	480184	100	320084	160000	100	320000	160000	500	800886	5029876	0	80045	80064	80041	0	0	3	46	480100	200	160000	320000	200	160000	640000	80060	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160013	14	43	0	160052	0	0	2	12	160039	0	0	32	35	0	5109	1	17	1	1	80041	1	0	0	0	160000	320000	100	80065	80065	80065	80065	80061
480204	80064	600	0	0	1	0	0	0	0	0	0	2	80049	2	12	0	0	25	480184	100	320084	160000	100	320000	160000	500	800402	9600000	0	80041	80064	80064	0	0	3	42	480100	200	160000	320000	200	160000	640000	80041	80210	2	1	80201	100	99	100	100	80000	80000	1	100	160000	0	35	0	160036	0	0	0	36	160036	6	1	0	35	0	5109	1	17	1	1	80038	0	0	14	14	160000	320000	100	80065	80042	80042	80065	80061
480204	80064	599	0	0	0	0	0	42	0	1	0	2	80045	2	0	0	0	25	480184	100	320084	160000	100	320000	160000	500	800853	10879996	0	80022	80064	80041	0	0	3	23	480100	200	160000	320000	200	160000	640000	80060	80060	1	1	80201	100	99	100	100	80000	80000	1	100	160000	0	0	0	160036	0	1	0	35	160036	6	0	32	40	0	5109	1	17	1	1	80038	0	0	7	14	160000	320000	100	80065	80065	80065	80065	80065
480204	80041	600	0	0	0	0	0	42	0	0	0	0	80026	0	12	12	0	25	480176	100	320000	160000	100	320000	160000	500	800853	3840000	1	80022	80064	80064	0	0	3	26	480100	200	160000	320000	200	160000	640000	80041	80060	1	1	80201	100	99	100	100	80000	80000	1	100	160000	0	35	0	160036	0	0	0	36	160036	6	1	36	40	0	5109	1	17	1	1	80038	0	0	14	14	160000	320000	100	80061	80065	80042	80065	80042
480204	80064	599	0	0	0	0	0	42	0	0	0	2	80026	2	15	12	0	25	480184	100	320084	160000	100	320000	160000	500	800853	3840000	0	80045	80064	80064	0	0	3	46	480100	200	160000	320000	200	160000	640000	80041	80060	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	0	160000	0	1	0	32	160036	0	0	36	40	0	5109	1	17	1	1	80061	1	0	0	10	160000	320000	100	80061	80061	80065	80065	80061
480204	80041	600	0	0	0	0	0	38	0	0	0	0	80045	2	12	0	0	25	480184	100	320000	160000	100	320000	160000	500	800377	9600004	0	80022	80065	80064	0	0	3	46	480100	200	160152	320000	200	160000	640000	80064	80060	1	1	80201	100	99	100	100	80000	80000	1	100	160000	0	0	0	160036	0	0	0	36	160036	6	1	32	35	0	5109	1	17	1	1	80142	0	0	0	10	160000	320000	100	80065	80065	80065	80065	80152
480204	80064	600	0	0	0	0	0	42	0	0	0	2	80049	2	0	0	0	25	480184	100	320076	160000	100	320000	160000	500	800377	9600000	1	80045	80064	80041	0	0	3	42	480100	200	160000	320000	200	160000	640000	80064	80060	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	0	160036	0	0	0	0	160036	6	1	0	35	0	5109	1	17	1	1	80061	0	0	14	14	160000	320000	100	80065	80065	80042	80065	80065
480204	80064	600	0	0	0	0	0	0	0	1	0	2	80049	0	0	12	0	25	480184	100	320000	160000	100	320000	160000	500	800377	10879996	1	80045	80064	80064	0	0	3	23	480100	200	160000	320000	200	160000	640000	80060	80060	1	1	80201	100	99	100	100	80000	80000	1	100	160000	0	0	0	160036	0	0	0	36	160000	6	1	32	0	1	5109	1	17	1	1	80041	0	0	14	14	160000	320000	100	80065	80065	80065	80065	80042
480204	80064	600	0	0	0	0	0	87	0	1	0	0	80049	0	12	12	0	25	480184	100	320084	160518	100	320000	160000	500	800853	10879996	0	80022	80041	80041	0	0	3	46	480100	200	160000	320000	200	160000	640000	80064	80060	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	0	160036	0	2	0	39	160036	6	1	36	35	0	5109	1	17	1	1	80061	0	0	0	0	160000	320000	100	80065	80065	80042	80065	80061

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	23	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480025	80056	600	1	1	1	30	0	0	80041	2	12	12	25	480086	10	320076	160000	10	320000	160000	50	800221	4133364	1	80037	80056	80056	0	3	38	480010	20	160000	320000	20	160000	640000	80056	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	27	160024	0	24	160000	6	0	0	0	0	0	0	5019	24	17	22	12	80038	1	0	6	160000	320000	10	80057	80057	80057	80057	80057
480024	80056	599	0	0	0	39	1	0	80026	2	12	12	25	480070	10	320000	160000	10	320000	160000	50	800000	8320000	1	80037	80056	80056	0	3	42	480010	20	160000	320000	20	160000	640000	80056	80056	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	160000	0	27	160024	0	1	24	27	0	0	0	5019	22	17	19	24	80053	1	6	6	160000	320000	10	80045	80057	80043	80057	80057
480024	80055	600	0	0	0	0	0	0	80026	2	12	0	25	480070	10	320060	160000	10	320000	160000	50	800219	8320000	1	80022	80056	80055	0	3	38	480010	20	160000	320000	20	160000	640000	80056	80056	1	1	80021	10	9	10	10	80000	80000	1	10	160000	0	160024	0	0	160024	6	1	24	27	0	0	0	5019	23	17	20	24	80053	1	6	6	160000	320000	10	80057	80057	80057	80057	80057
480024	80041	600	0	1	1	30	1	0	80026	2	12	12	25	480070	10	320060	160000	10	320000	160000	50	800216	3840000	1	80037	80056	80041	0	3	38	480010	20	160000	320000	20	160000	640000	80056	80056	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	160024	0	0	160024	6	1	24	27	0	0	0	5019	23	17	22	23	80041	1	0	6	160000	320000	10	80057	80057	80057	80042	80042
480024	80056	599	0	0	0	30	1	0	80120	2	12	12	25	480070	10	320060	160000	10	320000	160000	50	800219	8320004	0	80022	80056	80041	0	3	38	480010	20	160000	320000	20	160000	640000	80041	80056	1	1	80021	10	9	10	10	80000	80000	1	10	160000	27	160024	0	24	160000	6	0	24	0	1	0	1	5019	25	17	20	25	80053	1	6	0	160000	320000	10	80057	80057	80061	80057	80042
480025	80056	599	0	0	0	0	1	0	80041	2	12	0	25	480224	10	320060	160000	10	320000	160000	50	800222	8320000	0	80022	80056	80056	8	3	38	480010	20	160000	320000	20	160000	640000	80056	80056	1	1	80021	10	9	10	10	80000	80000	1	10	160000	27	160024	0	24	160024	6	1	24	27	0	0	0	5019	25	17	21	25	80053	1	85	0	160000	320000	10	80057	80057	80057	80057	80057
480024	80056	600	0	0	0	30	0	0	80032	2	12	0	25	480070	10	320060	160000	10	320000	160000	50	800219	3840000	0	80037	80056	80056	0	3	38	480010	20	160000	320000	20	160000	640000	80056	80056	1	1	80021	10	9	10	10	80000	80000	0	10	160000	27	160024	1	27	160000	6	1	24	27	0	0	0	5019	12	17	25	20	80038	1	108	6	160000	320000	10	80057	80057	80057	80057	80057
480024	80056	599	0	0	0	30	1	0	80041	2	12	12	25	480070	10	320000	160000	10	320000	160000	50	800000	8320000	0	80037	80056	80041	0	3	42	480010	20	160000	320000	20	160000	640000	80056	80041	1	1	80021	10	9	10	10	80000	80000	1	10	160000	27	160024	0	24	160024	6	1	0	27	0	0	0	5019	25	17	24	24	80038	1	70	0	160000	320000	10	80042	80057	80057	80042	80042
480024	80056	600	0	0	0	30	1	0	80026	2	12	0	25	480070	10	320060	160000	10	320000	160000	50	800000	8320004	0	80037	80198	80056	0	3	38	480010	20	160000	320000	20	160000	640000	80056	80056	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	160000	0	0	160024	0	1	24	27	0	0	0	5019	25	17	24	24	80053	1	70	0	160000	320000	10	80042	80057	80057	80057	80057
480024	80041	600	0	0	0	0	1	0	80026	2	12	12	25	480070	10	320056	160000	10	320000	160000	50	800217	8320000	0	80037	80056	80056	0	3	38	480010	20	160000	320000	20	160000	640000	80056	80056	1	1	80021	10	9	10	10	80000	80000	0	10	160000	27	160024	0	24	160024	6	1	24	27	0	0	0	5019	25	17	25	25	80053	1	91	0	160000	320000	10	80057	80042	80057	80057	80057

LD4R (2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations