Firestorm: LD4R (2S) measurements

Code:

  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.012

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.012

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
65005	29263	219	0	21	0	0	14	0	0	1	0	0	5	0	0	0	4586	28879	0	0	0	17009	5016	4016	1000	4000	1000	5000	47514	0	22865	29082	29218	3	10	5000	1000	4000	1000	4000	29060	29232	1	1	61001	1000	1000	1	1000	0	2	1000	0	0	0	0	1001	2	1	2	1	2	12974	9093	6910	3063	7	52	20220	3084	3816	14	44	36	28336	16063	13886	14787	1000	4000	29282	29264	29297	29376	29337
65004	29284	220	1	11	1	1	11	1	0	0	0	0	5	0	0	0	4578	28829	0	1	0	16983	5016	4000	1000	4000	1000	5000	47577	8	22923	29140	29250	3	10	5000	1000	4000	1000	4008	29175	29098	1	1	61001	1000	1000	0	1000	0	3	1002	0	0	0	3	1001	0	1	0	0	0	12797	9106	6844	3060	9	48	20170	3105	3816	11	45	44	28400	16252	13975	14988	1000	4000	29222	29244	29280	29329	29274
65004	29332	220	1	14	0	1	15	1	0	0	0	3	6	0	0	0	4566	28858	0	1	0	16980	5008	4016	1000	4000	1000	5001	47595	3	22914	29150	29180	3	10	5000	1000	4000	1000	4000	29148	29186	1	1	61001	1000	1000	0	1002	3	3	1002	0	0	2	1	1000	3	2	3	1	1	12985	9083	6826	3012	8	54	20190	3111	3818	15	45	38	28360	16347	14028	14985	1000	4000	29263	29294	29344	29347	29246
65004	29405	219	0	13	0	0	11	0	0	0	0	0	8	0	1	0	4562	28822	0	0	0	16899	5016	4012	1000	4000	1000	5000	47613	0	22947	29047	29343	3	10	5000	1000	4000	1000	4000	29127	29108	1	1	61001	1000	1000	0	1000	0	3	1001	0	0	0	0	1002	2	0	2	0	0	12942	9124	6831	3107	9	44	20122	3073	3816	18	42	45	28377	16417	14058	14883	1000	4000	29235	29217	29287	29218	29308
65004	29205	219	0	13	0	0	17	0	0	0	0	0	4	0	0	0	4630	28854	0	0	0	16911	5004	4016	1000	4000	1000	5000	47629	5	22907	29105	29315	3	10	5000	1000	4000	1000	4000	29187	29100	1	1	61001	1000	1000	0	1000	0	3	1000	0	0	0	1	1000	2	1	0	0	0	12807	9228	6911	3061	7	60	20230	3104	3817	18	39	42	28455	16481	13917	15124	1000	4000	29269	29205	29254	29270	29239
65004	29310	219	0	16	0	0	15	0	0	0	0	0	303	0	1	0	4560	28713	0	0	0	16984	5012	4004	1000	4000	1000	5000	47651	5	22897	29075	29272	3	10	5000	1000	4000	1000	4000	29186	29175	1	1	61001	1000	1000	0	1000	0	3	1000	0	0	0	0	1000	2	0	2	0	0	13056	9389	6849	3079	9	53	20225	3080	3818	16	47	50	28333	16311	13821	14841	1000	4000	29266	29241	29275	29278	29243
65004	29388	219	0	11	0	0	15	0	0	0	0	0	0	0	1	0	4535	28887	0	0	0	16973	5012	4016	1000	4000	1000	5000	47607	2	22924	29079	29310	3	10	5000	1000	4000	1000	4000	29101	29109	1	1	61001	1000	1000	0	1000	0	0	1002	0	1	0	3	1000	0	0	2	0	0	12994	9091	6896	3024	6	45	20196	3076	3817	9	43	41	28364	16319	13905	14856	1000	4000	29215	29234	29239	29342	29269
65004	29257	219	0	14	0	0	15	0	0	0	0	0	4	0	1	0	4566	28826	0	1	1	16946	5016	4016	1000	4000	1000	5000	47633	2	22883	29112	29307	3	10	5000	1000	4000	1000	4000	29156	29116	1	1	61001	1000	1000	0	1000	0	2	1002	0	1	0	0	1002	2	0	3	0	0	12869	9523	6830	3104	7	47	20080	3068	3818	12	45	42	28441	16463	14030	15020	1000	4000	29205	29343	29221	29267	29269
65004	29234	219	0	14	0	0	15	0	0	0	0	0	4	0	0	0	4638	28768	0	0	0	17007	5016	4016	1000	4000	1001	5002	47625	2	22917	29013	29254	3	10	5000	1000	4000	1000	4000	29145	29095	1	1	61001	1000	1000	0	1000	0	3	1000	0	0	0	2	1000	2	1	3	0	0	12903	9105	6841	3147	10	48	20077	3095	3823	13	47	43	28454	16307	13987	14924	1000	4000	29209	29280	29255	29301	29282
65004	29283	220	1	16	0	1	15	1	1	1	0	0	4	0	0	0	4594	28792	0	1	1	16931	5016	4016	1000	4000	1000	5000	47596	0	22925	29109	29266	3	10	5000	1000	4000	1000	4000	29121	29188	1	1	61001	1000	1000	1	1000	4	3	1000	0	0	0	0	1002	2	1	3	0	0	12864	9076	6840	3118	9	46	20142	3065	3816	10	39	38	28522	16359	13908	15038	1000	4000	29296	29289	29402	29219	29278

Count: 8

Code:

  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	19	1e	1f	22	23	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	80067	600	1	1	0	0	0	1	0	80045	1	6	6	25	400100	100	320000	80000	100	320000	80000	500	400029	3840000	0	80041	0	80041	80060	0	3	42	400100	200	80000	320000	200	80000	320000	80057	80057	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	0	80014	1	0	80000	6	0	14	18	0	5109	2	17	2	2	80038	0	13	10	80000	320000	100	80042	80061	80061	80061	80061
400204	80041	599	0	0	0	23	0	0	0	80045	1	6	0	25	400164	100	320064	80000	100	320000	80000	500	400000	3840000	1	80038	0	80060	80060	0	3	23	400100	200	80000	320000	200	80000	320000	80057	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80014	0	0	80014	0	0	14	0	0	5109	2	17	2	2	80057	0	13	0	80000	320000	100	80058	80042	80061	80061	80058
400204	80041	600	0	0	0	0	0	0	0	80045	1	0	6	25	400100	100	320076	80000	100	320000	80000	500	400022	7023940	1	80022	0	80044	80041	0	3	42	400100	200	80000	320000	200	80000	320000	80060	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80013	0	20	80000	6	0	14	22	0	5109	2	17	2	2	80057	1	0	10	80000	320000	100	80061	80061	80058	80061	80061
400204	80060	599	0	0	0	0	0	0	0	80045	1	0	6	25	400100	100	320076	80000	100	320000	80000	500	400029	9600020	1	80022	0	80060	80041	0	3	42	400100	200	80000	320000	200	80000	320000	80057	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80018	0	17	80018	0	1	18	0	0	5109	2	17	2	2	80054	1	0	13	80000	320000	100	80042	80045	80058	80061	80042
400204	80165	600	0	0	0	24	0	0	0	80045	1	6	0	25	400176	100	320076	80000	100	320000	80000	500	400032	4150376	1	80038	0	80060	80041	0	3	42	400100	200	80000	320000	200	80000	320000	80057	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80014	0	13	80018	0	1	0	22	0	5109	2	17	2	2	80038	0	13	0	80000	320000	100	80061	80061	80061	80061	80058
400204	80041	600	1	0	0	0	0	0	0	80045	1	6	6	25	400100	100	320000	80000	100	320000	80000	500	400024	8640020	1	80041	0	80057	80057	0	3	23	400100	200	80000	320000	200	80000	320000	80060	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80000	0	0	80000	6	1	0	22	0	5109	2	17	2	2	80038	0	13	13	80000	320000	100	80061	80058	80061	80058	80061
400204	80060	600	0	0	0	0	0	1	0	80045	1	6	6	25	400176	100	320000	80000	100	320000	80000	500	400015	8640020	1	80038	0	80060	80041	0	3	39	400100	200	80000	320000	200	80000	320000	80060	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80000	0	0	80014	0	1	0	22	1	5109	2	17	2	2	80038	1	13	10	80000	320000	100	80061	80061	80042	80061	80061
400204	80060	600	0	0	0	32	0	0	0	80045	1	6	6	25	400176	100	320000	80000	100	320000	80000	500	400000	9600020	1	80041	0	80041	80060	0	3	42	400100	200	80000	320000	200	80000	320000	80044	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80018	0	17	80018	0	1	14	0	0	5109	2	17	2	2	80057	1	10	13	80000	320000	100	80061	80042	80061	80061	80061
400204	80060	600	0	0	0	24	0	1	0	80045	1	0	6	25	400100	100	320076	80000	100	320000	80000	500	400000	8640020	1	80022	0	80041	80041	0	3	42	400100	200	80000	320000	200	80000	320000	80057	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80018	1	18	80018	0	0	18	22	0	5109	2	17	2	2	80057	1	13	0	80000	320000	100	80061	80042	80042	80058	80042
400204	80060	600	0	1	0	24	0	0	0	80045	1	6	0	25	400176	100	320064	80000	100	320000	80000	500	400029	8640020	1	80041	0	80060	80060	0	3	23	400100	200	80000	320000	200	80000	320000	80060	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80015	0	21	80018	6	0	18	22	0	5109	2	17	2	2	80038	0	0	0	80000	320000	100	80042	80042	80061	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	0e	0f	18	19	1e	1f	22	23	24	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80057	600	1	1	0	0	0	20	0	1	0	0	80047	1	6	6	0	25	400086	10	320076	80000	10	320000	80000	50	400022	8640024	0	80022	0	80041	80060	0	3	42	400010	20	80000	320000	20	80000	320000	80057	80057	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	0	80014	0	0	0	13	80000	6	1	13	0	0	5019	24	0	23	17	24	23	80054	1	0	10	80000	320000	10	80058	80042	80042	80042	80058
400024	80057	599	0	0	0	0	0	24	0	0	0	0	80045	1	0	6	0	25	400086	10	320064	80000	10	320000	80000	50	400011	3840000	1	80041	0	80044	80041	0	3	39	400010	20	80000	320000	20	80000	320000	80047	80046	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80014	0	0	0	18	80014	6	1	13	0	0	5019	15	0	26	17	20	26	80041	1	13	13	80000	320000	10	80061	80061	80061	80061	80061
400024	80057	599	0	0	0	0	0	24	0	1	0	0	80026	0	0	0	0	25	400086	10	320076	80000	10	320000	80000	50	400018	9600020	1	80041	0	80060	80041	0	3	42	400010	20	80000	320000	20	80000	320000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80000	0	0	0	17	80000	6	1	0	0	0	5056	15	0	25	17	24	24	80054	0	13	0	80000	320000	10	80042	80058	80058	80058	80042
400024	80060	600	0	0	0	0	0	19	0	1	0	0	80043	1	6	6	0	25	400086	10	320076	80000	10	320000	80000	50	400000	8640020	1	80041	0	80041	80060	0	3	42	400010	20	80000	320000	20	80000	320000	80057	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80018	0	0	0	18	80018	6	0	0	22	0	5019	21	0	11	17	22	12	80038	1	0	0	80000	320000	10	80042	80042	80061	80042	80061
400024	80060	600	0	0	0	0	0	23	0	0	0	0	80045	0	0	6	0	25	400086	10	320076	80000	10	320000	80000	50	400070	8640020	0	80038	0	80041	80057	0	3	42	400010	20	80000	320000	20	80000	320000	80060	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80013	0	0	0	0	80018	0	1	13	22	0	5019	21	0	20	17	24	11	80057	0	0	13	80000	320000	10	80061	80061	80474	80277	80061
400024	80041	599	0	0	0	0	0	23	0	1	0	0	80045	1	0	6	0	25	400010	10	320076	80000	10	320000	80000	50	400022	9600020	0	80041	0	80041	80041	0	3	23	400010	20	80000	320000	20	80000	320000	80060	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80013	0	0	0	102	80014	6	1	0	18	0	5019	18	0	12	17	26	19	80039	1	13	13	80000	320000	10	80042	80061	80061	80042	80061
400024	80057	600	0	0	0	0	0	23	0	0	0	0	80045	0	0	6	0	25	400074	10	320000	80000	10	320000	80000	50	400029	9600020	1	80041	0	80060	80060	0	3	39	400010	20	80000	320000	20	80000	320000	80060	80057	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	0	80000	0	0	0	14	80014	0	1	13	0	0	5019	21	0	25	17	25	25	80054	1	10	10	80000	320000	10	80058	80058	80058	80058	80042
400024	80041	600	0	0	0	0	0	20	0	0	0	0	80045	0	6	6	0	25	400010	10	320076	80000	10	320000	80000	50	400011	3840000	1	80038	0	80060	80057	0	3	42	400010	20	80000	320000	20	80000	320000	80041	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80018	0	0	0	18	80017	6	0	13	0	0	5019	18	0	26	17	21	25	80054	1	10	13	80000	320000	10	80061	80042	80061	80042	80061
400024	80057	599	0	0	0	0	0	0	0	1	0	0	80042	0	0	0	0	25	400010	10	320000	80000	10	320000	80000	50	400029	3840000	1	80022	0	80060	80060	0	3	23	400010	20	80000	320000	20	80000	320000	80060	80041	1	1	80022	10	9	10	10	80000	80000	0	10	80000	0	18	80017	0	0	0	18	80017	6	1	13	22	0	5019	18	0	25	17	14	26	80038	1	13	13	80000	320000	10	80061	80042	80061	80061	80061
400024	80041	600	0	1	0	0	0	24	0	0	0	0	80045	1	0	0	0	25	400086	10	320076	80000	10	320000	80000	50	400024	3840000	1	80038	0	80041	80060	0	3	39	400010	20	80000	320000	20	80000	320000	80057	80057	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	18	80018	0	0	0	17	80000	6	1	14	18	0	5019	18	0	25	17	23	25	80038	0	13	13	80000	320000	10	80061	80113	80061	80042	80058

LD4R (2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations