Firestorm: LD4R (4H) measurements

Code:

  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.008

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	0e	0f	18	19	1e	22	24	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
65005	29473	219	5	1	1	1	3	1	0	0	0	2	1	0	4632	28805	0	0	16922	5000	4004	1000	4000	1000	5000	47546	4	22917	29060	29251	3	10	5000	1000	4000	1000	4000	29292	29205	1	1	61001	1000	1000	1	1000	3	1000	0	0	1001	2	1	2	12975	9309	6834	3056	1	49	20173	3081	3817	12	51	49	28456	16254	14141	15236	1000	4000	29246	29314	29293	29357	29260
65004	29263	219	0	1	0	1	1	1	0	0	0	0	1	0	4671	28782	0	0	16928	5008	4000	1000	4000	1000	5000	47488	2	22895	29153	29289	3	10	5000	1000	4000	1000	4000	29239	29143	1	1	61001	1000	1000	0	1000	2	1000	1	0	1001	2	0	2	12821	9266	6878	3098	0	44	20113	3054	3816	13	40	50	28417	16567	13609	14865	1000	4000	29309	29327	29237	29299	29388
65004	29435	219	0	0	0	0	1	0	0	0	0	27	0	0	4749	28746	1	0	16948	5000	4008	1000	4000	1000	5000	47462	4	22940	29126	29314	3	10	5000	1000	4000	1000	4000	29148	29183	1	1	61001	1000	1000	0	1000	2	1000	0	0	1000	2	1	2	13190	9243	6908	3022	1	39	20130	3066	3811	15	45	46	28320	16409	13946	14880	1000	4000	29360	29240	29326	29176	29258
65004	29228	219	1	1	0	0	1	0	0	0	0	3	0	0	4531	28775	0	0	16937	5008	4000	1000	4000	1000	5000	47579	0	22888	29077	29278	3	10	5000	1000	4000	1000	4000	29148	29186	1	1	61001	1000	1000	0	1000	2	1000	0	0	1000	3	1	2	13026	9374	6905	3162	0	44	20132	3109	3813	11	43	38	28283	16434	13959	14822	1000	4000	29281	29242	29390	29335	29302
65004	29318	219	0	0	0	0	0	0	0	0	0	2	0	0	4609	28825	0	0	16949	5000	4008	1000	4000	1000	5000	47554	2	22897	29131	29324	3	10	5000	1000	4000	1000	4000	29265	29213	1	1	61001	1000	1000	1	1000	3	1000	0	0	1000	2	0	2	12849	9096	6847	3058	1	41	20210	3093	3815	13	37	37	28264	16211	14096	14927	1000	4000	29281	29196	29247	29260	29381
65004	29294	220	0	0	0	0	1	0	0	0	0	3	1	0	4715	28795	1	0	16955	5008	4008	1000	4000	1000	5000	47621	2	22932	29060	29303	3	10	5000	1000	4000	1000	4000	29205	29218	1	1	61001	1000	1000	0	1000	3	1001	0	0	1000	0	0	3	12807	9083	6901	3068	0	37	20157	3069	3815	8	48	39	28332	16331	13984	15192	1000	4000	29262	29265	29272	29227	29244
65004	29359	220	0	0	0	0	0	1	1	0	0	3	1	0	4507	28765	0	0	16977	5012	4000	1000	4000	1000	5000	47613	0	22931	29075	29261	3	10	5000	1000	4000	1000	4000	29048	29178	1	1	61001	1000	1000	0	1000	3	1000	1	0	1000	2	0	3	12802	9423	6875	3049	0	37	20156	3092	3813	19	38	46	28378	16630	13943	14885	1000	4000	29338	29298	29298	29305	29249
65004	29267	219	0	0	0	0	0	0	0	0	0	0	1	0	4599	28732	0	0	17071	5008	4012	1000	4000	1000	5000	47619	3	22894	29096	29355	3	10	5000	1000	4000	1000	4000	29175	29157	1	1	61001	1000	1000	0	1000	2	1000	0	0	1000	2	0	2	12952	9131	6866	3061	0	37	20134	3036	3811	14	42	41	28392	16547	13911	15038	1000	4000	29411	29356	29358	29280	29256
65004	29379	219	0	0	0	0	0	0	0	0	0	3	1	0	4615	28817	0	0	16936	5008	4012	1000	4000	1000	5000	47639	4	22886	29078	29317	3	10	5000	1000	4000	1000	4000	29164	29159	1	1	61001	1000	1000	1	1000	2	1000	0	0	1000	0	0	0	12877	9209	6810	3095	0	40	20135	3043	3819	11	44	45	28314	16427	13939	14976	1000	4000	29294	29288	29350	29261	29246
65004	29270	220	0	0	0	0	1	0	0	0	0	2	1	0	4506	28825	0	0	17037	5000	4012	1000	4000	1000	5000	47627	2	22900	29082	29342	3	10	5000	1000	4000	1000	4000	29136	29162	1	1	61001	1000	1000	0	1000	0	1002	0	0	1000	2	0	3	12799	9285	6860	3046	0	43	20067	3061	3813	13	45	42	28388	16458	14107	14565	1000	4000	29248	29279	29378	29350	29324

Count: 8

Code:

  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	23	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	80614	599	1	1	1	1	0	1239	0	1	0	80045	0	0	6	25	400176	100	320064	80000	100	320000	80000	500	400855	10880304	1	80038	0	80041	80060	0	0	3	42	400100	200	80000	320000	200	80000	320000	80060	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	80000	0	17	80023	6	1	13	22	0	0	0	5109	1	17	1	1	80038	0	10	10	80000	320000	100	80061	80061	80061	80042	80061
400204	80060	599	1	0	0	0	0	24	0	0	0	80042	1	0	6	25	400100	100	320076	80000	100	320000	80000	500	400054	10880304	0	80022	0	80060	80041	0	0	3	23	400100	200	80000	320000	200	80000	320000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80018	1	18	80023	0	1	13	22	0	0	0	5109	1	17	1	1	80057	0	0	10	80000	320000	100	80061	80061	80061	80061	80042
400204	80060	600	1	0	0	0	0	56	0	1	0	80045	1	6	6	25	400100	100	320000	80000	100	320000	80000	500	400048	5440156	1	80041	0	80060	80060	0	0	3	42	400100	200	80000	320000	200	80000	320000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80000	0	13	80024	0	1	0	0	0	0	0	5109	1	17	1	1	80057	1	13	13	80000	320000	100	80042	80058	80061	80061	80061
400204	80060	599	1	0	1	0	0	0	0	0	0	80026	1	6	0	25	400176	100	320076	80000	100	320000	80000	500	400048	5440028	1	80022	0	80060	80060	0	0	3	23	400100	200	80000	320000	200	80050	320000	80057	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80000	0	0	80024	0	1	0	0	0	0	0	5109	1	17	1	1	80057	1	10	13	80000	320000	100	80042	80042	80058	80042	80061
400204	80057	599	1	0	1	0	0	23	0	0	0	80045	1	0	6	25	400176	100	320076	80000	100	320000	80000	500	400047	10880304	0	80022	0	80057	80057	0	0	3	39	400100	200	80000	320000	200	80000	320000	80041	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80000	0	18	80024	6	0	13	18	0	0	0	5109	1	17	1	1	80038	0	13	0	80000	320000	100	80061	80061	80061	80042	80061
400204	80041	600	1	0	0	1	0	0	0	1	0	80045	0	6	6	25	400176	100	320000	80000	100	320000	80000	500	400046	10880304	0	80041	0	80060	80060	0	0	3	39	400100	200	80000	320000	200	80000	320000	80060	80041	1	1	80202	100	99	100	100	80000	80000	1	100	80000	0	80018	0	0	80023	0	1	0	18	0	0	0	5109	1	17	1	1	80057	0	13	0	80000	320000	100	80042	80061	80061	80061	80042
400204	80041	599	1	0	0	0	0	24	0	0	0	80045	0	6	6	25	400176	100	320076	80000	100	320000	80000	500	400047	6286260	0	80038	0	80107	80057	0	0	3	42	400100	200	80000	320000	200	80000	320000	80060	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80000	0	18	80023	0	1	0	0	0	0	0	5109	1	17	1	1	80038	1	0	13	80000	320000	100	80061	80042	80061	80061	80042
400204	80060	600	1	0	0	0	0	19	0	0	0	80045	1	6	6	25	400176	100	320000	80000	100	320000	80000	500	400046	10880304	1	80038	0	80041	80060	0	0	3	23	400100	200	80000	320000	200	80000	320000	80057	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	22	80018	0	18	80023	0	1	18	22	0	0	0	5109	1	17	1	1	80038	0	0	10	80000	320000	100	80061	80061	80061	80063	80061
400204	80060	600	1	0	0	0	0	173	168	1	0	80026	1	0	6	25	400176	100	320076	80000	100	320000	80000	500	401056	10880304	0	80022	0	80041	80041	0	0	3	42	400100	200	80000	320000	200	80000	320000	80041	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	22	80014	0	186	80023	6	0	0	18	0	0	0	5109	1	17	1	1	80038	0	13	10	80000	320000	100	80061	80061	80058	80061	80061
400204	80060	599	1	0	0	0	0	24	0	1	0	80045	1	6	6	25	400176	100	320076	80000	100	320000	80000	500	400046	5622636	1	80041	0	80060	80060	0	0	3	42	400100	200	80000	320000	200	80000	320000	80060	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80017	0	18	80023	6	0	0	22	0	0	0	5109	1	17	1	1	80057	0	0	13	80000	320000	100	80061	80061	80061	80042	80058

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	0e	0f	18	1e	22	24	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	cd	cf	d0	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80057	599	0	0	0	0	19	1	0	80045	1	6	6	0	25	400074	10	320064	80000	10	320000	80000	50	400793	8640020	1	80022	80060	80060	3	42	400010	20	80000	320000	20	80000	320800	80044	80447	1	1	80021	10	9	10	10	80000	80000	0	10	80008	8	27	80031	1	0	31	80000	6	0	14	0	0	0	5019	0	21	17	0	0	15	15	80057	0	13	10	80000	320000	10	80042	80042	80061	80058	80061
400024	80060	599	0	0	0	0	23	1	0	80045	1	6	6	0	25	400086	10	320076	80000	10	320000	80000	50	400685	8640020	1	80041	80060	80060	3	42	400010	20	80000	320000	20	80000	320000	80060	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80000	0	0	0	80013	0	0	0	0	0	0	5019	0	16	17	0	0	16	13	80057	1	0	13	80000	320000	10	80042	80061	80061	80061	80061
400024	80060	600	0	0	1	0	23	0	0	80042	1	6	0	0	25	400086	10	320076	80000	10	320000	80000	50	400898	8640020	0	80022	80041	80060	3	42	400010	20	80000	320000	20	80000	320000	80060	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80000	0	0	20	80014	0	1	17	22	0	0	5019	0	16	17	0	0	13	15	80057	0	13	13	80000	320000	10	80042	80061	80042	80042	80061
400024	80043	600	0	0	0	0	0	0	0	80045	1	6	6	0	25	400010	10	320076	80000	10	320000	80000	50	400318	8640020	0	80022	80060	80060	3	42	400010	20	80000	320000	20	80000	320000	80060	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80000	0	0	0	80000	6	0	0	22	0	0	5019	0	15	17	0	0	15	13	80057	0	0	0	80000	320000	10	80058	80043	80058	80058	80058
400024	80060	599	1	1	1	0	23	1	0	80029	1	6	6	0	25	400086	10	320076	80000	10	320000	80000	50	400034	4473180	0	80043	80060	80041	3	42	400010	20	80000	320000	20	80000	320000	80060	80057	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	0	80018	0	0	18	80000	6	1	13	22	0	0	5019	0	16	17	0	0	16	13	80057	1	31	10	80000	320000	10	80042	80061	80042	80061	80061
400024	80041	600	0	1	1	0	0	0	0	80026	1	6	6	0	25	400086	10	320076	80000	10	320000	80000	50	400066	8640020	0	80041	80060	80060	3	42	400010	20	80000	320000	20	80000	320000	80060	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80018	0	0	14	80014	6	0	13	22	0	0	5019	0	15	17	0	0	14	14	80038	1	0	10	80000	320000	10	80061	80061	80061	80061	80061
400024	80060	599	0	0	0	0	0	0	0	80042	1	6	6	0	25	400086	10	320076	80000	10	320000	80000	50	400029	9600020	0	80038	80041	80041	3	42	400010	20	80000	320000	20	80000	320000	80060	80041	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	0	80000	0	0	0	80017	6	0	0	22	0	0	5019	0	16	17	0	0	16	14	80038	1	13	0	80000	320000	10	80058	80061	80061	80061	80061
400024	80060	599	0	0	0	0	0	0	0	80045	1	0	6	0	25	400086	10	320000	80000	10	320000	80000	50	400526	8640020	0	80041	80041	80060	3	42	400010	20	80000	320000	20	80000	320000	80041	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80000	0	0	0	80000	6	1	0	22	0	0	5019	0	13	17	0	0	15	13	80041	1	0	13	80000	320000	10	80042	80042	80061	80061	80042
400024	80041	599	0	0	0	0	19	1	0	80045	1	6	6	0	25	400010	10	320076	80000	10	320000	80000	50	400062	9600020	0	80022	80041	80060	3	42	400010	20	80000	320000	20	80000	320000	80060	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80018	2	4	14	80013	6	1	0	22	0	0	5019	0	15	17	0	0	16	16	80038	1	13	13	80000	320000	10	80058	80058	80045	80061	80042
400024	80060	600	0	0	0	0	0	0	0	80026	1	6	6	0	25	400086	10	320052	80000	10	320000	80000	50	400347	9600020	0	80043	80041	80060	3	42	400010	20	80000	320000	20	80000	320000	80060	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80000	0	0	18	80000	6	1	14	22	0	0	5019	0	16	17	0	0	16	16	80057	0	0	10	80000	320000	10	80042	80042	80042	80061	80042

LD4R (4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations