Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 1 mov x1, 2 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 5.000
Issues: 5.008
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 4.008
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 0e | 0f | 1e | 1f | 22 | 24 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule simd uop (54) | schedule ldst uop (55) | dispatch simd uop (57) | dispatch ldst uop (58) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd load (98) | inst ldst (9b) | 9d | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
65005 | 29284 | 220 | 1 | 15 | 1 | 1 | 14 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 4607 | 28821 | 0 | 0 | 16944 | 5008 | 4012 | 1000 | 4000 | 1000 | 5000 | 47510 | 4 | 22950 | 29091 | 29300 | 3 | 10 | 5000 | 1000 | 4000 | 1000 | 4000 | 29138 | 29172 | 1 | 1 | 61001 | 1000 | 1000 | 1 | 1000 | 0 | 2 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 2 | 0 | 0 | 12974 | 9432 | 6851 | 3046 | 7 | 43 | 20139 | 3202 | 3812 | 11 | 37 | 37 | 28429 | 16002 | 13843 | 14647 | 1000 | 4000 | 29226 | 29316 | 29251 | 29251 | 29303 |
65004 | 29228 | 219 | 0 | 16 | 0 | 0 | 13 | 0 | 0 | 0 | 2 | 0 | 1 | 0 | 4559 | 28746 | 1 | 0 | 16977 | 5008 | 4008 | 1000 | 4000 | 1000 | 5000 | 47528 | 2 | 22931 | 29074 | 29256 | 3 | 10 | 5000 | 1000 | 4000 | 1000 | 4000 | 29206 | 29127 | 1 | 1 | 61001 | 1000 | 1000 | 1 | 1000 | 0 | 3 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 2 | 0 | 0 | 12979 | 9335 | 6977 | 3078 | 3 | 32 | 20157 | 3018 | 3814 | 9 | 33 | 36 | 28399 | 16409 | 13949 | 14589 | 1000 | 4000 | 29236 | 29249 | 29242 | 29302 | 29240 |
65004 | 29298 | 219 | 0 | 14 | 0 | 0 | 18 | 0 | 0 | 0 | 3 | 0 | 1 | 0 | 4549 | 28779 | 1 | 1 | 16970 | 5012 | 4008 | 1000 | 4000 | 1000 | 5000 | 47561 | 2 | 22946 | 29103 | 29279 | 3 | 10 | 5000 | 1000 | 4000 | 1000 | 4000 | 29038 | 29130 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 2 | 1000 | 0 | 0 | 0 | 1000 | 2 | 1 | 2 | 0 | 0 | 12995 | 9388 | 6825 | 3090 | 8 | 34 | 20193 | 3125 | 3813 | 7 | 31 | 34 | 28320 | 16372 | 13818 | 14973 | 1000 | 4000 | 29299 | 29389 | 29155 | 29190 | 29238 |
65004 | 29237 | 219 | 0 | 15 | 0 | 0 | 12 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 4557 | 28806 | 0 | 0 | 16936 | 5016 | 4016 | 1000 | 4000 | 1000 | 5000 | 47581 | 5 | 22950 | 29090 | 29285 | 3 | 10 | 5000 | 1000 | 4000 | 1000 | 4000 | 29153 | 29102 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1002 | 1 | 3 | 1002 | 0 | 0 | 1 | 1000 | 2 | 0 | 2 | 0 | 0 | 12751 | 9409 | 6845 | 3175 | 7 | 39 | 20202 | 3061 | 3813 | 9 | 37 | 36 | 28380 | 16500 | 13755 | 14802 | 1000 | 4000 | 29277 | 29268 | 29248 | 29292 | 29284 |
65004 | 29296 | 219 | 0 | 13 | 0 | 0 | 10 | 0 | 0 | 0 | 2 | 0 | 1 | 0 | 4602 | 28819 | 0 | 1 | 16980 | 5008 | 4012 | 1000 | 4000 | 1000 | 5000 | 47625 | 0 | 22917 | 29093 | 29262 | 3 | 10 | 5000 | 1000 | 4000 | 1000 | 4000 | 29114 | 29136 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 2 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 3 | 0 | 0 | 13023 | 9254 | 6848 | 3029 | 8 | 35 | 20177 | 3060 | 3812 | 4 | 40 | 32 | 28389 | 16284 | 13855 | 14774 | 1000 | 4000 | 29310 | 29261 | 29233 | 29278 | 29335 |
65004 | 29219 | 220 | 0 | 16 | 0 | 0 | 14 | 0 | 0 | 0 | 2 | 0 | 1 | 0 | 4559 | 28804 | 0 | 0 | 17012 | 5012 | 4008 | 1000 | 4000 | 1000 | 5000 | 47591 | 4 | 22939 | 29138 | 29241 | 3 | 10 | 5000 | 1000 | 4000 | 1000 | 4000 | 29162 | 29182 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 2 | 1001 | 0 | 0 | 0 | 1001 | 2 | 1 | 2 | 0 | 0 | 12967 | 9442 | 6870 | 3097 | 4 | 44 | 20190 | 3086 | 3739 | 8 | 41 | 39 | 28414 | 16414 | 13967 | 14905 | 1000 | 4000 | 29269 | 29326 | 29268 | 29270 | 29316 |
65004 | 29278 | 219 | 0 | 13 | 0 | 0 | 20 | 0 | 0 | 0 | 165 | 0 | 1 | 0 | 4568 | 28830 | 1 | 1 | 16967 | 5008 | 4008 | 1000 | 4000 | 1000 | 5000 | 47508 | 1 | 22918 | 29130 | 29333 | 3 | 10 | 5000 | 1000 | 4000 | 1000 | 4000 | 29134 | 29057 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 2 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 2 | 0 | 0 | 12871 | 9238 | 6849 | 3084 | 5 | 42 | 20155 | 3114 | 3812 | 7 | 38 | 37 | 28495 | 15827 | 14004 | 14678 | 1000 | 4000 | 29265 | 29300 | 29252 | 29324 | 29188 |
65004 | 29316 | 219 | 0 | 13 | 0 | 0 | 12 | 0 | 1 | 0 | 2 | 0 | 0 | 0 | 4585 | 28833 | 0 | 1 | 16961 | 5012 | 4016 | 1000 | 4000 | 1000 | 5000 | 47633 | 7 | 22953 | 29135 | 29306 | 3 | 10 | 5000 | 1000 | 4000 | 1000 | 4000 | 29170 | 29132 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 3 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 2 | 0 | 0 | 12913 | 9189 | 6864 | 3152 | 9 | 39 | 20195 | 3093 | 3811 | 8 | 39 | 37 | 28407 | 15611 | 13897 | 14827 | 1000 | 4000 | 29314 | 29314 | 29247 | 29200 | 29334 |
65004 | 29204 | 219 | 0 | 14 | 0 | 0 | 17 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 4525 | 28753 | 1 | 0 | 17032 | 5008 | 4016 | 1000 | 4000 | 1000 | 5000 | 47563 | 2 | 22915 | 29123 | 29283 | 3 | 10 | 5000 | 1000 | 4000 | 1000 | 4000 | 29209 | 29192 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 2 | 1000 | 0 | 0 | 1 | 1001 | 2 | 0 | 3 | 0 | 0 | 12843 | 9225 | 6874 | 3010 | 8 | 35 | 20300 | 3080 | 3813 | 10 | 41 | 41 | 28321 | 16327 | 14020 | 15167 | 1000 | 4000 | 29205 | 29231 | 29166 | 29295 | 29181 |
65004 | 29187 | 219 | 0 | 16 | 0 | 0 | 18 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 4566 | 28836 | 0 | 0 | 16947 | 5008 | 4012 | 1000 | 4000 | 1000 | 5000 | 47539 | 2 | 22942 | 29101 | 29312 | 3 | 10 | 5000 | 1000 | 4000 | 1000 | 4000 | 29216 | 29197 | 1 | 1 | 61001 | 1000 | 1000 | 1 | 1002 | 2 | 2 | 1001 | 0 | 0 | 1 | 1000 | 2 | 1 | 3 | 1 | 0 | 12914 | 9273 | 6827 | 3095 | 7 | 40 | 20105 | 3100 | 3812 | 7 | 42 | 41 | 28368 | 16320 | 13805 | 15126 | 1000 | 4000 | 29310 | 29328 | 29229 | 29219 | 29219 |
Count: 8
Code:
ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6] ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6] ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6] ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6] ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6] ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6] ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6] ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0007
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 0e | 0f | 19 | 1e | 1f | 22 | 24 | 3f | 43 | 46 | 49 | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | e7 | ea | eb | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
400205 | 80070 | 599 | 0 | 1 | 1 | 0 | 20 | 0 | 1 | 0 | 80042 | 1 | 6 | 0 | 0 | 25 | 400118 | 100 | 320064 | 80006 | 100 | 320032 | 80008 | 500 | 400056 | 8640272 | 0 | 80038 | 0 | 80057 | 80057 | 6 | 28 | 400140 | 200 | 80008 | 320032 | 200 | 80008 | 320032 | 80041 | 80041 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80002 | 18 | 80015 | 0 | 14 | 80002 | 6 | 1 | 14 | 18 | 1 | 1 | 1 | 5116 | 0 | 16 | 0 | 0 | 80038 | 0 | 10 | 10 | 80000 | 320000 | 100 | 80042 | 80058 | 80058 | 80042 | 80058 |
400204 | 80057 | 600 | 0 | 0 | 0 | 0 | 20 | 0 | 1 | 0 | 80042 | 0 | 0 | 6 | 0 | 25 | 400170 | 100 | 320012 | 80006 | 100 | 320032 | 80008 | 500 | 400246 | 8640272 | 1 | 80038 | 0 | 80041 | 80057 | 6 | 28 | 400140 | 200 | 80008 | 320032 | 200 | 80008 | 320032 | 80057 | 80057 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80002 | 18 | 80002 | 0 | 0 | 80015 | 6 | 1 | 14 | 0 | 1 | 1 | 1 | 5117 | 0 | 16 | 0 | 0 | 80038 | 0 | 10 | 10 | 80000 | 320000 | 100 | 80058 | 80058 | 80058 | 80058 | 80058 |
400204 | 80057 | 599 | 0 | 0 | 0 | 0 | 20 | 0 | 1 | 0 | 80026 | 1 | 0 | 6 | 0 | 25 | 400170 | 100 | 320064 | 80006 | 100 | 320032 | 80008 | 500 | 400049 | 8640272 | 1 | 80038 | 0 | 80057 | 80057 | 6 | 28 | 400140 | 200 | 80008 | 320032 | 200 | 80008 | 320032 | 80057 | 80057 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80002 | 18 | 80016 | 0 | 0 | 80016 | 0 | 0 | 14 | 0 | 1 | 1 | 1 | 5117 | 0 | 16 | 0 | 0 | 80038 | 1 | 10 | 10 | 80000 | 320000 | 100 | 80058 | 80058 | 80042 | 80058 | 80042 |
400204 | 80041 | 599 | 0 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | 80042 | 1 | 6 | 6 | 0 | 25 | 400100 | 100 | 320000 | 80000 | 100 | 320000 | 80000 | 500 | 400000 | 3840000 | 1 | 80038 | 0 | 80057 | 80041 | 3 | 39 | 400100 | 200 | 80000 | 320000 | 200 | 80000 | 320000 | 80041 | 80057 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 1 | 100 | 80000 | 18 | 80013 | 0 | 14 | 80013 | 6 | 0 | 0 | 18 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80038 | 0 | 10 | 0 | 80000 | 320000 | 100 | 80042 | 80058 | 80042 | 80042 | 80058 |
400204 | 80057 | 599 | 0 | 1 | 1 | 0 | 19 | 0 | 0 | 0 | 80026 | 0 | 6 | 6 | 0 | 25 | 400100 | 100 | 320000 | 80000 | 100 | 320000 | 80000 | 500 | 400000 | 8640020 | 1 | 80022 | 0 | 80041 | 80057 | 3 | 48 | 400100 | 200 | 80000 | 320000 | 200 | 80000 | 320000 | 80041 | 80041 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 80000 | 0 | 14 | 80013 | 6 | 1 | 14 | 18 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80054 | 0 | 10 | 0 | 80000 | 320000 | 100 | 80042 | 80058 | 80058 | 80058 | 80042 |
400204 | 80057 | 599 | 0 | 0 | 0 | 0 | 19 | 0 | 1 | 0 | 80042 | 0 | 6 | 0 | 0 | 25 | 400164 | 100 | 320064 | 80000 | 100 | 320000 | 80000 | 500 | 400011 | 3840000 | 1 | 80022 | 0 | 80041 | 80057 | 3 | 48 | 400100 | 200 | 80000 | 320000 | 200 | 80000 | 320000 | 80041 | 80057 | 2 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 18 | 80014 | 1 | 17 | 80000 | 6 | 1 | 14 | 18 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80038 | 0 | 10 | 10 | 80000 | 320000 | 100 | 80058 | 80058 | 80058 | 80042 | 80058 |
400204 | 80041 | 599 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 80026 | 1 | 6 | 6 | 0 | 25 | 400100 | 100 | 320000 | 80000 | 100 | 320000 | 80000 | 500 | 400011 | 3840000 | 1 | 80038 | 0 | 80057 | 80057 | 3 | 48 | 400100 | 200 | 80000 | 320000 | 200 | 80000 | 320000 | 80057 | 80057 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 80000 | 0 | 17 | 80013 | 0 | 1 | 0 | 18 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80054 | 1 | 10 | 10 | 80000 | 320000 | 100 | 80042 | 80042 | 80058 | 80047 | 80058 |
400204 | 80057 | 600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 80026 | 1 | 6 | 0 | 0 | 25 | 400164 | 100 | 320000 | 80000 | 100 | 320000 | 80000 | 500 | 400011 | 8640020 | 1 | 80038 | 0 | 80057 | 80041 | 3 | 48 | 400100 | 200 | 80000 | 320000 | 200 | 80000 | 320000 | 80057 | 80057 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 18 | 80014 | 0 | 14 | 80014 | 6 | 1 | 13 | 18 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80054 | 0 | 10 | 0 | 80000 | 320000 | 100 | 80058 | 80042 | 80058 | 80058 | 80058 |
400204 | 80057 | 599 | 0 | 0 | 0 | 0 | 20 | 0 | 1 | 0 | 80042 | 1 | 6 | 6 | 0 | 25 | 400100 | 100 | 320000 | 80000 | 100 | 320000 | 80000 | 500 | 400011 | 3840000 | 1 | 80022 | 0 | 80057 | 80057 | 3 | 39 | 400100 | 200 | 80000 | 320000 | 200 | 80000 | 320000 | 80057 | 80057 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 18 | 80014 | 0 | 14 | 80014 | 6 | 1 | 13 | 18 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80054 | 1 | 0 | 10 | 80000 | 320000 | 100 | 80108 | 80042 | 80058 | 80058 | 80047 |
400204 | 80041 | 600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 80026 | 1 | 0 | 0 | 0 | 25 | 400164 | 100 | 320064 | 80000 | 100 | 320000 | 80000 | 500 | 400009 | 8640020 | 1 | 80022 | 0 | 80041 | 80041 | 3 | 39 | 400100 | 200 | 80000 | 320000 | 200 | 80000 | 320000 | 80044 | 80041 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 80013 | 0 | 0 | 80014 | 0 | 1 | 13 | 18 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80054 | 1 | 10 | 10 | 80000 | 320000 | 100 | 80042 | 80042 | 80042 | 80058 | 80042 |
Result (median cycles for code divided by count): 1.0007
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | 0e | 0f | 1e | 1f | 22 | 24 | 3f | 43 | 46 | 49 | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | db | dd | fetch restart (de) | e0 | e7 | ea | eb | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
400025 | 80057 | 599 | 0 | 1 | 0 | 0 | 1377 | 0 | 1 | 0 | 80042 | 1 | 6 | 6 | 0 | 25 | 400074 | 10 | 320064 | 80000 | 10 | 320000 | 80000 | 50 | 400018 | 3840000 | 0 | 80038 | 80057 | 80057 | 3 | 39 | 400010 | 20 | 80000 | 320000 | 20 | 80000 | 320000 | 80041 | 80057 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 18 | 80013 | 1 | 0 | 80000 | 6 | 1 | 14 | 0 | 0 | 5019 | 5 | 17 | 0 | 3 | 3 | 80054 | 0 | 10 | 10 | 80000 | 320000 | 10 | 80061 | 80042 | 80058 | 80058 | 80042 |
400024 | 80057 | 600 | 0 | 0 | 0 | 0 | 19 | 0 | 1 | 0 | 80026 | 0 | 6 | 0 | 0 | 25 | 400086 | 10 | 320064 | 80000 | 10 | 320000 | 80000 | 50 | 400000 | 8640020 | 0 | 80022 | 80041 | 80057 | 3 | 39 | 400010 | 20 | 80000 | 320000 | 20 | 80000 | 320000 | 80057 | 80057 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 18 | 80014 | 0 | 14 | 80014 | 6 | 1 | 14 | 0 | 0 | 5019 | 4 | 17 | 0 | 2 | 2 | 80054 | 1 | 10 | 10 | 80000 | 320000 | 10 | 80058 | 80058 | 80058 | 80058 | 80042 |
400024 | 80041 | 600 | 0 | 0 | 0 | 0 | 20 | 0 | 1 | 0 | 80042 | 1 | 6 | 6 | 0 | 25 | 400010 | 10 | 320000 | 80000 | 10 | 320000 | 80000 | 50 | 400009 | 3840000 | 0 | 80022 | 80041 | 80041 | 3 | 39 | 400010 | 20 | 80000 | 320000 | 20 | 80000 | 320000 | 80057 | 80057 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 18 | 80014 | 0 | 14 | 80014 | 6 | 0 | 0 | 18 | 0 | 5019 | 2 | 17 | 0 | 2 | 3 | 80054 | 0 | 0 | 10 | 80000 | 320000 | 10 | 80058 | 80171 | 80275 | 80058 | 80058 |
400024 | 80057 | 600 | 0 | 0 | 0 | 0 | 928 | 0 | 1 | 0 | 80042 | 1 | 0 | 6 | 0 | 25 | 400074 | 10 | 320000 | 80000 | 10 | 320000 | 80000 | 50 | 400000 | 3840000 | 0 | 80022 | 80060 | 80041 | 3 | 39 | 400010 | 20 | 80000 | 320000 | 20 | 80000 | 320000 | 80057 | 80057 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 18 | 80013 | 1 | 25 | 80013 | 0 | 1 | 14 | 0 | 0 | 5019 | 2 | 17 | 0 | 2 | 2 | 80054 | 1 | 10 | 10 | 80000 | 320000 | 10 | 80058 | 80058 | 80058 | 80058 | 80042 |
400024 | 80057 | 600 | 0 | 0 | 0 | 0 | 20 | 0 | 1 | 0 | 80026 | 1 | 6 | 0 | 0 | 25 | 400010 | 10 | 320000 | 80000 | 10 | 320000 | 80000 | 50 | 400000 | 8640020 | 1 | 80038 | 80057 | 80057 | 3 | 39 | 400010 | 20 | 80000 | 320000 | 20 | 80000 | 320000 | 80041 | 80057 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 18 | 80014 | 0 | 14 | 80014 | 0 | 1 | 14 | 18 | 0 | 5019 | 2 | 17 | 0 | 2 | 2 | 80041 | 0 | 10 | 10 | 80000 | 320000 | 10 | 80109 | 80058 | 80058 | 80058 | 80058 |
400024 | 80057 | 599 | 0 | 0 | 0 | 0 | 898 | 0 | 1 | 0 | 80042 | 1 | 6 | 6 | 0 | 25 | 400074 | 10 | 320064 | 80000 | 10 | 320000 | 80000 | 50 | 400015 | 3840000 | 0 | 80038 | 80057 | 80057 | 3 | 39 | 400010 | 20 | 80000 | 320000 | 20 | 80000 | 320000 | 80041 | 80057 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 18 | 80013 | 0 | 14 | 80000 | 6 | 1 | 14 | 18 | 0 | 5019 | 2 | 17 | 0 | 2 | 2 | 80038 | 1 | 10 | 10 | 80000 | 320000 | 10 | 80058 | 80058 | 80058 | 80058 | 80058 |
400024 | 80057 | 599 | 0 | 0 | 0 | 0 | 20 | 0 | 1 | 0 | 80042 | 0 | 6 | 6 | 0 | 25 | 400010 | 10 | 320064 | 80000 | 10 | 320000 | 80000 | 50 | 400000 | 8640024 | 0 | 80038 | 80041 | 80057 | 3 | 39 | 400010 | 20 | 80000 | 320000 | 20 | 80000 | 320000 | 80057 | 80057 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 80014 | 0 | 0 | 80014 | 6 | 1 | 0 | 18 | 0 | 5019 | 2 | 17 | 0 | 2 | 3 | 80054 | 1 | 10 | 10 | 80000 | 320000 | 10 | 80042 | 80058 | 80156 | 80058 | 80058 |
400024 | 80057 | 600 | 1 | 0 | 0 | 0 | 19 | 0 | 1 | 0 | 80042 | 1 | 6 | 6 | 0 | 25 | 400086 | 10 | 320076 | 80000 | 10 | 320000 | 80000 | 50 | 400018 | 8640020 | 0 | 80038 | 80057 | 80041 | 3 | 39 | 400010 | 20 | 80000 | 320000 | 20 | 80000 | 320000 | 80041 | 80057 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 18 | 80013 | 0 | 14 | 80000 | 6 | 0 | 0 | 18 | 0 | 5019 | 3 | 17 | 0 | 2 | 2 | 80054 | 1 | 0 | 0 | 80000 | 320000 | 10 | 80058 | 80155 | 80045 | 80058 | 80058 |
400024 | 80041 | 600 | 0 | 0 | 0 | 0 | 995 | 0 | 1 | 0 | 80042 | 1 | 0 | 0 | 50 | 25 | 400074 | 10 | 320064 | 80000 | 10 | 320000 | 80000 | 50 | 400009 | 8640020 | 0 | 80038 | 80060 | 80057 | 3 | 42 | 400010 | 20 | 80000 | 320000 | 20 | 80050 | 320000 | 80057 | 80142 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 18 | 80013 | 0 | 14 | 80013 | 0 | 1 | 13 | 18 | 0 | 5019 | 2 | 17 | 0 | 2 | 2 | 80054 | 1 | 0 | 10 | 80000 | 320000 | 10 | 80058 | 80042 | 80058 | 80042 | 80058 |
400024 | 80041 | 600 | 0 | 0 | 1 | 0 | 947 | 0 | 1 | 0 | 80026 | 1 | 6 | 6 | 0 | 25 | 400074 | 10 | 320064 | 80000 | 10 | 320000 | 80000 | 50 | 400011 | 3840000 | 0 | 80038 | 80057 | 80057 | 3 | 39 | 400010 | 20 | 80000 | 320000 | 20 | 80000 | 320000 | 80057 | 80057 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 18 | 80000 | 0 | 17 | 80014 | 0 | 1 | 13 | 0 | 0 | 5019 | 2 | 17 | 0 | 2 | 2 | 80054 | 0 | 10 | 10 | 80000 | 320000 | 10 | 80058 | 80058 | 80042 | 80042 | 80045 |