Firestorm: LD4R (8B) measurements

Code:

  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.008

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	0e	0f	18	19	1e	1f	22	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
65005	28500	213	16	0	17	0	1	0	0	9	0	1	4988	28031	0	1	1	16004	5000	4000	1000	4000	1000	5000	47548	3	1	0	22963	28209	28402	3	10	5000	1000	4000	1000	4000	28218	28195	1	1	61001	1000	1000	1	1001	0	2	1002	0	0	5	1000	1	2	2	13849	10080	7179	3392	8	51	19243	3319	3817	31	46	49	27979	14546	12765	13512	1000	4000	28835	29035	28595	28929	28561
65004	28954	213	27	0	18	0	0	6	5	792	176	1	4762	28372	0	0	1	16370	5025	4020	1001	4012	1000	5099	47560	4	1	8	22939	28835	28372	38	80	5015	1003	4000	1000	4000	28232	28433	1	1	61001	1000	1000	0	1000	0	2	1002	3	0	5	1001	1	0	2	13771	9991	7122	3349	6	47	19220	3404	3812	21	52	54	27926	14518	12619	13679	1000	4000	28736	28548	28848	28988	28576
65004	28323	211	15	0	18	0	0	0	0	2	264	1	4913	28403	0	1	1	16482	5012	4008	1002	4000	1004	5045	48012	2	0	7	23144	28580	28843	29	123	5015	1001	4016	1004	4008	28204	28687	7	1	61001	1000	1000	0	1003	2	0	1005	0	2	7	1003	1	1	2	13720	10247	7221	3291	10	45	19162	3350	3812	29	49	50	27917	14553	12593	13355	1000	4000	28558	28635	28368	28364	28282
65004	28464	213	14	0	16	0	0	0	0	2	0	1	5097	28035	1	1	1	16250	5012	4008	1000	4000	1000	5000	47520	3	0	8	22998	28219	28262	19	46	5000	1000	4000	1000	4000	28418	28343	1	1	61001	1000	1000	0	1000	0	2	1000	1	0	14	1002	1	1	2	13438	10077	7146	3359	8	46	19257	3387	3822	26	51	49	27940	14257	12432	13192	1000	4000	28804	28497	28542	28479	28378
65004	28374	212	20	0	18	0	0	0	0	3	0	0	5006	28042	0	1	1	15938	5008	4012	1000	4000	1000	5000	47558	4	1	0	22998	28140	28248	3	10	5000	1000	4000	1000	4000	28186	28222	1	1	61001	1000	1000	0	1000	0	2	1001	0	0	0	1000	0	2	2	13826	10371	7159	3357	6	53	19188	3331	3817	19	40	52	28062	14115	12523	13210	1000	4000	28508	28413	28503	28273	28450
65004	28403	212	17	0	20	0	1	0	0	0	0	1	5107	28188	0	1	0	16100	5008	4008	1000	4000	1000	5000	47514	3	1	0	22924	28209	28251	3	10	5000	1000	4000	1000	4000	28404	28237	1	1	61001	1000	1000	0	1000	0	2	1001	2	0	1	1001	1	1	2	13799	10075	7125	3383	9	43	19256	3391	3817	22	43	47	27912	14316	12352	12943	1000	4000	28511	28343	28345	28351	28470
65004	28493	213	15	0	19	0	0	0	0	7	0	0	5045	28008	0	0	0	16021	5008	4000	1000	4000	1000	5000	47578	3	0	0	22940	28195	28276	3	10	5000	1000	4000	1000	4000	28294	28185	1	1	61001	1000	1000	0	1000	0	0	1001	0	0	2	1002	0	2	0	13864	10195	7150	3377	9	53	19260	3391	3816	23	43	44	27879	14617	12477	13343	1000	4000	28628	28484	28592	28238	28311
65004	28274	212	18	0	16	0	0	0	0	2	0	1	4943	28035	1	1	1	15949	5012	4012	1000	4000	1000	5000	47508	1	1	0	22939	28187	28248	3	10	5000	1000	4000	1000	4000	28194	28311	1	1	61001	1000	1000	0	1000	0	0	1001	0	0	0	1001	1	1	2	13909	10135	7191	3368	10	52	19436	3362	3818	22	47	47	28023	14368	12566	13517	1000	4000	28557	28334	28440	28552	28474
65004	28291	212	17	0	14	0	0	0	0	3	0	0	4876	28098	0	1	1	16156	5012	4012	1000	4000	1000	5000	47572	3	0	8	22949	28178	28220	3	10	5000	1000	4000	1000	4000	28246	28267	1	1	61001	1000	1000	0	1000	0	0	1001	0	0	1	1001	1	2	2	13774	9992	7161	3419	7	49	19258	3449	3811	19	52	50	27920	14465	12406	13377	1000	4000	28594	28417	28597	28294	28412
65004	28366	213	18	0	17	1	1	0	0	3	0	1	5104	28043	0	1	0	16202	5000	4012	1000	4000	1000	5000	47568	4	0	0	22918	28223	28325	3	10	5000	1000	4000	1000	4000	28267	28271	1	1	61001	1000	1000	0	1000	0	0	1001	0	0	0	1001	1	1	0	13718	10368	7179	3390	8	44	19252	3328	3814	23	52	55	27801	14380	12611	13422	1000	4000	28516	28502	28523	28394	28350

Count: 8

Code:

  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	0e	0f	1e	1f	22	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	80067	600	0	1	1	20	0	1	1	80042	1	6	0	25	400164	100	320064	80000	100	320000	80000	500	400038	8640020	0	80038	0	80057	80057	0	3	39	400100	200	80000	320000	200	80000	320000	80057	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80007	18	80014	0	0	13	80000	6	1	0	18	5109	2	17	2	2	80054	0	10	10	0	80000	320000	100	80067	80048	80058	80058	80058
400204	80057	600	0	0	0	19	0	1	0	80042	1	6	0	25	400164	100	320064	80000	100	320000	80000	500	400009	8640020	0	80038	0	80057	80057	0	3	39	400100	200	80000	320000	200	80000	320000	80057	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80014	0	0	0	80014	6	1	14	18	5109	2	17	2	2	80054	0	10	10	0	80000	320000	100	80058	80058	80058	80398	80058
400204	80057	599	0	0	0	20	0	1	0	80042	1	6	6	25	400164	100	320064	80000	100	320000	80000	500	400009	8640020	0	80038	0	80057	80057	0	3	39	400100	200	80000	320000	200	80000	320000	80041	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80013	0	0	14	80013	6	1	14	18	5109	2	17	2	2	80054	1	10	10	0	80000	320000	100	80058	80058	80058	80058	80067
400204	80057	600	0	0	0	63	0	1	0	80042	1	6	6	25	400164	100	320064	80000	100	320000	80000	500	400011	8640020	0	80038	0	80057	80041	0	3	39	400100	200	80000	320000	200	80000	320000	80057	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80014	0	0	13	80014	6	1	14	18	5109	2	17	2	2	80054	0	10	10	0	80000	320000	100	80058	80058	80058	80058	80042
400204	80057	599	0	0	0	20	0	1	0	80042	1	6	6	25	400164	100	320000	80000	100	320000	80000	500	400009	3840000	0	80038	0	80057	80057	0	3	23	400100	200	80000	320000	200	80000	320000	80057	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80000	18	80000	0	0	0	80014	6	1	13	18	5109	1	17	2	2	80038	1	10	13	2	80000	320000	100	80067	80058	80058	80058	80058
400204	80041	599	0	0	0	29	0	1	0	80042	0	6	6	25	400100	100	320000	80000	100	320000	80000	500	400009	3840000	0	80038	0	80057	80057	0	3	39	400100	200	80000	320000	200	80000	320000	80057	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80000	0	0	14	80014	0	1	13	18	5109	2	17	2	2	80054	0	0	10	0	80000	320000	100	80058	80051	80058	80058	80058
400204	80057	600	0	0	0	19	0	1	0	80042	1	6	6	25	400164	100	320064	80000	100	320000	80000	500	400018	8640020	0	80022	0	80057	80057	0	3	39	400100	200	80000	320000	200	80000	320000	80057	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80013	0	0	14	80000	6	0	14	18	5109	2	17	2	2	80054	0	0	10	0	80000	320000	100	80058	80058	80058	80449	80058
400204	80041	599	0	0	0	19	0	1	0	80042	1	6	6	25	400164	100	320064	80000	100	320000	80000	500	400009	8640020	0	80038	0	80057	80041	0	3	39	400100	200	80000	320000	200	80000	320000	80047	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80014	0	0	14	80014	6	0	14	18	5109	2	17	2	2	80054	0	10	0	0	80000	320000	100	80058	80058	80047	80058	80058
400204	80057	600	0	0	0	19	0	1	0	80042	1	6	6	25	400164	100	320064	80000	100	320000	80000	500	400009	8640020	0	80038	0	80057	80057	0	3	39	400100	200	80000	320000	200	80000	320000	80057	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80014	0	0	13	80014	6	1	14	18	5109	2	17	2	2	80054	0	10	10	0	80000	320000	100	80058	80058	80058	80058	80058
400204	80057	600	0	0	0	19	0	1	0	80042	1	6	0	25	400164	100	320064	80000	100	320000	80000	500	400018	3840000	0	80038	0	80041	80041	0	3	39	400100	200	80000	320000	200	80000	320000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	18	80014	0	0	14	80047	6	1	13	18	5109	2	17	2	2	80054	1	0	10	0	80000	320000	100	80058	80051	80058	80058	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	0e	0f	18	19	1e	1f	22	23	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80475	600	0	0	0	0	0	20	0	1	0	80042	1	6	6	0	25	400086	10	320076	80000	10	320000	80000	50	400020	8640020	0	80041	80060	80060	0	3	39	400010	20	80000	320000	20	80000	320000	80041	80057	1	1	80021	10	9	10	10	80000	80000	1	10	80194	0	18	80014	0	0	17	80014	6	1	0	0	5019	7	17	0	4	2	80054	1	0	10	80000	320000	10	80347	80058	80058	80058	80061
400024	80041	599	0	0	0	0	0	0	0	0	0	80045	1	6	6	0	25	400074	10	320076	80000	10	320000	80000	50	400000	9600020	0	80041	80060	80041	0	3	23	400010	20	80000	320000	20	80000	320000	80060	80057	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	0	80018	0	0	0	80018	6	1	0	22	5019	4	17	0	3	5	80041	1	13	0	80000	320000	10	80058	80058	80058	80058	80042
400024	80041	600	0	0	0	0	0	19	0	0	0	80042	1	6	6	0	25	400086	10	320000	80000	10	320000	80000	50	400024	8640020	0	80041	80060	80060	0	3	42	400010	20	80000	320000	20	80000	320000	80060	80057	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	18	80000	0	0	17	80000	6	0	0	18	5019	2	17	0	2	4	80057	0	13	10	80000	320000	10	80061	80061	80061	80058	80058
400024	80060	600	0	0	0	0	0	20	0	1	0	80045	1	6	6	0	25	400086	10	320076	80000	10	320000	80000	50	400050	9600020	0	80038	80041	80060	0	3	42	400010	20	80000	320000	20	80000	320000	80060	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	22	80054	0	0	0	80018	6	0	0	0	5019	4	17	0	4	4	80057	0	0	0	80000	320000	10	80061	80058	80058	80061	80058
400024	80060	600	0	1	1	0	0	19	0	1	0	80042	1	6	6	0	25	400074	10	320000	80000	10	320000	80000	50	400008	8640020	0	80038	80060	80041	0	3	42	400010	20	80000	320000	20	80000	320000	80060	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80013	0	0	0	80017	6	0	13	18	5019	5	17	0	5	5	80054	1	10	10	80000	320000	10	80058	80042	80058	80042	80042
400024	80060	599	0	0	0	0	0	24	0	0	0	80026	1	6	6	0	25	400010	10	320064	80000	10	320800	80000	50	400000	8640020	0	80038	80057	80041	0	3	23	400010	20	80000	320000	20	80000	320000	80041	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80000	0	0	14	80000	6	1	13	18	5019	4	17	0	4	2	80038	0	13	0	80000	320000	10	80061	80058	80042	80061	80058
400024	80060	600	0	0	0	0	0	24	0	1	0	80045	1	6	0	0	25	400010	10	320076	80000	10	320800	80000	50	400009	8640020	1	80022	80041	80057	0	3	192	400010	20	80000	320000	20	80000	320000	80057	80041	2	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80017	0	0	3	80161	6	1	18	0	5019	4	17	0	2	4	80038	1	0	10	80000	320000	10	80058	80058	80058	80058	80042
400024	80057	600	0	0	0	0	0	35	0	0	0	80045	1	6	6	0	25	400086	10	320064	80000	10	320000	80000	50	400024	9600020	0	80041	80445	80060	0	3	24	400010	20	80000	320000	20	80000	320000	80060	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80018	3	0	18	80018	6	0	17	22	5019	2	17	0	5	8	80057	0	13	0	80000	320000	10	80058	80051	80061	80058	80058
400024	80041	600	0	0	0	0	0	0	0	1	0	80026	1	0	0	0	25	400074	10	320000	80000	10	320000	80000	50	400011	8640020	0	80038	80057	80057	0	3	42	400010	20	80000	320000	20	80000	320000	80057	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80018	0	0	0	80017	0	1	0	22	5019	2	17	0	4	4	80057	1	13	10	80000	320000	10	80061	80058	80042	80061	80061
400024	80060	600	0	0	0	0	0	23	0	0	0	80045	0	0	0	0	125	400086	10	320076	80000	10	320000	80000	50	400021	9600020	0	80041	80044	80060	0	3	23	400010	20	80000	320000	20	80000	320000	80057	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80192	0	0	80014	0	0	18	80017	6	1	0	18	5019	4	17	0	4	2	80039	0	13	0	80000	320000	10	80058	80042	80061	80061	80061

LD4R (8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations