Firestorm: LD4R (8H) measurements

Code:

  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.008

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.012

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	df	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
65005	28785	215	5	5	0	1	3	0	0	0	2	1	0	5140	28088	0	0	1	16072	5012	4012	1000	4000	1000	5000	47520	8	22938	0	28363	28454	3	10	5000	1000	4000	1000	4000	28225	28281	1	1	61001	1000	1000	0	1000	0	2	1000	0	6	1000	2	2	2	0	13577	10244	7060	3201	2	74	19309	3215	3811	14	53	56	2	27944	15276	12605	13553	1000	4000	28346	28175	28544	28433	28411
65004	28423	213	4	5	0	0	6	0	0	0	4	0	0	5138	28135	0	1	1	16327	5008	4012	1000	4000	1000	5000	47533	3	22940	0	28314	28223	3	10	5000	1000	4000	1000	4000	28269	28360	1	1	61001	1000	1000	1	1000	0	2	1001	0	3	1001	2	2	3	0	13904	10020	7165	3399	2	57	19238	3256	3814	14	52	50	2	27895	14401	12767	13055	1000	4000	28396	27991	28629	28415	28455
65004	28357	214	2	2	0	0	5	0	0	0	4	1	0	5093	27947	0	0	0	16092	5012	4008	1000	4000	1000	5000	47534	0	22941	0	28248	28426	3	10	5000	1000	4000	1000	4000	28232	28287	1	1	61001	1000	1000	0	1000	0	2	1000	0	3	1000	2	2	2	0	13365	9738	7112	3422	2	54	19296	3219	3802	14	67	56	2	27956	14738	12770	13999	1000	4000	28309	28424	28652	28399	28423
65004	28633	215	4	5	0	0	5	0	0	0	2	1	0	5112	28077	0	0	0	16128	5008	4012	1000	4000	1000	5000	47538	1	22942	0	28359	28530	3	10	5000	1000	4000	1000	4000	28288	28249	1	1	61001	1000	1000	0	1000	0	2	1001	0	3	1000	2	1	2	1	13383	10051	7102	3191	1	58	19435	3378	3807	9	58	53	2	27985	14314	12841	13317	1000	4000	28289	28405	28402	28192	28289
65004	28629	212	4	4	0	1	5	0	0	0	3	1	0	4821	28254	1	0	0	16007	5008	4012	1000	4000	1000	5001	47518	3	22991	0	28231	28239	3	10	5000	1000	4000	1000	4000	28304	28353	1	1	61001	1000	1000	0	1000	0	2	1000	0	4	1000	1	1	3	0	13831	9604	7213	3386	6	61	19397	3264	3810	18	58	52	2	28011	14557	13160	13889	1000	4000	28545	28453	28363	28275	28590
65004	28322	213	5	5	0	0	5	0	0	0	3	1	0	5015	28109	1	0	0	15951	5008	4012	1000	4000	1000	5010	47558	16	22899	0	28244	28291	3	10	5000	1000	4000	1000	4000	28258	28174	1	1	61001	1000	1000	0	1000	0	2	1000	0	3	1000	2	1	2	0	13304	9912	7089	3318	6	56	19264	3249	3809	11	59	57	2	27998	14622	12756	13400	1000	4000	28456	28425	28290	28486	28539
65004	28490	213	5	6	0	0	7	0	0	0	2	1	0	5068	28024	1	0	0	16140	5008	4012	1000	4000	1000	5000	47534	13	22948	0	28357	28667	3	10	5000	1000	4000	1000	4000	28296	28260	1	1	61001	1000	1000	0	1000	0	2	1000	0	3	1000	2	2	2	0	13905	9913	7069	3268	7	54	19267	3291	3812	17	60	63	2	27882	14599	12540	13182	1000	4000	28200	28325	28325	28493	28268
65004	28380	213	5	3	0	0	5	0	0	0	2	0	0	5062	28259	1	0	0	16116	5008	4012	1000	4000	1000	5001	47563	6	22976	0	28153	28308	3	10	5000	1000	4000	1000	4000	28236	28197	1	1	61001	1000	1000	0	1000	0	2	1001	0	3	1000	2	0	2	0	13944	10206	7171	3334	4	55	19249	3353	3799	16	58	53	2	27864	15036	12374	13427	1000	4000	28449	28248	28364	28262	28366
65004	28599	214	5	4	0	0	4	0	0	0	3	1	0	5026	27966	1	0	0	16183	5008	4012	1000	4000	1000	5000	47559	5	22966	0	28225	28483	3	10	5000	1000	4000	1000	4000	28309	28287	1	1	61001	1000	1000	0	1000	0	2	1001	1	94	1000	2	0	3	0	13581	9973	7116	3361	7	58	19285	3290	3808	10	59	60	2	27896	14703	12547	13765	1000	4000	28417	28270	28585	28465	28582
65004	28331	212	7	4	0	0	4	0	0	0	2	1	0	4951	28049	1	0	0	15919	5008	4012	1000	4000	1000	5002	47562	5	22954	0	28215	28171	3	10	5000	1000	4000	1000	4000	28054	28609	1	1	61001	1000	1000	0	1000	0	2	1000	0	6	1000	2	0	2	0	13639	9987	7094	3300	2	60	19263	3273	3806	19	56	61	2	27955	14791	12763	13139	1000	4000	28344	28437	28388	28440	28474

Count: 8

Code:

  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	22	24	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	80066	599	1	1	1	1	1	0	6	0	1	0	0	80432	1	0	6	2	25	400152	100	320024	80000	100	320000	80000	500	400054	10880304	0	80047	80047	80047	0	0	3	48	400100	200	80000	320000	200	80000	320000	80071	80071	1	1	80201	100	99	100	100	80000	80000	0	100	80007	8	28	80030	0	1	1	7	80023	6	1	31	0	6	1	0	0	5109	0	1	17	1	1	80044	1	0	13	2	80000	320000	100	80547	80048	80067	80067	80048
400204	80066	599	1	1	1	2	0	0	37	0	1	0	0	80032	1	0	6	0	25	400100	100	320076	80000	100	320000	80000	500	400029	4403096	1	80027	80060	80041	0	0	3	42	400100	200	80000	320000	200	80000	320000	80060	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80013	0	0	0	14	80000	6	1	14	18	0	0	0	0	5109	0	1	17	1	1	80038	0	10	10	0	80000	320000	100	80047	80061	80061	80061	80061
400204	80041	599	0	0	0	0	0	0	0	0	1	0	0	80042	0	6	6	0	25	400164	100	320064	80000	100	320000	80000	500	400009	8640020	1	80038	80057	80057	0	0	3	42	400100	200	80000	320000	200	80000	320000	80057	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80018	0	1	0	0	80000	0	0	0	22	0	0	0	0	5109	0	1	17	1	1	80057	1	10	10	0	80000	320000	100	80057	80061	80058	80058	80061
400204	80057	600	0	0	0	0	0	0	24	0	0	0	0	80045	1	6	6	0	25	400100	100	320076	80000	100	320000	80000	500	400029	8640020	1	80041	80057	80041	0	0	3	42	400100	200	80000	320000	200	80000	320000	80057	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80014	0	0	0	16	80014	0	1	13	18	0	0	0	0	5109	0	1	17	1	1	80054	0	10	10	0	80000	320000	100	80058	80045	80058	80058	80061
400204	80041	599	0	0	0	0	0	0	0	0	0	0	0	80045	1	0	6	0	25	400100	100	320064	80000	100	320000	80000	500	400000	9600020	1	80022	80041	80060	0	0	3	42	400100	200	80000	320000	200	80000	320000	80060	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80018	0	1	0	0	80018	0	0	14	18	0	0	0	0	5109	0	1	17	1	1	80054	1	0	10	0	80000	320000	100	80058	80045	80058	80058	80058
400204	80041	599	0	0	0	0	0	0	0	0	0	0	0	80045	0	6	6	0	25	400176	100	320076	80000	100	320000	80000	500	400021	3840000	1	80022	80092	80057	0	0	3	39	400100	200	80000	320000	200	80000	320000	80057	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80013	0	0	0	0	80014	6	0	13	0	0	0	0	0	5109	0	1	17	1	1	80038	0	0	10	0	80000	320000	100	80058	80058	80058	80349	80042
400204	80057	600	0	0	0	0	0	0	19	0	0	0	0	80026	1	6	6	0	25	400176	100	320064	80000	100	320000	80000	500	400000	8640020	0	80022	80060	80060	0	0	3	39	400100	200	80000	320000	200	80000	320000	80060	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80018	0	0	0	17	80018	0	1	18	22	0	0	0	0	5109	0	1	17	1	1	80054	0	0	10	0	80000	320000	100	80061	80045	80061	80042	80042
400204	80060	599	0	0	0	0	0	0	24	0	0	0	0	80026	1	6	6	0	25	400176	100	320000	80000	100	320000	80000	500	400000	8640020	1	80038	80057	80057	0	0	3	42	400100	200	80000	320000	200	80000	320000	80060	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80013	0	0	0	0	80018	6	1	14	22	0	0	0	0	5109	0	1	17	1	1	80057	0	10	10	0	80000	320000	100	80061	80058	80058	80042	80042
400204	80060	599	0	0	0	0	0	0	0	0	0	0	0	80026	0	6	6	0	25	400176	100	320076	80000	100	320000	80000	500	400024	9600020	1	80041	80044	80057	0	0	3	42	400100	200	80000	320000	200	80000	320000	80060	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80014	0	0	0	0	80018	6	1	0	0	0	0	0	0	5109	0	1	17	1	1	80041	1	13	13	0	80000	320000	100	80067	80048	80067	80067	80067
400204	80047	600	1	1	1	1	0	1	37	0	1	0	0	80051	0	0	6	0	25	400148	100	320072	80000	100	320000	80000	500	400054	5440028	1	80041	80041	80041	0	0	3	23	400100	200	80000	320000	200	80000	320000	80060	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80000	0	0	0	17	80018	6	0	14	22	0	0	0	0	5109	0	1	17	1	1	80054	0	10	10	0	80000	320000	100	80058	80058	80058	80058	80058

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80062	600	1	1	0	0	1	0	31	1	0	0	80047	1	0	0	25	400034	10	320052	80000	10	320000	80000	50	400038	10240016	80043	80062	80047	0	3	44	400010	20	80000	320000	20	80000	320000	80047	80047	1	1	80021	10	9	10	10	80000	80000	0	10	80007	8	23	80008	0	1	1	29	80019	6	0	25	23	7	0	5019	0	0	5	17	0	5	5	80059	0	0	9	2	80000	320000	10	80048	80063	80063	80063	80063
400024	80062	600	1	1	0	0	0	0	7	1	0	0	80047	0	0	6	25	400062	10	320024	80000	10	320000	80000	50	400003	10240016	80043	80062	80047	0	3	44	400010	20	80000	320000	20	80000	320000	80062	80062	1	1	80021	10	9	10	10	80000	80000	1	10	80006	6	0	80027	0	0	0	25	80019	0	1	26	24	7	0	5019	0	0	4	17	0	5	5	80059	0	9	0	2	80000	320000	10	80048	80063	80048	80048	80063
400024	80062	599	1	1	0	0	0	0	32	0	0	0	80032	1	0	6	25	400062	10	320024	80000	10	320000	80000	50	400003	10240016	80028	80047	80062	0	3	44	400010	20	80000	320000	20	80000	320000	80047	80062	1	1	80021	10	9	10	10	80000	80000	1	10	80008	7	0	80028	0	0	2	7	80000	6	0	25	23	6	0	5019	0	0	4	17	4	6	5	80044	0	9	9	0	80000	320000	10	80063	80048	80048	80048	80063
400024	80062	599	1	1	0	0	0	0	31	0	0	0	80032	0	6	0	25	400062	10	320052	80000	10	320000	80000	50	400003	5440024	80043	80062	80062	0	3	29	400010	20	80000	320000	20	80000	320000	80047	80047	1	1	80021	10	9	10	10	80000	80000	1	10	80008	6	24	80026	0	0	0	26	80020	6	1	25	24	6	1	5019	1	0	4	17	0	5	4	80059	0	9	0	2	80000	320000	10	80063	80063	80048	80063	80063
400024	80062	599	1	0	0	0	0	0	32	1	0	0	80047	0	6	6	25	400062	10	320052	80000	10	320000	80000	50	400038	10240016	80028	80062	80062	0	3	44	400010	20	80000	320000	20	80000	320000	80062	80062	1	1	80021	10	9	10	10	80000	80000	1	10	80007	7	24	80025	0	1	1	25	80000	6	0	26	0	7	1	5019	0	0	5	17	0	5	6	80059	1	9	9	2	80000	320000	10	80063	80048	80063	80048	80048
400024	80062	599	1	0	0	1	0	0	31	0	0	1	80047	1	6	6	25	400034	10	320052	80000	10	320000	80000	50	400038	5440028	80043	80062	80047	0	3	44	400010	20	80000	320000	20	80000	320000	80062	80062	1	1	80021	10	9	10	10	80000	80000	1	10	80008	8	24	80026	0	0	0	26	80000	6	0	7	24	6	1	5019	0	0	5	17	0	8	5	80059	0	0	9	0	80000	320000	10	80063	80048	80048	80063	80063
400024	80047	600	1	0	0	0	0	0	32	0	0	0	80047	1	6	6	25	400062	10	320024	80000	10	320000	80000	50	400038	10240016	80043	80062	80062	0	3	29	400275	20	80000	320000	20	80000	320000	80062	80062	1	1	80021	10	9	10	10	80000	80000	1	10	80006	7	24	80026	0	0	0	26	80020	6	1	7	0	6	1	5019	0	0	4	17	0	6	6	80059	0	0	9	2	80000	320000	10	80048	80063	80063	80048	80048
400024	80047	600	1	0	0	1	0	0	33	0	0	0	80047	1	6	6	25	400062	10	320052	80000	10	320000	80000	50	400004	10240016	80028	80062	80062	0	3	29	400010	20	80000	320000	20	80000	320000	80062	80062	1	1	80021	10	9	10	10	80000	80000	1	10	80007	6	24	80026	0	0	0	26	80020	6	1	25	23	6	2	5019	0	0	5	17	0	5	5	80044	1	9	9	0	80000	320000	10	80063	80063	80063	80063	80063
400024	80062	599	1	1	0	1	0	0	32	0	0	0	80047	1	0	6	25	400062	10	320052	80000	10	320000	80000	50	400033	5440024	80043	80062	80047	0	3	44	400010	20	80000	320000	20	80000	320000	80047	80047	1	1	80021	10	9	10	10	80000	80000	0	10	80007	7	0	80027	0	0	1	7	80020	6	1	26	24	7	0	5019	0	0	5	17	0	5	6	80044	0	0	0	2	80000	320000	10	80048	80063	80063	80048	80063
400024	80062	599	1	1	0	0	0	1	32	1	0	0	80047	0	0	6	25	400062	10	320052	80000	10	320000	80000	50	400003	5440024	80043	80062	80062	0	3	44	400010	20	80000	320000	20	80000	320000	80047	80062	1	1	80021	10	9	10	10	80000	80000	1	10	80008	8	24	80008	0	0	1	26	80018	0	0	7	23	7	1	5019	0	0	5	17	0	5	5	80044	1	0	9	0	80000	320000	10	80048	80063	80063	80048	80063

LD4R (8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations