Firestorm: LD4R (post-index, 16B) measurements

Code:

  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 6.008

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	0e	0f	18	1e	1f	22	23	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
65005	29001	233	5	1	0	1	0	1	0	1	0	4	0	0	0	4737	28541	0	0	16575	6012	1000	4000	1000	1000	4000	1000	5000	5023	47526	11	22952	28688	28909	3	10	6000	1000	4000	2000	4000	28793	28807	1	1	61001	1000	1000	0	1005	1	3	1002	0	3	1497	1001	0	1	2	1040	13240	9329	6915	3131	0	56	20153	3339	3812	25	58	53	28133	1000	15625	12647	13809	1000	4000	1000	29010	28785	28814	28788	28811
65004	28896	231	1	0	1	0	0	0	0	0	1	18	0	1	0	4620	28296	0	0	16346	6012	1001	4012	1000	1000	4000	1000	5000	5024	47512	10	22875	28686	28751	3	10	6000	1000	4000	2000	4000	28694	28611	1	1	61001	1000	1000	0	1003	0	2	1000	0	0	0	1001	2	0	3	0	13106	9439	6953	3192	0	48	19605	3333	3815	16	53	55	28372	1000	15833	12701	13901	1000	4000	1000	28641	28768	28788	28830	28711
65004	28791	232	1	0	1	0	0	0	0	0	0	12	0	0	0	4710	28361	0	0	16356	6012	1000	4012	1000	1000	4000	1000	5000	5014	47540	12	22861	28556	28660	3	10	6000	1000	4000	2000	4000	28564	28651	1	1	61001	1000	1000	0	1000	2	3	1001	1	0	4	1001	2	1	3	0	13394	9492	6942	3281	0	50	19643	3138	3814	20	51	44	28160	1000	15524	12594	13810	1000	4000	1000	28858	28763	28709	28712	28697
65004	28721	231	2	0	0	0	0	0	0	0	0	0	0	0	0	4709	28254	0	0	16527	6012	1000	4012	1000	1000	4000	1000	5000	5000	47504	10	22965	28635	28612	3	10	6000	1000	4000	2000	4000	28634	28664	1	1	61001	1000	1000	0	1001	0	0	1001	1	0	1	1001	2	1	3	0	13084	9381	7044	3185	1	51	19712	3178	3817	23	49	54	28464	1000	15258	12704	13628	1000	4000	1000	28635	28740	28800	28603	28639
65004	28951	233	1	0	1	0	0	0	0	0	0	12	88	1	0	4733	28367	0	0	16400	6012	1000	4008	1000	1000	4000	1000	5000	5000	47548	12	22859	28376	28740	3	10	6000	1000	4000	2000	4000	28635	28441	1	1	61001	1000	1000	0	1000	0	0	1000	0	0	403	1000	1	1	3	0	13217	9333	7053	3206	0	49	19510	3188	3811	15	48	54	28161	1000	15482	12416	13743	1000	4000	1000	28683	28708	28765	28729	28633
65004	28765	222	1	0	0	0	0	1	0	0	0	14	0	0	0	4781	28361	0	0	16419	6008	1000	4012	1000	1000	4000	1000	5000	5000	47426	11	22945	28614	28586	3	10	6000	1000	4000	2000	4000	28515	28568	1	1	61001	1000	1000	0	1000	0	2	1001	0	0	0	1001	0	0	0	0	13230	9240	6990	3202	0	53	19621	3201	3818	22	59	51	28125	1000	15749	12576	13348	1000	4000	1000	28806	28620	28572	28651	28499
65004	28590	222	1	0	0	0	0	0	1	0	0	12	0	0	0	4930	28278	0	0	16414	6012	1000	4000	1000	1000	4000	1000	5000	5000	47434	9	22893	28637	28715	3	10	6000	1000	4000	2000	4000	28630	28622	1	1	61001	1000	1000	0	1000	0	2	1000	0	0	0	1002	2	1	2	0	13273	9310	7030	3205	1	53	19610	3232	3828	21	53	53	28057	1000	15666	12725	14014	1000	4000	1000	29226	30116	29507	29443	29545
65004	29619	237	6	0	8	0	0	7	0	0	0	4	0	0	0	4839	28452	1	0	16444	6012	1000	4012	1000	1000	4000	1000	5000	5000	47404	11	22972	28660	28560	3	10	6000	1000	4000	2000	4000	28840	28701	1	1	61001	1000	1000	0	1000	0	2	1001	1	0	15	1000	1	0	0	0	13231	9637	7014	3265	3	48	19476	3244	3817	16	49	49	28209	1000	15552	12744	13873	1000	4000	1000	28668	28513	28582	28628	28767
65004	28614	222	0	0	7	0	1	4	0	0	0	13	0	0	0	4616	28602	1	0	16756	6012	1000	4012	1000	1000	4000	1000	5000	5031	47520	8	22901	28941	28925	3	19	6000	1000	4000	2000	4000	28462	28522	1	1	61001	1000	1000	0	1000	0	0	1000	0	0	1	1000	0	1	2	0	13339	9787	6860	3200	3	55	19510	3275	3820	15	52	53	28071	1000	15116	12234	13714	1000	4000	1000	28712	28665	28596	28575	28507
65004	28586	222	2	0	7	0	1	5	0	0	0	3	0	0	0	4673	28376	0	1	16467	6012	1000	4008	1000	1000	4000	1000	5000	5002	47426	6	22960	28624	28774	3	10	6000	1000	4000	2000	4000	28615	28564	1	1	61001	1000	1000	0	1000	0	2	1001	0	0	0	1001	2	1	3	166	13199	9795	6978	3286	4	49	19548	3184	3821	9	58	48	28034	1000	15377	12614	13623	1000	4000	1000	28726	28771	28683	28741	28761

Count: 8

Code:

  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cd	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	80057	621	0	1	0	0	0	0	0	21	0	1	0	80045	1	6	6	0	25	480100	80100	320072	80000	80100	320000	80000	480499	480011	8640020	80041	80060	80042	0	0	3	39	480100	200	80000	320000	200	160000	320000	80060	80057	1	1	80201	100	99	100	100	80000	80000	100	80000	0	18	80016	0	0	14	80016	6	1	14	0	0	0	0	5111	0	2	17	1	2	80057	1	80000	13	10	80000	320000	80100	80062	80061	80061	80061	80061
400204	80060	620	0	0	0	0	0	0	0	0	0	0	0	80045	1	6	0	0	25	480172	80100	320072	80000	80100	320000	80000	480499	480028	8640024	80038	80057	80060	0	0	3	42	480100	200	80000	320000	200	160000	320336	80060	80057	1	1	80201	100	99	100	100	80000	80000	100	80000	0	18	80015	0	0	19	80016	6	1	14	23	0	0	0	5109	0	1	17	2	1	80057	1	80000	13	10	80000	320000	80100	80061	80061	80061	80061	80061
400204	80060	621	0	0	0	0	0	0	0	22	0	0	0	80027	1	0	0	0	25	480172	80100	320072	80000	80100	320000	80000	480499	480023	4159996	80038	80060	80060	0	0	3	42	480100	200	80000	320000	200	160000	320000	80060	80060	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	80016	0	0	13	80016	6	1	0	20	0	0	0	5109	0	1	17	1	1	80057	0	80000	13	14	80000	320000	80100	80061	80058	80061	80061	80061
400204	80060	621	0	0	0	0	0	0	0	22	0	0	1	80046	1	6	0	0	25	480172	80100	320072	80000	80100	320000	80000	480499	480015	8640020	80041	80042	80060	0	0	3	39	480100	200	80000	320000	200	160000	320000	80060	80057	1	1	80201	100	99	100	100	80000	80000	100	80000	0	18	80003	1	0	19	80016	6	0	13	0	0	0	0	5109	0	1	17	1	1	80057	1	80000	0	10	80000	320000	80100	80061	80061	80061	80061	80061
400204	80060	621	0	0	0	0	0	0	0	26	0	0	0	80045	1	6	6	0	25	480172	80100	320000	80000	80100	320000	80000	480499	480015	8640020	80041	80060	80060	0	0	3	42	480100	200	80000	320000	200	160000	320000	80060	80057	1	1	80201	100	99	100	100	80000	80000	100	80000	0	19	80015	0	0	16	80015	6	1	13	20	0	0	0	5109	0	1	17	1	2	80057	0	80000	13	10	80000	320000	80100	80061	80061	80061	80061	80062
400204	80060	621	0	0	0	0	0	0	0	23	0	0	0	80045	1	6	6	0	25	480172	80100	320072	80000	80100	320000	80000	480499	479998	4574864	80041	80060	80045	0	0	3	42	480100	200	80000	320000	200	160000	320000	80060	80057	1	1	80201	100	99	100	100	80000	80000	100	80000	0	18	80016	0	0	17	80000	6	1	0	20	0	0	0	5109	0	1	17	2	2	80057	0	80000	10	10	80000	320000	80100	80061	80061	80061	80061	80061
400204	80042	621	0	0	0	0	0	0	0	0	0	0	1	80030	1	6	6	0	25	480172	80100	320072	80000	80100	320000	80000	480499	480018	8640020	80038	80060	80060	0	0	3	42	480100	200	80000	320000	200	160000	320000	80060	80057	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	80016	0	0	16	80016	6	1	14	20	0	0	0	5109	3	1	17	1	1	80057	0	80000	13	0	80000	320000	80100	80061	80043	80061	80061	80046
400204	80060	621	0	0	0	0	0	0	0	20	0	0	1	80045	1	6	6	0	25	480172	80100	320000	80000	80100	320000	80000	480499	480019	8640020	80041	80042	80060	0	0	3	42	480100	200	80000	320000	200	160000	320000	80060	80057	1	1	80201	100	99	100	100	80000	80000	100	80000	0	19	80015	0	0	18	80014	6	1	0	20	0	0	0	5111	0	2	17	1	2	80057	1	80000	0	0	80000	320000	80100	80043	80061	80043	80061	80061
400204	80060	621	0	0	0	0	0	0	0	22	0	0	1	80045	1	6	6	0	25	480172	80100	320000	80000	80100	320000	80000	480499	480028	8640020	80041	80060	80060	0	7	3	39	480100	200	80000	320000	200	160000	320000	80060	80057	1	1	80201	100	99	100	100	80000	80000	100	80000	0	20	80016	1	0	16	80015	6	1	13	20	0	0	0	5111	0	2	17	1	2	80039	0	80000	13	13	80000	320000	80100	80061	80061	80061	80061	80061
400204	80060	620	0	0	0	0	0	0	0	0	0	0	1	80027	0	6	0	0	25	480172	80100	320000	80000	80100	320000	80000	480499	480021	9600020	80038	80060	80060	0	0	3	39	480100	200	80000	320000	200	160000	320000	80060	80057	1	1	80201	100	99	100	100	80000	80000	100	80000	0	20	80015	1	0	18	80016	6	1	16	20	0	0	0	5111	0	1	17	1	2	80057	1	80000	13	0	80000	320000	80100	80061	80061	80061	80058	80061

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	18	19	1e	1f	22	23	24	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80058	620	0	1	0	0	0	0	0	54	0	0	0	0	80045	1	6	6	0	25	480082	80010	320072	80000	80010	320000	80000	480049	480017	8640020	80041	80042	80060	0	0	3	42	480010	20	80000	320000	20	160000	320000	80060	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80016	0	0	0	17	80016	6	1	13	20	0	5019	5	17	6	5	80057	1	80000	13	13	80000	320000	80010	80061	80061	80061	80061	80061
400024	80060	620	0	0	0	0	0	0	0	36	0	1	0	0	80045	1	6	0	0	25	480082	80010	320072	80000	80010	320000	80000	480049	480031	8640020	80041	80042	80042	0	0	3	42	480010	20	80000	320000	20	160000	320000	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80015	0	1	0	19	80016	6	1	16	18	0	5019	6	17	5	6	80057	0	80000	10	13	80000	320000	80010	80061	80043	80061	80061	80062
400024	80060	621	0	0	0	0	0	0	0	282	0	0	0	0	80048	1	0	6	0	25	480082	80010	320072	80000	80010	320000	80000	480049	480015	8640020	80038	80057	80060	0	172	3	42	480010	20	80000	320000	20	160000	320000	80060	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	20	80016	0	0	0	19	80015	6	1	14	20	0	5019	5	17	7	5	80057	0	80000	13	13	80000	320000	80010	80061	80058	80061	80061	80061
400024	80060	621	0	0	0	0	0	0	0	321	0	1	0	0	80045	1	0	6	0	25	480078	80010	320072	80000	80010	320000	80000	480049	480015	8640020	80041	80060	80060	0	0	3	42	480010	20	80000	320000	20	160000	320000	80061	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80016	0	0	0	0	80015	6	1	0	20	0	5019	5	17	5	6	80057	1	80000	13	13	80000	320000	80010	80061	80061	80061	80061	80061
400024	80060	620	0	0	0	0	0	0	0	73	0	1	0	0	80045	0	6	6	0	25	480010	80010	320060	80000	80010	320000	80000	480049	480016	8640020	80041	80060	80060	0	0	3	42	480010	20	80000	320000	20	160000	320000	80060	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	20	80016	0	1	0	16	80014	0	1	13	0	0	5019	5	17	5	6	80057	1	80000	13	10	80000	320000	80010	80058	80061	80058	80058	80061
400024	80057	620	0	0	0	0	0	0	0	468	0	0	0	0	80045	1	6	6	0	25	480082	80010	320072	80000	80010	320000	80000	480049	480015	8640020	80023	80060	80060	0	0	3	39	480010	20	80000	320000	20	160000	320000	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	20	80016	0	0	0	0	80016	6	1	13	20	0	5019	6	17	5	4	80057	1	80000	13	14	80000	320000	80010	80061	80046	80061	80061	80060
400024	80060	620	0	0	0	0	0	0	0	456	0	0	0	0	80045	1	6	6	0	25	480082	80010	320072	80000	80010	320000	80000	480049	480015	8640020	80041	80060	80060	0	0	3	42	480010	20	80000	320000	20	160000	320000	80060	80059	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80015	0	0	0	16	80016	6	1	15	20	0	5019	5	17	5	5	80057	1	80000	13	10	80000	320000	80010	80061	80061	80061	80061	80061
400024	80060	620	0	0	0	0	0	0	0	493	0	0	0	0	80045	1	6	6	0	25	480082	80010	320072	80000	80010	320000	80000	480049	480021	9600020	80041	80060	80060	0	0	3	42	480010	20	80000	320000	20	160000	320000	80060	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	20	80015	0	1	0	16	80013	6	1	16	18	0	5019	5	17	5	6	80058	0	80000	13	13	80000	320000	80010	80058	80061	80061	80061	80061
400024	80042	621	0	0	0	0	0	0	0	448	0	0	0	0	80045	1	6	6	0	25	480082	80010	320072	80000	80010	320000	80000	480049	480021	8640020	80041	80060	80060	0	0	3	42	480010	20	80000	320000	20	160000	320000	80060	80061	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80016	0	0	0	14	80016	6	1	13	20	0	5019	5	17	7	5	80039	1	80000	13	10	80000	320000	80010	80061	80058	80061	80061	80061
400024	80060	620	0	0	0	0	0	0	0	106	0	0	0	0	80027	0	0	6	0	25	480082	80010	320072	80000	80010	320000	80000	480049	479998	9600020	80041	80060	80060	0	0	3	42	480328	20	80000	320000	20	160000	320000	80062	80060	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	20	80013	0	0	0	16	80016	6	1	18	20	0	5034	5	34	6	8	80287	1	80080	13	13	80000	320000	80010	80194	80349	80087	80061	80350

LD4R (post-index, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations