Firestorm: LD4R (post-index, 1D) measurements

Code:

  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.008

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
66005	28348	213	0	20	0	0	25	0	0	0	0	8	0	0	5016	28082	0	1	15647	7000	1000	4000	2000	1000	4000	2000	5000	10002	47452	16	23039	27999	28336	3	10	7000	2000	4000	3000	8000	28112	28111	1	1	61001	1000	1000	0	2000	0	4	2002	0	0	2	2002	0	2	0	0	0	13990	9981	7107	3356	12	52	19045	3352	3810	12	50	57	27888	1000	14150	12173	13083	2000	4000	1000	28519	28222	28202	28080	28606
66004	28630	212	0	18	0	0	23	0	0	0	1	8	0	0	5006	27891	0	0	15697	7008	1000	4000	2000	1000	4000	2000	5000	10003	47544	8	23011	28246	28333	3	10	7000	2000	4000	3000	8000	28224	28260	1	1	61001	1000	1000	0	2000	0	4	2002	0	0	2	2000	2	0	4	0	0	13941	9617	7128	3345	14	52	19065	3379	3812	25	51	52	27980	1000	14295	11815	12931	2000	4000	1000	28447	28312	28297	28113	28263
66004	28361	212	0	21	0	0	14	0	0	0	0	0	0	0	4865	28079	0	1	16109	7000	1000	4012	2000	1000	4000	2000	5000	10004	47544	4	23045	28262	28558	3	10	7000	2000	4000	3000	8000	28294	28166	1	1	61001	1000	1000	0	2003	0	6	2000	0	0	2	2004	4	0	0	0	0	13924	9770	7115	3381	11	47	19202	3307	3807	14	52	56	27825	1000	14262	11926	12952	2000	4000	1000	28476	28066	28216	28203	28186
66004	28456	213	0	20	0	0	21	0	0	0	0	7	0	0	5107	28255	0	0	15781	7000	1000	4008	2000	1000	4000	2000	5000	10004	47536	6	23018	28145	28212	3	10	7000	2000	4000	3000	8000	28090	28129	1	1	61001	1000	1000	0	2002	3	0	2002	0	0	0	2002	0	2	4	2	0	13914	10097	7174	3276	12	50	19147	3252	3810	16	49	45	27839	1000	14650	11645	12853	2000	4000	1000	28364	28421	28432	28436	28323
66004	28159	213	0	24	0	0	22	0	0	0	0	4	0	0	5093	27937	0	1	15728	7004	1000	4012	2000	1000	4000	2000	5000	10002	47452	14	23048	28138	28388	3	10	7000	2000	4000	3000	8000	28189	28155	1	1	61001	1000	1000	0	2000	3	0	2002	0	0	0	2002	2	2	6	2	1	13799	9905	7222	3378	15	48	19032	3276	3814	21	49	49	27947	1000	14779	12429	12535	2000	4000	1000	28097	28282	28248	28519	28365
66004	28325	212	0	22	0	0	20	0	0	0	0	7	0	0	4832	28069	0	0	15929	7012	1000	4000	2000	1000	4000	2000	5000	10000	47516	11	23043	28198	28059	3	10	7000	2000	4000	3000	8000	28404	28141	1	1	61001	1000	1000	0	2000	0	0	2002	0	0	2	2002	0	0	6	0	1	13945	9856	7090	3306	13	51	19099	3353	3810	13	49	51	27877	1002	14323	12060	12513	2000	4000	1000	28414	28166	28493	28578	28425
66004	28382	212	0	19	0	0	18	0	0	0	0	5	0	0	5050	28114	0	1	15928	7012	1000	4012	2000	1000	4000	2000	5000	10000	47554	8	23010	28436	28132	3	10	7000	2000	4000	3000	8000	28147	28338	1	1	61001	1000	1000	0	2000	0	0	2000	0	0	0	2000	4	2	6	0	0	13541	10179	7145	3280	13	48	19086	3277	3819	18	52	52	27872	1000	14988	12046	12958	2000	4000	1000	28220	28253	28445	28218	28359
66004	28531	212	1	24	0	0	14	0	0	0	0	7	0	0	5028	28035	0	0	15972	7000	1000	4020	2000	1000	4000	2000	5000	10000	47444	8	23006	28283	28465	3	10	7000	2000	4000	3000	8000	28112	28118	1	1	61001	1000	1000	0	2000	0	0	2000	0	0	0	2002	6	2	2	0	0	13888	9827	7163	3379	9	49	19181	3247	3814	16	52	52	27843	1000	14416	11999	13175	2000	4000	1000	28452	28360	28409	28389	28145
66004	28260	212	1	18	0	0	18	0	0	0	0	4	0	0	4906	28021	2	0	15784	7004	1000	4008	2000	1000	4000	2000	5000	10000	47438	12	23058	28273	28202	3	10	7000	2000	4000	3000	8000	28290	28179	1	1	61001	1000	1000	0	2000	0	4	2008	0	0	2	2002	4	0	0	0	0	13906	10391	7136	3319	13	51	19088	3306	3821	13	55	51	27891	1000	14309	12168	12980	2000	4000	1000	28273	28321	28306	28180	28203
66004	28142	212	0	15	0	0	22	0	0	0	0	0	0	0	5130	28053	0	0	16095	7004	1000	4000	2000	1000	4000	2000	5000	10000	47436	10	23046	28152	28257	3	10	7000	2000	4000	3000	8000	28166	28210	1	1	61001	1000	1000	0	2000	0	4	2006	0	0	0	2002	0	2	0	0	0	13754	10075	7225	3228	9	49	19018	3415	3813	13	44	47	27864	1000	14912	11755	13167	2000	4000	1000	28369	28359	28260	28195	28375

Count: 8

Code:

  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480205	80070	620	0	1	0	1	0	0	1	0	0	0	35	0	0	2	80045	2	12	14	0	0	25	560100	80100	320000	160000	80100	320000	160000	480499	961025	8320004	80046	80065	80042	0	0	3	42	560100	200	160000	320264	200	240000	640000	80060	80056	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	0	160000	0	1	47	160030	6	1	0	33	0	0	5111	2	17	2	1	80208	0	80000	9	6	160000	320000	80100	80061	80061	80061	80228	80066
480204	80042	620	0	1	0	0	1	1	0	0	0	0	52	0	0	2	80045	2	12	12	0	0	25	560172	80100	320072	160000	80100	320000	160000	480499	960887	5440032	80041	80065	80065	0	0	25	39	560100	200	160000	320000	200	240000	640000	80060	80056	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	25	0	160162	0	0	21	160028	6	1	48	33	0	0	5109	2	17	2	2	80057	0	80000	9	9	160000	320000	80100	80061	80061	80060	80061	80049
480204	80042	621	0	1	0	0	1	1	0	0	0	0	53	0	0	1	80050	2	12	12	1	0	25	560172	80100	320244	160000	80100	320000	160000	480499	960360	10880152	80041	80060	80065	0	0	3	42	560100	200	160000	320000	200	240000	640600	80056	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	25	0	160000	0	0	46	160036	0	1	47	40	0	0	5109	1	17	2	1	80053	1	80000	10	12	160000	320000	80100	80043	80043	80043	80043	80043
480204	80042	620	0	0	0	0	0	0	0	0	26	14	0	0	0	2	80050	2	0	12	0	0	25	560172	80100	320000	160000	80100	320000	160000	480499	960330	8320004	80041	80065	80060	0	0	3	38	560100	200	160000	320000	200	240000	640000	80060	80056	1	1	80201	100	99	100	100	80000	80000	0	100	160011	0	25	0	160022	0	0	49	160036	6	1	0	0	0	0	5111	2	17	1	1	80062	0	80000	0	10	160000	320000	80100	80048	80061	80061	80061	80066
480204	80060	620	0	1	0	0	1	0	1	1	0	0	23	0	0	1	80045	2	0	0	0	0	25	560100	80100	320224	160000	80100	320000	160000	480499	960330	9600000	80041	80065	80048	0	0	3	45	560100	200	160000	320000	200	240000	640000	80062	80060	2	1	80201	100	99	100	100	80000	80000	0	100	160012	11	25	0	160000	1	0	22	160030	6	0	29	33	10	0	5111	2	17	1	2	80062	1	80000	10	10	160000	320000	80100	80061	80061	80061	80061	80049
480204	80065	621	0	1	0	0	0	0	0	0	0	0	11	0	0	1	80050	2	0	0	1	0	25	560184	80100	320056	160000	80100	320000	160000	480499	959996	4799112	80041	80042	80048	0	0	3	42	560100	200	160000	320000	200	240000	640000	80065	80060	1	1	80201	100	99	100	100	80000	80000	0	100	160000	11	25	0	160030	0	0	22	160000	6	1	30	43	11	0	5111	2	17	2	1	80053	1	80000	10	10	160000	320000	80100	80061	80043	80061	80061	80061
480204	80065	621	0	1	0	0	1	0	1	0	0	0	35	0	0	2	80180	2	12	12	0	0	25	560184	80100	320072	160000	80100	320000	160000	480499	960358	9600000	80041	80042	80042	0	0	3	42	560100	200	160000	320264	200	240000	640000	80065	80065	1	1	80201	100	99	100	100	80000	80000	0	100	160012	0	40	0	160000	0	0	30	160036	0	1	22	40	0	0	5111	1	17	1	2	80062	0	80000	6	10	160000	320000	80100	80061	80061	80229	80061	80048
480204	80060	620	0	0	1	0	0	0	0	0	0	0	168	0	0	1	80213	2	12	0	0	0	25	560172	80100	320076	160000	80166	320000	160000	480499	960331	4159992	80023	80042	80228	0	0	3	42	560569	200	160000	320000	200	240000	640000	80060	80065	1	1	80201	100	99	100	100	80000	80000	0	100	160010	11	40	0	160154	0	0	30	160030	6	0	30	0	11	0	5124	2	17	1	1	80062	1	80000	0	10	160000	320000	80100	80061	80061	80057	80061	80061
480204	80065	620	1	0	0	0	0	0	0	0	1	1	35	0	1	2	80045	2	12	12	0	352	202	561080	80228	320580	160520	80232	320000	160398	491769	963978	5971516	80041	80060	80060	0	0	3	42	560100	200	160000	320000	200	240000	640000	80065	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160000	11	25	0	160029	0	0	21	160000	6	0	21	33	11	3	5109	2	17	2	2	80054	1	80000	0	10	160000	320000	80100	80066	80061	80061	80061	80061
480204	80065	621	1	0	0	0	0	0	1	1	0	0	39	0	0	2	80027	0	15	12	0	0	25	560120	80100	320332	160000	80100	320000	160136	480499	960338	8320004	80041	80060	80060	0	0	3	47	560100	200	160000	320000	200	240000	640000	80048	80065	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	40	0	160012	0	0	32	160000	6	1	21	33	0	0	5109	2	17	1	2	80053	0	80000	6	10	160000	320000	80100	80230	80066	80061	80043	80043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480025	80069	620	1	1	0	1	0	0	0	0	43	0	2	80054	2	6	7	0	0	25	560074	80010	320064	160000	80010	320000	160000	480048	961108	10880752	0	80050	80069	80069	0	0	3	52	560010	20	160000	320000	20	240000	640000	80069	80069	1	1	80021	10	9	10	10	80000	80000	10	160013	0	43	0	160050	1	0	0	50	160039	6	1	50	43	10	1	5019	4	17	5	5	80066	0	80000	13	13	160000	320000	80010	80070	80070	80070	80070	80065
480024	80069	620	1	0	1	1	0	0	0	0	11	0	2	80054	2	7	6	0	0	25	560094	80010	320064	160000	80010	320000	160132	480048	961098	5760016	0	80050	80063	80069	4	0	3	52	560010	20	160000	320000	20	240000	640000	80069	80069	1	1	80021	10	9	10	10	80000	80000	10	160011	11	43	0	160051	0	0	2	50	160039	6	1	49	43	11	0	5019	3	16	3	3	80066	0	80000	14	13	160000	320000	80010	80070	80070	80070	80070	80070
480024	80071	621	1	1	1	0	0	0	0	0	56	0	2	80054	2	12	12	6	0	25	560094	80010	320096	160000	80010	320000	160000	480048	961143	10880752	0	80050	80069	80069	4	0	3	52	560010	20	160000	320000	20	240000	640000	80069	80070	1	1	80021	10	9	10	10	80000	80000	10	160011	11	43	0	160051	0	0	0	53	160039	6	1	50	43	11	0	5019	4	17	3	3	80066	0	80000	13	13	160000	320000	80010	80070	80070	80072	80070	80070
480024	80069	621	1	1	1	0	0	0	0	0	68	0	0	80054	2	6	6	5	0	25	560094	80010	320076	160000	80010	320000	160000	480048	961142	10880752	0	80050	80069	80069	3	0	3	29	560010	20	160000	320000	20	240000	640000	80063	80047	1	1	80021	10	9	10	10	80000	80000	10	160011	0	43	0	160050	0	0	1	52	160000	6	1	49	43	10	0	5019	3	17	4	3	80066	0	80000	13	13	160000	320000	80010	80070	80070	80064	80070	80070
480024	80069	620	1	1	0	0	0	0	0	0	67	0	0	80054	2	7	6	5	0	58	560082	80010	320076	160000	80010	320000	160000	480048	961101	10880752	0	80041	80060	80069	3	0	3	45	560010	20	160000	320000	20	240000	640000	80069	80069	1	1	80021	10	9	10	10	80000	80000	10	160011	11	35	0	160038	0	0	0	13	160039	6	1	49	43	10	0	5019	4	16	3	3	80066	0	80000	14	13	160000	320000	80010	80070	80070	80070	80070	80070
480024	80069	620	1	0	0	0	0	0	0	0	56	0	2	80054	2	12	6	5	0	25	560034	80010	320096	160000	80010	320000	160000	480048	961161	10880752	0	80050	80069	80063	3	0	3	52	560010	20	160000	320000	20	240000	640000	80069	80069	1	1	80021	10	9	10	10	80000	80000	10	160011	12	43	0	160050	0	0	0	49	160039	6	1	50	43	11	0	5019	3	16	3	3	80066	0	80000	17	13	160000	320000	80010	80070	80070	80070	80070	80070
480024	80070	620	0	1	0	0	0	0	0	0	56	0	3	80054	2	6	7	5	0	25	560074	80010	320076	160000	80010	320000	160000	480048	960754	10880752	0	80050	80069	80069	3	0	3	52	560010	20	160000	320000	20	240000	640000	80069	80060	1	1	80021	10	9	10	10	80000	80000	10	160010	0	43	0	160049	0	0	0	37	160039	6	1	30	43	10	0	5019	3	16	5	6	80066	0	80000	13	13	160000	320000	80010	80070	80067	80070	80070	80070
480024	80070	621	0	0	0	1	0	0	0	0	56	0	3	80054	2	6	12	5	0	25	560078	80010	320076	160000	80010	320000	160000	480048	961108	10880756	0	80050	80063	80417	3	0	3	253	560010	20	160000	320000	20	240000	640000	80069	80069	1	1	80021	10	9	10	10	80000	80000	10	160011	10	43	0	160050	0	1	0	49	160039	6	1	49	43	10	1	5019	3	16	4	4	80066	0	80000	13	14	160000	320000	80010	80070	80065	80070	80070	80064
480024	80069	621	1	0	1	0	1	1	0	0	56	0	2	80054	2	6	7	6	0	25	560074	80010	320076	160000	80010	320000	160000	480049	961112	10880888	0	80050	80069	80069	4	0	3	52	560010	20	160000	320000	20	240000	640000	80069	80069	1	1	80021	10	9	10	10	80000	80000	10	160012	0	43	0	160049	0	0	0	49	160039	6	1	50	43	10	0	5019	3	16	3	3	80066	0	80000	13	13	160000	320000	80010	80070	80070	80070	80073	80070
480024	80069	620	1	0	0	0	0	0	0	0	56	0	2	80054	2	6	7	5	0	25	560078	80010	320020	160000	80010	320000	160000	480048	960690	10880752	0	80050	80069	80069	3	0	3	52	560010	20	160000	320000	20	240000	640000	80063	80069	1	1	80021	10	9	10	10	80000	80000	10	160011	10	33	0	160049	0	1	0	1069	160039	6	1	29	43	0	0	5048	5	25	4	3	80354	0	80132	13	13	160000	320000	80010	80417	80413	80232	80234	80417

LD4R (post-index, 1D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations