Firestorm: LD4R (post-index, 2D) measurements

Code:

  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.008

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
66005	29652	237	3	0	2	0	0	1	0	0	0	0	0	19	0	0	4812	28964	0	2	2	17070	7012	1000	4012	2000	1000	4000	2000	5000	10000	47570	9	0	0	22976	29227	29511	3	10	7000	2000	4000	3000	8000	29463	29462	1	1	61001	1000	1000	0	2003	3	8	2006	2	1	4	2002	6	4	8	2	1	13147	9294	6912	3134	1	60	20348	3194	3809	36	60	66	28705	1000	16587	13366	14580	2000	4000	1000	29429	29602	29551	29581	29508
66004	29633	239	0	1	1	1	1	2	1	0	0	0	0	19	0	0	4712	29025	0	0	2	17141	7018	1000	4018	2000	1000	4000	2000	5000	10004	47618	10	1	0	23007	29311	29587	3	10	7000	2000	4000	3000	8000	29389	29247	1	1	61001	1000	1000	0	2003	3	4	2003	0	0	4	2000	6	2	8	2	1	13227	9338	6956	3136	1	65	20336	3276	3805	27	61	57	28874	1000	16153	13006	14526	2000	4000	1000	29566	29480	29606	29634	29481
66004	29447	236	0	1	0	1	1	1	1	0	0	0	0	8	0	0	4620	28901	0	0	2	16989	7016	1000	4016	2000	1000	4000	2000	5000	10004	47622	14	0	0	23017	29150	29367	3	10	7000	2000	4000	3000	8000	29306	29390	1	1	61001	1000	1000	0	2003	3	6	2006	0	1	4	2002	4	4	6	2	2	13080	9253	6958	3130	0	62	20293	3201	3802	25	54	53	28593	1000	16285	13261	14406	2000	4000	1000	29330	29336	29403	29454	29447
66004	29420	238	0	1	2	1	1	1	0	0	0	0	0	4	0	0	4775	29003	0	0	0	17258	7008	1000	4012	2000	1000	4000	2000	5000	10000	47522	9	1	0	22960	29236	29620	3	10	7000	2000	4000	3000	8000	29439	29404	2	1	61001	1000	1000	0	2000	3	2	2005	1	0	5	2000	2	2	2	2	1	13406	9327	6956	3069	0	61	20252	3278	3808	33	61	64	28783	1000	16512	13136	14530	2000	4000	1000	29493	29670	29515	29500	29571
66004	29518	238	0	1	1	1	1	2	1	0	0	0	1	6	0	0	4741	28986	0	0	0	17274	7008	1000	4008	2000	1000	4000	2000	5000	10000	47498	3	0	0	23059	29706	29614	6	47	7007	2000	4000	3000	8000	29296	29348	1	1	61001	1000	1000	0	2002	5	6	2000	0	0	249	2000	4	2	4	2	1	13328	9465	6916	3157	1	61	20404	3330	3804	32	61	56	28724	1001	16444	13333	14403	2000	4000	1000	29476	29662	29528	29516	29416
66004	29491	228	0	1	1	1	0	0	0	0	0	0	0	6	0	0	4793	28858	0	1	0	17036	7012	1000	4012	2000	1000	4000	2000	5000	10000	47580	12	0	5	23013	29259	29503	3	10	7000	2000	4000	3000	8000	29401	29388	1	1	61001	1000	1000	0	2004	3	2	2002	0	1	2	2002	2	4	2	2	1	13296	9327	6910	3117	0	67	20236	3320	3813	30	52	65	28600	1000	16197	13269	14668	2000	4000	1000	29478	29519	29453	29500	29511
66004	29547	229	0	1	2	1	1	2	1	0	0	1	0	4	0	0	4709	28988	0	0	0	17056	7016	1000	4016	2000	1000	4000	2000	5000	10000	47606	11	0	0	22968	29365	29430	3	10	7000	2000	4000	3000	8000	29438	29414	1	1	61001	1000	1000	0	2003	5	4	2003	0	1	2	2000	4	2	4	2	1	13230	9319	6822	3155	0	63	20508	3233	3802	28	64	60	28754	1000	16232	13236	14516	2000	4000	1000	29525	29666	29474	29537	29693
66004	29497	229	0	1	2	1	1	1	1	0	0	0	1	4	0	0	4657	28977	0	0	0	17205	7012	1000	4008	2000	1000	4000	2000	5005	10000	47582	8	0	0	23096	29305	29609	3	10	7000	2000	4000	3000	8000	29336	29363	1	1	61001	1000	1000	0	2004	3	2	2003	0	1	2	2000	2	2	2	2	1	13200	9359	6958	3097	1	59	20378	3237	3808	28	60	57	28731	1000	16471	13245	14354	2000	4000	1000	29444	29473	29519	29470	29559
66004	29442	229	0	1	2	1	1	2	1	0	0	0	1	2	0	0	4712	28930	0	0	0	17121	7008	1000	4008	2000	1000	4000	2000	5000	10000	47624	15	0	9	23005	29348	29604	3	10	7000	2000	4000	3000	8000	29438	29402	1	1	61001	1000	1000	0	2000	0	4	2000	0	0	0	2000	4	0	4	0	0	13191	9455	7052	3146	2	61	20328	3271	3817	28	68	66	28763	1000	16349	13202	14472	2000	4000	1000	29597	29521	29645	29473	29516
66004	29556	230	0	0	3	0	0	6	0	0	0	0	0	0	0	0	4601	29021	0	0	0	17332	7008	1000	4008	2000	1000	4000	2000	5000	10010	47518	0	0	0	23056	29315	29573	7	10	7000	2000	4004	3000	8000	29449	29384	1	1	61001	1000	1000	0	2000	0	0	2000	0	0	0	2000	2	0	4	0	0	13148	9277	6910	3172	5	52	20480	3240	3817	33	64	57	28694	1000	16323	13472	14239	2000	4000	1000	29524	29561	29533	29468	29540

Count: 8

Code:

  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480205	80069	620	0	0	0	1	1	0	0	43	0	1	0	0	80048	2	12	12	0	0	25	560184	80100	320084	160000	80100	320000	160000	480499	960649	9600000	0	0	80053	80063	80063	0	0	3	42	560100	200	160132	320000	200	240000	640000	80063	80060	1	1	80201	100	99	100	100	80000	80000	1	100	160000	0	33	0	160037	0	0	37	160037	6	1	37	40	0	0	5109	1	17	1	1	80060	1	80061	14	10	160000	320000	80100	80067	80064	80064	80064	80064
480204	80063	620	0	0	0	0	0	0	0	43	0	0	0	2	80048	0	0	12	0	0	25	560184	80100	320084	160000	80100	320000	160000	480499	960650	9600000	0	0	80041	80063	80063	0	0	3	27	560555	200	160000	320000	200	240000	640000	80063	80060	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	41	0	160036	1	0	30	160037	6	1	30	41	0	0	5109	1	17	1	1	80060	0	80000	14	14	160000	320000	80100	80064	80064	80064	80064	80043
480204	80063	621	0	1	0	0	0	0	0	43	0	0	0	2	80048	2	12	12	0	0	25	560558	80100	320084	160000	80100	320000	160000	480499	960649	9600000	0	0	80177	80060	80063	0	0	3	45	560100	200	160000	320000	200	240000	640536	80063	80060	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	41	0	160037	0	0	36	160039	6	1	30	33	0	0	5109	1	17	1	1	80060	0	80000	14	14	160000	320000	80100	80061	80064	80064	80061	80064
480204	80063	620	0	0	0	0	0	0	0	0	0	0	0	2	80048	2	12	12	0	0	25	560184	80100	320084	160000	80100	320000	160000	480499	963700	9600000	0	0	80041	80063	80063	0	0	3	45	560100	200	160000	320000	200	240000	640000	80063	80063	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	41	0	160000	0	0	40	160036	6	1	29	33	0	0	5136	1	17	1	1	80060	0	80134	0	14	160000	320000	80100	80064	80064	80064	80064	80061
480204	80042	620	0	0	0	0	0	0	13	76	0	0	0	2	80048	2	12	12	0	0	25	560184	80100	320084	160000	80100	320000	160000	480499	960652	9600000	0	0	80041	80063	80063	0	0	3	27	560100	200	160000	320000	200	240000	640000	80063	80060	1	1	80201	100	99	100	100	80000	80000	1	100	160000	0	41	0	160037	2	0	30	160037	6	1	30	0	0	0	5109	1	17	1	1	80060	0	80000	14	14	160000	320000	80100	80064	80061	80064	80064	80064
480204	80042	620	0	0	0	0	0	0	0	36	0	0	0	2	80048	2	12	12	0	0	25	560184	80100	320084	160000	80100	320000	160000	480499	960684	9600000	0	0	80041	80063	80200	0	0	3	45	560100	200	160000	320000	200	240000	640000	80063	80060	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	0	160030	0	0	37	160037	6	1	30	41	0	0	5109	1	17	1	1	80057	0	80000	15	10	160000	320000	80100	80064	80064	80064	80064	80064
480204	80065	620	0	0	0	0	0	0	0	43	0	0	0	0	80048	0	12	12	0	0	25	560184	80100	320084	160000	80100	320000	160000	480499	960652	10560008	0	0	80041	80063	80060	0	0	3	45	560100	200	160000	320000	200	240000	640000	80068	80063	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	40	0	160037	0	0	29	160037	6	1	29	41	0	0	5109	1	17	1	1	80060	0	80000	16	14	160000	320000	80100	80061	80067	80064	80064	80064
480204	80063	620	0	1	0	0	1	0	0	43	0	0	0	2	80048	2	12	12	0	0	25	560100	80100	320084	160000	80100	320000	160000	480499	959996	4159992	0	0	80032	80063	80063	0	0	3	42	560100	200	160000	320000	200	240000	640000	80063	80063	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	0	160037	1	0	0	160038	6	1	34	33	0	0	5109	1	17	1	1	80057	1	80000	0	11	160000	320000	80100	80061	80064	80043	80064	80064
480204	80063	621	0	0	0	0	0	0	0	43	0	0	0	2	80048	2	12	12	0	0	25	560184	80100	320084	160000	80100	320000	160000	480499	960650	9600008	0	0	80044	80063	80045	0	0	3	45	560100	200	160000	320000	200	240000	640000	80065	80063	1	1	80201	100	99	100	100	80000	80000	4	100	160000	0	0	0	160037	0	0	37	160037	0	1	0	41	0	0	5109	1	17	1	1	80060	0	80000	14	14	160000	320000	80100	80064	80066	80064	80046	80064
480204	80063	620	0	1	0	0	0	0	0	43	0	0	0	2	80048	0	12	12	0	0	25	560184	80100	320084	160000	80100	320000	160000	480499	960649	9600000	0	0	80041	80063	80060	0	0	3	45	560100	200	160000	320000	200	240000	640000	80063	80060	1	1	80201	100	99	100	100	80000	80000	1	100	160000	0	33	0	160037	0	0	37	160167	0	1	0	35	2	0	5137	2	17	2	2	80196	1	80130	14	10	160000	320000	80100	80413	80228	80411	80231	80233

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480025	80069	621	0	0	0	0	0	1	0	0	0	43	0	0	0	1	80045	3	12	12	0	0	25	560086	80010	320096	160000	80010	320000	160000	480048	960680	9600000	0	80044	80069	80063	4	0	3	52	560465	20	160000	320000	20	240000	640000	80060	80060	1	1	80021	10	9	0	10	10	80000	80000	0	10	160000	0	33	0	160012	0	0	0	16	160039	6	1	30	41	0	0	5063	5	16	5	5	80062	0	80000	14	10	160000	320000	80010	80064	80064	80064	80043	80064
480024	80045	620	1	0	0	0	0	0	0	0	0	55	0	0	0	3	80211	2	12	0	0	0	25	560010	80010	320076	160000	80010	320252	160000	480048	961108	10880752	0	80050	80069	80069	0	0	3	45	560010	20	160000	320000	20	240000	640000	80069	80069	1	1	80021	10	9	0	10	10	80000	80000	0	10	160010	11	43	0	160050	1	0	0	55	160037	6	1	10	41	0	0	5021	5	16	5	5	80066	0	80068	13	10	160000	320000	80010	80064	80043	80070	80064	80061
480024	80069	620	0	0	0	0	0	0	0	0	0	43	0	1	0	3	80052	2	12	12	0	0	25	560086	80010	320084	160000	80010	320000	160000	480048	960652	10560008	0	80046	80069	80063	3	0	3	45	560010	20	160000	320000	20	240000	640000	80063	80060	1	1	80021	10	9	0	10	10	80000	80000	0	10	160000	0	33	0	160051	1	0	1	67	160039	0	1	30	41	0	0	5021	3	17	5	5	80060	0	80000	14	10	160000	320000	80010	80064	80064	80048	80064	80064
480024	80064	620	0	0	0	0	0	0	0	0	0	12	0	0	0	1	80048	2	12	12	0	0	25	560094	80010	320096	160000	80010	320000	160000	480049	960650	9600000	0	80044	80063	80063	0	0	3	42	560010	20	160000	320000	20	240000	640544	80063	80063	1	1	80021	10	9	0	10	10	80000	80000	0	10	160011	10	33	0	160037	0	1	0	20	160030	6	0	50	33	0	0	5021	5	16	4	5	80066	0	80000	13	10	160000	320000	80010	80069	80043	80048	80064	80061
480024	80069	621	0	0	0	0	0	0	0	0	0	56	0	0	0	4	80054	2	6	12	0	0	25	560074	80010	320064	160000	80010	320000	160000	480048	961039	10880752	0	80050	80071	80042	3	0	3	45	560010	20	160000	320000	20	240000	640000	80060	80060	1	1	80021	10	9	0	10	10	80000	80000	0	10	160011	11	43	0	160012	1	0	1	25	160039	6	1	0	41	0	0	5021	5	17	5	5	80042	0	80000	14	14	160000	320000	80010	80043	80064	80064	80067	80064
480024	80060	621	0	0	0	0	0	1	0	0	0	35	0	0	0	3	80048	2	12	12	1	0	25	560094	80010	320076	160000	80010	320000	160000	480048	959996	9600000	0	80044	80069	80064	0	0	3	45	560010	20	160000	320000	20	240000	640000	80063	80062	1	1	80021	10	9	0	10	10	80000	80000	0	10	160011	11	0	0	160050	0	0	1	56	160039	6	1	49	43	10	0	5021	5	16	5	5	80045	0	80000	14	10	160000	320000	80010	80070	80070	80070	80046	80070
480024	80069	620	0	0	0	0	0	0	0	0	0	44	0	0	0	1	80048	2	12	12	0	0	25	560034	80010	320072	160000	80010	320000	160000	480049	960652	9600000	0	80044	80069	80063	3	0	3	45	560010	20	160000	320000	20	240000	640000	80060	80063	1	1	80021	10	9	0	10	10	80000	80000	1	10	160000	0	33	0	160052	1	0	0	71	160039	6	1	30	41	0	0	5021	5	17	5	3	80062	0	80000	14	0	160000	320000	80010	80064	80064	80061	80064	80064
480024	80060	621	0	0	0	0	0	0	0	0	0	43	0	0	1	1	80048	2	12	12	0	0	25	560094	80010	320096	160000	80010	320000	160000	480049	960650	9600000	0	80044	80063	80063	0	0	3	24	560010	20	160000	320000	20	240000	640000	80063	80060	1	1	80021	10	9	0	10	10	80000	80000	0	10	160012	11	41	0	160037	0	0	1	83	160000	6	0	50	41	0	1	5021	12	259	5	5	80066	0	80000	13	10	160000	320000	80010	80064	80061	80070	80064	80061
480024	80069	620	0	0	0	0	0	1	1	0	0	65	0	0	1	1	80045	0	12	12	0	0	25	560106	80076	320080	160000	80010	320000	160000	480048	961147	10880752	0	80044	80072	80069	3	0	3	45	560010	20	160000	320000	20	240000	640000	80233	80069	1	1	80021	10	9	0	10	10	80000	80000	0	10	160013	11	0	0	160052	0	0	0	58	160039	0	1	30	43	0	1	5021	5	16	3	5	80066	0	80000	13	14	160000	320000	80010	80064	80064	80064	80065	80064
480024	80063	621	0	0	0	0	0	0	0	0	0	43	0	0	0	3	80048	2	12	12	0	0	25	560094	80010	320064	160000	80010	320000	160000	480049	960330	4620936	0	80044	80045	80042	0	61	3	45	560010	20	160000	320000	20	240000	640000	80063	80063	1	1	80021	10	9	0	10	10	80000	80000	0	10	160011	13	0	0	160037	0	0	1	17	160000	6	1	49	33	0	0	5021	3	16	3	5	80066	1	80000	13	13	160000	320000	80010	80064	80064	80070	80070	80061

LD4R (post-index, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations