Firestorm: LD4R (post-index, 2S) measurements

Code:

  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 6.008

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
65005	29477	228	2	0	2	0	1	4	0	1	1	0	0	132	0	0	0	0	4656	28754	0	1	17051	6012	1000	4012	1000	1000	4000	1000	5000	5000	47558	15	22909	0	29083	29274	3	10	6000	1000	4000	2000	4000	29219	29134	1	1	61001	1000	1000	1001	2	3	1001	0	0	1	2	1001	0	1	0	0	0	0	12986	9269	6941	3164	0	59	20206	3165	3807	17	53	52	28505	1000	16299	13270	14277	1000	4000	1000	29307	29319	29348	29323	29224
65004	29323	226	0	0	1	0	0	0	0	0	0	0	0	55	0	1	0	0	4620	28675	0	1	17024	6000	1000	4000	1000	1000	4000	1000	5000	5000	47596	9	22832	0	29127	29355	3	10	6000	1000	4000	2000	4000	29220	29204	1	1	61001	1000	1000	1000	3	3	1002	0	0	0	1	1000	0	1	0	0	0	0	13083	9262	6951	3142	1	58	20176	3196	3797	16	56	57	28545	1000	15866	13342	14136	1000	4000	1000	29368	29223	29371	29304	29304
65004	29289	227	0	1	2	0	0	2	1	0	0	0	0	45	0	1	0	0	4649	28819	0	1	17063	6004	1000	4004	1000	1000	4000	1000	5000	5000	47621	13	22882	0	29098	29346	3	10	6000	1000	4000	2000	4000	29192	29202	1	1	61001	1000	1000	1002	0	0	1003	0	0	0	2	1000	3	1	3	0	0	0	12949	9189	6872	3137	0	56	20236	3230	3808	15	61	60	28534	1000	16177	13352	14283	1000	4000	1000	29224	29261	29241	29203	29204
65004	29307	227	0	0	1	0	0	2	0	0	0	0	0	36	0	0	0	0	4625	28749	0	0	17006	6004	1000	4000	1000	1000	4000	1000	5000	5000	47466	12	22972	0	29153	29371	3	10	6000	1001	4000	2000	4000	29100	29200	1	1	61001	1000	1000	1001	2	0	1003	0	1	1	1	1000	0	2	3	1	0	0	13172	9454	6928	3114	3	56	20252	3159	3806	18	57	56	28411	1000	16259	13206	14197	1000	4000	1000	29224	29288	29365	29295	29321
65004	29318	227	0	0	0	0	0	1	0	0	0	0	0	46	0	1	0	0	4621	28907	1	0	17082	6012	1000	4012	1000	1000	4000	1000	5000	5000	47428	0	22903	0	29103	29187	3	10	6000	1000	4000	2000	4000	29203	29225	1	1	61001	1000	1000	1001	3	3	1002	0	0	2	1	1001	3	1	3	0	0	0	13094	9085	6980	3105	0	59	20286	3157	3805	15	56	61	28465	1000	16241	13231	14555	1000	4000	1000	29264	29262	29264	29279	29201
65004	29419	227	0	0	2	0	0	2	0	1	0	0	0	51	0	1	0	0	4713	28782	0	1	16918	6016	1000	4000	1000	1000	4000	1000	5000	5000	47576	9	22872	0	29138	29352	3	10	6000	1000	4000	2000	4000	29227	29174	1	1	61001	1000	1000	1000	2	3	1001	0	2	2	4	1000	0	0	0	0	0	0	13249	9113	6903	3087	0	56	20249	3318	3807	16	63	56	28429	1000	16263	13156	14357	1000	4000	1000	29384	29293	29252	29366	29226
65004	29310	226	0	0	3	0	0	0	0	0	0	0	0	54	0	1	0	0	4624	28763	0	0	17077	6019	1000	4012	1000	1000	4000	1000	5000	5000	47608	10	22872	0	29120	29323	3	10	6000	1000	4000	2000	4000	29210	29103	1	1	61001	1000	1000	1001	2	3	1002	0	0	1	1	1000	2	1	3	0	1	0	13163	9157	6880	3150	1	64	20260	3105	3812	15	57	63	28578	1000	16395	13138	14176	1000	4000	1000	29410	29348	29349	29290	29335
65004	29268	228	0	0	2	0	0	2	0	0	0	0	0	51	0	1	0	0	4541	28795	0	0	17021	6008	1000	4008	1000	1000	4000	1000	5000	5000	47554	4	22915	0	29249	29371	3	10	6000	1000	4000	2000	4000	29252	29321	1	1	61001	1000	1000	1002	1	2	1002	0	0	0	1	1000	0	1	2	0	0	0	13059	9287	6891	3114	1	58	20258	3122	3813	18	52	57	28544	1000	16274	13206	14340	1000	4000	1000	29322	29389	29338	29307	29421
65004	29206	228	0	1	2	1	0	2	0	0	0	0	0	60	0	0	0	0	4688	28950	0	0	17005	6008	1000	4008	1000	1000	4000	1000	5000	5000	47554	1	22891	0	29115	29357	3	10	6000	1000	4000	2000	4000	29227	29267	1	1	61001	1000	1000	1002	2	2	1003	0	0	2	1	1000	2	0	2	0	0	0	13166	9146	6821	3127	3	64	20326	3179	3807	16	57	55	28545	1000	16405	13419	14353	1000	4000	1000	29280	29334	29373	29350	29440
65004	29369	227	0	0	2	0	0	2	0	0	0	0	0	50	0	0	0	0	4690	28906	0	0	16998	6008	1000	4008	1000	1000	4000	1000	5000	5000	47398	9	22907	0	29135	29316	3	10	6000	1000	4000	2000	4000	29342	29226	1	1	61001	1000	1000	1000	2	0	1003	0	0	0	1	1000	3	0	2	0	0	0	13147	9221	6872	3181	2	59	20210	3182	3814	15	57	53	28577	1000	16376	13007	14362	1000	4000	1000	29274	29347	29421	29289	29468

Count: 8

Code:

  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	80071	621	1	0	0	0	0	0	0	0	0	18	0	1	0	0	80042	1	6	6	0	25	480156	80100	320000	80000	80100	320000	80000	480499	480010	7680020	0	80023	80059	80042	0	0	3	36	480100	200	80000	320000	200	160000	320000	80054	80054	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	13	80010	0	0	0	80010	5	0	13	17	0	0	0	5109	1	17	1	1	80054	0	80000	6	6	80000	320000	80100	80058	80058	80058	80043	80058
400204	80057	621	0	0	0	0	0	0	1	0	0	18	0	0	0	0	80042	0	6	0	0	25	480156	80100	320048	80000	80100	320000	80000	480499	480005	7680020	0	80038	80057	80042	0	0	3	27	480100	200	80000	320000	200	160000	320000	80054	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	17	80013	1	0	16	80012	5	0	0	13	0	0	0	5109	1	17	1	1	80052	1	80000	9	6	80000	320000	80100	80058	80055	80058	80058	80058
400204	80057	620	0	0	0	0	0	0	0	0	0	18	0	0	0	0	80039	1	6	6	0	25	480156	80100	320056	80000	80100	320000	80000	480499	479998	7680020	0	80038	80057	80042	0	0	3	39	480100	200	80000	320000	200	160000	320000	80057	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	13	80009	0	0	10	80009	5	1	12	17	0	0	0	5109	1	17	1	1	80054	0	80000	9	6	80000	320000	80100	80058	80058	80058	80058	80058
400204	80054	620	0	0	0	0	0	0	1	0	0	55	0	0	0	0	80042	1	6	6	0	25	480148	80100	320056	80000	80100	320000	80000	480499	480006	7680020	0	80038	80054	80057	0	0	3	39	480100	200	80000	320000	200	160000	320000	80057	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	13	80013	1	0	9	80010	0	0	12	17	0	0	0	5109	1	17	1	1	80054	1	80000	9	6	80000	320000	80100	80058	80055	80058	80058	80058
400204	80057	621	0	0	0	0	0	0	0	0	0	22	0	0	0	0	80042	1	6	6	0	25	480100	80100	320056	80000	80100	320000	80000	480499	480013	7680020	0	80038	80057	80057	0	0	3	39	480100	200	80000	320000	200	160000	320000	80057	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	13	80012	0	0	10	80009	0	0	12	14	0	0	0	5109	1	17	1	1	80054	1	80000	9	0	80000	320000	80100	80058	80058	80058	80058	80058
400204	80057	620	0	0	0	0	0	0	0	0	0	31	0	0	0	0	80042	1	6	6	0	25	480156	80100	320056	80000	80100	320000	80000	480499	480013	7680020	1	80038	80042	80042	0	0	3	24	480100	200	80000	320000	200	160000	320000	80057	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	15	80013	0	0	12	80010	6	1	9	0	0	0	0	5109	1	17	1	1	80039	1	80000	9	9	80000	320000	80100	80043	80055	80058	80058	80058
400205	80054	620	0	0	0	0	0	0	0	0	0	22	0	0	0	0	80042	1	6	6	0	25	480100	80100	320056	80000	80100	320000	80000	480499	480005	7680020	0	80023	80054	80057	0	0	3	39	480100	200	80000	320000	200	160000	320000	80057	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80012	0	0	10	80010	5	1	10	17	0	0	0	5109	1	17	1	1	80054	1	80000	0	6	80000	320000	80100	80058	80055	80055	80058	80055
400204	80057	621	0	0	0	0	0	1	0	0	0	18	0	0	0	0	80042	1	6	6	0	25	480100	80100	320056	80000	80100	320000	80000	480499	480005	7680020	1	80038	80057	80057	0	0	3	39	480100	200	80000	320000	200	160000	320000	80057	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	13	80013	1	0	12	80013	6	1	10	17	0	0	0	5109	1	17	1	1	80051	1	80000	9	6	80000	320000	80100	80058	80058	80058	80058	80058
400204	80057	620	0	0	0	0	0	0	0	0	0	15	0	0	0	0	80042	1	6	6	0	25	480156	80100	320056	80000	80100	320000	80000	480499	480014	7680020	0	80038	80057	80057	0	0	3	39	480100	200	80000	320000	200	160000	320000	80042	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	16	80010	0	0	13	80012	6	1	10	18	0	0	0	5109	1	17	1	1	80054	0	80000	9	9	80000	320000	80100	80058	80058	80058	80058	80058
400204	80057	621	0	0	0	0	0	0	0	0	0	18	0	0	1	0	80042	1	6	6	0	25	480156	80100	320000	80000	80100	320000	80000	480499	480023	10240020	0	80043	80062	80062	0	0	3	44	480100	200	80000	320000	200	160000	320000	80062	80062	1	1	80201	100	99	100	100	80000	80000	0	100	80084	7	23	80025	0	0	23	80019	6	0	23	0	6	1	0	5109	1	17	1	1	80059	1	80000	0	9	80000	320000	80100	80049	80049	80049	80063	80049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80062	620	1	0	0	1	0	0	0	0	0	0	0	0	0	80047	1	6	6	0	25	480058	80010	320056	80000	80010	320000	80000	480049	481658	10240024	0	80043	0	80062	80062	0	0	3	44	480010	20	80000	320000	20	160000	320000	80062	80062	1	1	80021	10	9	10	10	80000	80000	1	10	80005	7	23	80024	1	1	24	80018	0	1	23	0	0	0	5019	4	17	4	5	80059	1	80000	9	6	80000	320000	80010	80063	80058	80063	80063	80063
400024	80048	620	0	0	0	0	0	0	0	0	0	30	0	0	0	80047	1	6	6	0	25	480058	80010	320048	80000	80010	320000	80000	480049	480029	10240020	0	80043	0	80062	80062	0	0	3	44	480544	20	80000	320000	20	160000	320000	80062	80054	1	1	80021	10	9	10	10	80000	80000	1	10	80007	6	23	80025	0	1	907	80018	6	1	25	23	5	0	5019	4	17	5	4	80059	0	80000	9	11	80000	320000	80010	80048	80058	80048	80048	80063
400024	80047	621	0	0	1	1	2	0	0	0	0	41	0	0	0	80047	1	6	6	0	25	480066	80010	320056	80000	80010	320000	80000	480049	480029	5760016	0	80043	0	80062	80054	0	0	3	46	480010	20	80000	320000	20	160000	320000	80062	80062	1	1	80021	10	9	10	10	80000	80000	1	10	80007	6	23	80013	0	2	27	80018	6	1	25	22	5	0	5019	4	17	3	4	80045	0	80000	9	9	80000	320000	80010	80063	80063	80063	80058	80063
400024	80062	621	1	0	1	0	1	0	0	0	0	31	0	0	0	80042	1	6	6	0	25	480058	80010	320056	80000	80010	320000	80000	480049	480023	7680020	0	80023	0	80062	80062	0	0	3	44	480010	20	80000	320000	20	160000	320000	80062	80062	1	1	80021	10	9	10	10	80000	80000	1	10	80006	5	0	80024	0	0	25	80018	6	1	23	22	6	0	5019	5	17	4	5	80059	0	80000	9	9	80000	320000	80010	80063	80063	80063	80064	80063
400024	80062	620	1	0	0	0	0	0	0	0	0	41	0	0	0	80137	1	0	6	0	25	480066	80010	320048	80000	80010	320000	80000	480049	480005	10240020	0	80043	0	80048	80047	0	0	3	39	480010	20	80000	320000	20	160000	320000	80057	80062	1	1	80021	10	9	10	10	80000	80000	1	10	80006	6	23	80026	0	1	23	80018	6	0	23	23	6	1	5019	6	17	3	3	80558	1	80000	9	0	80000	320000	80010	80197	80350	80349	80197	80196
400024	80062	623	1	0	0	2	0	0	0	19	3	295	88	0	0	80335	1	6	6	0	64	480034	80089	320304	80000	80160	320000	80000	480497	480033	5520664	0	80038	0	80195	80196	20	21	3	44	480010	20	80079	320300	20	160470	320324	80196	80347	2	1	80021	10	9	10	10	80000	80000	1	10	80198	9	23	80159	0	0	908	80094	6	1	24	24	6	0	5034	3	17	4	5	80059	1	80077	9	0	80000	320000	80010	80197	80049	80048	80349	80196
400024	80194	622	1	0	0	0	0	0	0	1	1	162	0	0	0	80047	1	6	6	0	25	480066	80010	320056	80000	80010	320000	80000	480049	480023	10240020	0	80043	0	80062	80057	0	0	3	44	480010	20	80000	320000	20	160000	320000	80057	80062	1	1	80021	10	9	10	10	80000	80000	1	10	80006	0	23	80026	2	0	27	80012	6	1	25	23	5	0	5019	4	17	4	4	80059	0	80000	9	9	80000	320000	80010	80058	80063	80049	80063	80063
400024	80062	621	1	0	1	1	0	0	0	0	0	30	0	0	0	80047	1	6	6	0	25	480034	80010	320048	80000	80010	320000	80000	480049	480034	10240020	0	80044	0	80057	80209	0	0	3	44	480010	20	80000	320000	20	160000	320000	80062	80062	1	1	80021	10	9	10	10	80000	80000	1	10	80005	5	0	80024	0	0	28	80018	6	1	25	17	0	1	5019	4	17	3	3	80059	1	80000	9	6	80000	320000	80010	80063	80063	80058	80063	80058
400024	80062	621	1	0	0	1	1	0	0	0	0	30	0	0	0	80047	1	6	6	0	25	480066	80010	320024	80000	80010	320000	80000	480049	480011	5440024	0	80043	0	80062	80062	0	0	3	44	480010	20	80000	320000	20	160000	320000	80062	80062	1	1	80021	10	9	10	10	80000	80000	1	10	80006	5	23	80025	0	0	24	80019	6	1	24	23	6	1	5019	4	17	3	4	80044	1	80000	9	9	80000	320000	80010	80063	80048	80048	80063	80058
400024	80062	620	1	0	0	1	1	0	0	0	0	29	0	0	0	80047	0	6	6	0	25	480058	80010	320048	80000	80010	320000	80000	480049	480023	10880016	0	80043	0	80062	80057	0	0	3	44	480010	20	80000	320000	20	160000	320000	80062	80062	1	1	80021	10	9	10	10	80000	80000	1	10	80007	6	23	80013	0	1	24	80018	6	1	24	23	6	0	5019	3	17	3	5	80045	1	80000	9	9	80000	320000	80010	80063	80063	80063	80063	80063

LD4R (post-index, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations