Firestorm: LD4R (post-index, 4H) measurements

Code:

  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 6.008

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
65005	29382	228	0	29	1	23	1	1	1	0	0	5	0	0	0	4632	28686	0	0	1	17057	6012	1000	4019	1000	1000	4000	1000	5000	5000	47653	24	22856	29110	29329	3	10	6000	1000	4000	2000	4000	29218	29316	1	1	61001	1000	1000	0	1000	0	3	1003	0	0	0	2	1000	0	1	4	0	0	0	12841	9307	6844	3037	11	62	20287	3208	3806	14	74	69	28457	1000	16214	13155	14480	1000	4000	1000	29408	29341	29400	29353	29369
65004	29365	229	0	28	0	20	0	0	0	0	1	0	0	0	0	4566	28848	0	1	0	17087	6016	1000	4000	1000	1000	4000	1000	5000	5000	47560	15	22937	29224	29374	3	10	6000	1000	4000	2000	4000	29168	29184	1	1	61001	1000	1000	0	1000	0	0	1001	0	0	0	2	1001	2	2	0	0	0	0	13097	9241	6873	3138	6	70	20355	3266	3808	23	71	73	28532	1000	16124	13308	14427	1000	4000	1000	29341	29538	29417	29433	29303
65004	29375	228	0	26	0	17	0	0	0	0	0	0	0	0	0	4600	28831	0	0	0	17088	6012	1000	4012	1000	1000	4000	1000	5000	5000	47611	7	22919	29059	29502	3	10	6000	1000	4000	2000	4000	29233	29320	1	1	61001	1000	1000	0	1000	0	3	1000	0	1	0	3	1000	0	1	3	0	0	0	13142	9397	6921	3076	14	75	20260	3136	3812	19	75	75	28485	1000	16334	13017	14313	1000	4000	1000	29398	29425	29428	29465	29336
65004	29357	229	0	29	0	17	0	0	0	0	0	0	0	0	0	4666	28925	0	1	1	17026	6012	1000	4012	1000	1000	4000	1000	5000	5000	47613	9	22939	29248	29442	3	10	6000	1000	4000	2000	4000	29262	29188	1	1	61001	1000	1000	0	1000	0	3	1001	0	0	0	0	1002	0	0	3	0	0	0	13014	9346	6832	3143	12	68	20392	3190	3807	18	66	67	28567	1000	16470	13247	14317	1000	4000	1000	29254	29409	29515	29433	29258
65004	29295	227	0	24	0	30	0	0	0	0	0	3	0	0	0	4624	28873	0	1	0	17017	6012	1000	4000	1000	1000	4000	1000	5000	5000	47549	6	22910	29213	29463	3	10	6000	1000	4000	2000	4000	29169	29254	1	1	61001	1000	1000	0	1000	0	3	1001	0	1	0	1	1002	2	0	3	0	0	0	13096	9312	6862	3090	10	67	20295	3131	3804	16	65	64	28552	1000	16442	13194	14357	1000	4000	1000	29392	29503	29469	29316	29377
65004	29365	227	0	23	1	24	0	1	1	0	0	12	0	0	0	4691	28849	0	1	1	17197	6000	1000	4016	1000	1000	4000	1000	5000	5000	47556	4	22853	29229	29259	3	10	6000	1000	4000	2000	4000	29296	29157	1	1	61001	1000	1000	0	1000	0	3	1000	0	0	0	0	1000	0	1	3	0	0	0	13117	9197	6895	3080	10	69	20137	3298	3803	25	70	68	28482	1000	16493	13051	14556	1000	4000	1000	29482	29353	29400	29408	29403
65004	29340	227	0	24	0	20	0	1	1	0	0	4	0	0	0	4603	28890	0	1	1	17191	6016	1000	4000	1000	1000	4000	1000	5000	5000	47426	6	22897	29199	29442	3	10	6000	1000	4000	2000	4000	29199	29210	1	1	61001	1000	1000	0	1000	0	0	1000	0	0	0	0	1000	2	0	3	0	0	0	12970	9442	6856	3141	9	66	20274	3197	3802	20	66	75	28560	1000	16196	13362	14487	1000	4000	1000	29419	29349	29432	29307	29374
65004	29442	227	0	26	0	25	0	0	0	0	0	4	0	0	0	4619	28845	0	0	0	17039	6012	1000	4012	1000	1000	4000	1000	5000	5000	47595	15	22842	29197	29273	3	10	6000	1000	4000	2000	4000	29230	29208	1	1	61001	1000	1000	0	1000	0	3	1001	0	0	0	0	1001	0	0	3	0	0	0	12848	9388	6934	3114	11	71	20403	3151	3808	13	72	70	28648	1000	16037	13193	14226	1000	4000	1000	29463	29390	29339	29393	29381
65004	29396	227	0	28	0	26	1	0	0	0	0	3	0	0	0	4712	28957	0	0	1	17101	6012	1000	4000	1000	1000	4000	1000	5000	5000	47400	4	22858	29066	29389	3	10	6000	1000	4000	2002	4000	29243	29364	1	1	61001	1000	1000	0	1000	0	0	1001	0	0	0	3	1001	2	0	0	0	0	0	13087	9330	6863	3073	9	71	20347	3122	3810	20	71	77	28547	1000	16492	13303	14437	1000	4000	1000	29361	29451	29342	29301	29345
65004	29201	227	0	23	0	22	0	0	0	0	0	0	0	0	0	4640	28871	0	0	1	17128	6012	1000	4000	1000	1000	4000	1000	5000	5000	47621	4	22924	29153	29362	3	10	6000	1000	4000	2000	4000	29217	29234	1	1	61001	1000	1000	0	1000	0	3	1001	0	0	0	5	1001	2	2	3	0	0	0	13087	9263	6935	3100	12	74	20226	3180	3812	17	68	66	28507	1000	16306	13358	14534	1000	4000	1000	29354	29383	29417	29346	29368

Count: 8

Code:

  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	80057	620	0	0	0	1	0	0	0	18	0	0	0	0	80042	1	6	6	0	25	480156	80100	320000	80000	80100	320000	80000	480499	480020	7680020	0	80038	80057	80057	0	0	3	39	480100	200	80000	320000	200	160000	320000	80057	80047	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	13	80009	1	0	16	80009	6	1	10	0	0	5109	1	17	1	1	80039	0	80000	0	6	80000	320000	80100	80043	80043	80043	80046	80058
400204	80054	620	0	1	0	0	1	0	0	31	0	0	0	0	80030	0	6	0	0	25	480156	80100	320056	80000	80100	320000	80000	480499	479998	7680020	0	80038	80057	80057	0	0	3	36	480100	200	80000	320000	200	160000	320000	80057	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	13	80000	0	0	12	80000	6	0	10	17	0	5109	1	17	1	2	80054	0	80000	0	0	80000	320000	80100	80063	80058	80043	80043	80055
400204	80043	620	0	0	0	0	1	0	0	19	0	0	0	0	80042	1	0	0	0	25	480100	80100	320056	80000	80100	320000	80000	480499	480014	7680020	0	80038	80057	80042	0	0	3	24	480100	200	80000	320000	200	160000	320000	80057	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80012	1	0	0	80012	6	1	10	17	0	5139	2	44	0	1	80453	0	80230	0	0	80000	320000	80100	80429	80266	80345	80444	80433
400204	80484	624	1	0	0	0	0	0	0	9	0	1	0	0	80027	0	6	0	0	25	480156	80100	320056	80000	80100	320000	80000	480499	480006	7680020	0	80038	80042	80057	0	0	3	24	480100	200	80000	320000	200	160000	320000	80042	80054	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	0	80013	0	0	0	80013	6	1	9	17	0	5109	1	17	1	1	80054	1	80000	9	0	80000	320000	80100	80058	80058	80043	80058	80046
400204	80042	621	0	0	0	0	0	0	0	0	0	0	0	0	80027	1	6	6	0	25	480156	80100	320056	80000	80100	320000	80000	480499	479998	4797016	0	80038	80057	80057	0	0	3	39	480100	200	80000	320000	200	160000	320000	80057	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	17	80000	0	0	9	80013	6	0	0	0	0	5109	1	17	1	1	80039	1	80000	9	9	80000	320000	80100	80043	80056	80058	80058	80055
400204	80057	649	1	0	0	0	0	0	1	148	0	1	0	0	80180	1	6	0	0	25	480156	80180	320056	80068	80100	320308	80000	480499	480011	5021508	1	80038	80042	80042	0	0	3	39	480100	200	80000	320000	200	160000	320000	80057	80194	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	17	80000	0	0	13	80037	6	1	10	0	2	5109	1	25	1	1	80039	1	80000	0	0	80000	320000	80100	80087	80058	80043	80043	80196
400204	80196	620	0	0	0	1	1	0	0	132	0	1	0	0	80042	1	6	0	0	25	480156	80100	320304	80000	80100	320000	80080	480499	479998	7680020	0	80035	80042	80042	0	0	3	24	480100	200	80000	320000	200	160000	320000	80057	80196	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	13	80076	0	0	0	80009	6	1	0	17	0	5109	1	17	1	1	80163	0	80000	9	6	80000	320000	80100	80058	80058	80058	80196	80043
400204	80042	620	1	0	0	0	1	1	0	0	0	0	0	0	80182	1	6	6	0	25	480156	80181	320056	80000	80100	320320	80000	480499	479998	4197432	1	80023	80057	80195	0	13	3	89	480100	200	80000	320000	200	160000	320324	80045	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80013	0	0	12	80010	6	1	10	0	0	5109	1	17	1	1	80039	0	80000	9	6	80000	320000	80100	80043	80058	80196	80058	80111
400204	80042	621	0	0	0	0	0	0	0	18	0	0	0	0	80039	0	0	6	0	25	480100	80100	320000	80000	80100	320000	80000	480499	480014	7680020	0	80023	80057	80054	0	0	3	39	480100	200	80000	320000	200	160000	320000	80042	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80013	0	0	0	80013	6	1	0	0	0	5109	1	17	1	1	80042	0	80000	10	6	80000	320000	80100	80045	80043	80058	80058	80043
400204	80042	620	0	0	0	1	0	0	0	0	0	1	0	0	80027	0	0	6	0	25	480100	80100	320056	80000	80100	320000	80000	480499	480005	8639988	1	80038	80057	80057	0	0	3	39	480100	200	80000	320000	200	160000	320000	80057	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	13	80000	0	0	0	80012	6	1	10	17	0	5109	1	17	1	2	80054	0	80000	0	0	80000	320000	80100	80058	80058	80058	80058	80451

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80066	621	1	0	0	0	0	0	0	0	0	35	0	1	0	0	0	80051	1	6	6	2	25	480058	80010	320048	80000	80010	320000	80000	480049	480040	10880304	0	80047	80066	80066	0	0	3	48	480010	20	80000	320000	20	160000	320000	80066	80066	1	1	80021	10	9	10	10	80000	80000	0	10	80007	5	27	80031	0	0	28	80023	0	1	29	27	6	2	5019	0	0	13	17	16	11	80044	1	80000	13	13	80000	320000	80010	80067	80067	80067	80073	80067
400024	80196	622	1	0	0	0	0	0	0	0	0	35	0	0	0	0	0	80032	1	6	6	2	25	480066	80010	320048	80000	80010	320000	80000	480049	480040	10880304	0	80029	80066	80066	0	0	3	48	480010	20	80000	320000	20	160000	320000	80066	80066	1	1	80021	10	9	10	10	80000	80000	1	10	80007	6	27	80029	0	0	31	80023	6	1	29	26	6	0	5019	0	0	13	17	13	6	80063	1	80000	13	13	80000	320000	80010	80049	80067	80067	80067	80067
400024	80066	620	1	0	0	0	0	1	1	0	0	59	0	0	0	0	0	80051	1	6	6	2	25	480058	80010	320048	80000	80010	320000	80000	480049	480007	10880304	0	80047	80066	80066	0	0	3	29	480010	20	80000	320000	20	160000	320000	80066	80066	1	1	80021	10	9	10	10	80000	80000	0	10	80006	7	27	80029	0	0	28	80023	6	1	29	0	6	0	5019	0	0	5	17	5	14	80063	1	80000	13	13	80000	320000	80010	80067	80067	80067	80049	80067
400024	80066	620	1	0	0	0	0	0	0	0	0	35	0	1	0	0	1	80051	1	0	0	2	25	480062	80010	320048	80000	80087	320640	80160	480049	480038	10880304	0	80047	80066	80066	0	0	3	48	480010	20	80000	320000	20	160000	320000	80066	80066	1	1	80021	10	9	10	10	80000	80000	1	10	80007	7	0	80029	0	0	28	80023	6	1	6	27	6	1	5019	0	0	5	17	14	7	80063	1	80000	13	13	80000	320000	80010	80067	80067	80067	80067	80067
400024	80066	621	1	0	0	0	1	1	0	0	0	5	0	1	0	0	0	80051	0	0	0	2	25	480058	80010	320024	80000	80010	320000	80000	480048	480045	10880304	0	80047	80066	80066	0	0	3	48	480010	20	80000	320000	20	160000	320000	80066	80066	1	1	80021	10	9	10	10	80000	80000	0	10	80005	6	26	80028	0	1	28	80023	6	1	29	26	6	1	5019	0	0	5	17	13	7	80044	1	80000	13	13	80000	320000	80010	80067	80067	80067	80067	80067
400024	80066	621	1	0	1	0	1	0	1	0	0	35	0	0	0	0	0	80051	0	6	6	2	25	480066	80010	320048	80000	80010	320000	80000	480049	480040	10880304	0	80047	80048	80066	0	0	3	48	480010	20	80000	320000	20	160000	320000	80066	80066	1	1	80021	10	9	10	10	80000	80000	0	10	80008	5	27	80006	0	0	30	80021	6	1	28	27	5	2	5019	0	0	15	17	14	13	80045	1	80000	0	13	80000	320000	80010	80067	80049	80067	80067	80067
400024	80066	620	1	0	1	0	0	1	1	0	0	35	0	0	1	0	0	80051	1	0	6	2	25	480058	80010	320056	80000	80010	320000	80000	480049	480045	10880304	0	80047	80066	80066	0	0	3	48	480010	20	80000	320000	20	160000	320000	80066	80066	1	1	80021	10	9	10	10	80000	80000	0	10	80005	6	27	80029	1	1	6	80026	6	1	6	26	6	2	5019	0	0	11	17	15	13	80044	1	80000	13	13	80000	320000	80010	80067	80067	80067	80067	80067
400024	80066	620	1	0	0	0	1	1	1	0	0	33	0	0	0	0	0	80052	1	6	6	2	25	480066	80010	320048	80000	80010	320000	80000	480049	480040	10880304	0	80047	80066	80066	0	0	3	48	480010	20	80000	320000	20	160000	320000	80066	80066	1	1	80021	10	9	10	10	80000	80000	0	10	80006	7	27	80028	1	1	28	80000	6	1	5	27	5	0	5019	0	0	5	17	5	14	80063	0	80000	0	0	80000	320000	80010	80067	80067	80067	80067	80067
400024	80066	621	1	0	1	1	0	0	0	0	0	55	0	0	1	0	0	80051	1	6	6	2	25	480066	80010	320048	80000	80010	320324	80000	480049	480040	10880304	0	80047	80066	80066	0	0	3	48	480010	20	80000	320000	20	160000	320000	80066	80066	1	1	80021	10	9	10	10	80000	80000	0	10	80005	6	27	80030	0	0	28	80000	6	1	6	27	5	1	5019	0	0	15	17	14	14	80063	1	80000	13	13	80000	320000	80010	80067	80067	80067	80049	80067
400024	80066	621	1	0	1	0	1	0	0	0	0	34	0	0	0	0	0	80051	1	0	6	2	25	480058	80010	320048	80000	80010	320348	80000	480049	480045	10880304	0	80047	80048	80066	0	0	3	53	480010	20	80000	320000	20	160000	320000	80066	80066	1	1	80021	10	9	10	10	80000	80000	0	10	80005	6	27	80030	0	0	32	80021	0	0	28	26	6	1	5019	0	0	14	17	14	7	80063	1	80000	14	13	80000	320000	80010	80067	80067	80067	80067	80067

LD4R (post-index, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations