Firestorm: LD4R (post-index, 4S) measurements

Code:

  ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 6.012

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.012

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
65005	29506	237	0	0	2	0	1	1	0	0	0	0	0	3	0	0	4707	28880	0	1	1	17051	6012	1000	4012	1000	1000	4000	1000	5000	5000	47594	0	5	0	0	22899	29232	29451	3	10	6000	1000	4000	2000	4000	29257	29442	1	1	61001	1000	1000	1	1000	0	3	1003	1	2	2	1001	0	1	0	0	0	0	13196	9132	6905	3164	0	48	20346	3355	3812	19	52	57	29244	1000	16259	13211	14412	1000	4000	1000	29396	29383	29486	29621	29797
65004	29602	237	1	0	0	0	0	0	0	0	0	0	0	12	0	0	4648	28806	0	0	0	17345	6012	1000	4008	1000	1000	4000	1000	5000	5000	47570	0	10	0	0	23021	30432	31056	47	182	6003	1000	4000	2000	4000	29168	29152	1	1	61001	1000	1000	0	1001	2	3	1001	0	1	1	1000	2	1	3	0	0	1146	13171	9452	6986	3170	0	50	20265	3167	3813	14	51	50	28974	1000	16255	13273	14726	1000	4000	1000	29125	29140	29017	29792	29224
65004	28962	232	0	0	0	1	0	0	0	0	0	17	13	2650	1496	0	4528	29069	0	1	1	16865	6048	1000	4008	1004	1009	4040	1009	5055	5193	47644	0	10	0	0	23000	29251	29699	20	220	6047	1000	4000	2008	4032	29048	29243	16	1	61001	1000	1000	1	1000	0	3	1003	0	1	4	1001	3	1	3	0	0	0	13120	9402	6935	3101	0	58	20249	3157	3798	19	55	58	28413	1000	16134	13137	14159	1000	4000	1000	29195	29033	29334	29330	29204
65004	29366	226	1	1	0	0	2	0	0	0	0	0	0	138	0	0	4592	28815	0	1	1	17032	6012	1000	4012	1000	1000	4004	1000	5000	5006	47643	0	10	0	0	22862	29113	29324	7	48	6000	1000	4004	2000	4000	29143	29234	1	1	61001	1000	1000	1	1002	1	3	1004	0	1	2	1002	2	0	3	0	0	0	12961	9390	6877	3036	0	50	20168	3308	3806	11	55	51	28535	1000	16405	13350	14096	1000	4000	1000	29216	29251	29326	29280	29226
65004	29161	226	0	0	0	1	0	0	0	0	0	0	0	264	0	0	4690	28848	0	0	1	17012	6000	1000	4000	1000	1000	4000	1000	5000	5000	47422	0	10	0	0	22874	29135	29148	3	10	6000	1000	4000	2000	4000	29285	29136	1	1	61001	1000	1000	0	1002	2	3	1001	0	1	2	1002	0	0	3	0	0	0	13019	9151	6971	3092	0	56	20068	3230	3809	11	51	53	28494	1000	15938	13172	14333	1000	4000	1000	29257	29262	29199	29284	29217
65004	29221	227	1	0	0	0	0	0	0	0	0	0	0	0	0	0	4598	28906	0	1	0	17085	6000	1000	4000	1000	1000	4000	1000	5000	5000	47432	0	11	0	0	22865	29141	29405	3	10	6000	1000	4000	2000	4000	29247	29176	1	1	61001	1000	1000	1	1002	2	0	1003	0	1	1	1001	0	1	0	0	0	0	12918	9375	6851	3169	0	44	20259	3196	3809	12	55	51	28469	1000	16258	13179	14278	1000	4000	1000	29332	29191	29264	29252	29312
65004	29192	227	0	1	0	0	0	0	0	0	0	0	0	6	0	0	4679	28819	0	1	0	16967	6012	1000	4004	1000	1000	4000	1000	5000	5000	47418	0	10	0	0	22921	29134	29266	3	10	6000	1000	4000	2000	4000	29126	29076	1	1	61001	1000	1000	1	1001	2	4	1001	1	1	2	1000	3	1	3	0	0	0	12989	9099	6934	3086	0	52	20142	3171	3807	11	55	54	28415	1000	15953	12996	14374	1000	4000	1000	29345	29550	29180	29147	29263
65004	29260	227	0	0	0	0	0	0	0	0	0	0	0	12	0	0	4543	28797	0	1	0	16926	6012	1000	4012	1000	1000	4000	1000	5000	5000	47422	0	5	1	0	22874	29105	29216	3	10	6000	1000	4000	2000	4000	29256	29195	1	1	61001	1000	1000	1	1002	2	3	1001	0	0	4	1000	3	0	0	1	1	0	13112	9241	6930	3132	1	58	20244	3232	3814	20	57	54	28541	1000	16201	13043	14484	1000	4000	1000	29406	29338	29221	29205	29307
65004	29378	227	1	0	0	0	0	0	0	0	0	0	0	3	0	0	4602	28904	0	1	1	17050	6012	1000	4016	1000	1000	4000	1000	5000	5000	47585	0	5	0	0	22928	29146	29368	3	10	6000	1000	4000	2000	4000	29193	29152	1	1	61001	1000	1000	0	1002	2	0	1002	0	1	1	1000	3	0	0	0	0	0	13081	9228	6919	3157	0	51	20290	3214	3812	7	55	52	28500	1000	16268	13283	14228	1000	4000	1000	29335	29347	29323	29266	29191
65004	29291	227	1	0	0	0	0	0	0	0	0	0	0	3	0	0	4494	28781	0	1	1	16980	6012	1000	4016	1000	1000	4000	1000	5000	5000	47630	0	5	0	0	22903	29213	29303	3	10	6000	1000	4000	2000	4000	29179	29224	1	1	61001	1000	1000	0	1002	2	0	1001	0	1	1	1002	0	0	0	0	0	0	13214	9262	6932	3154	1	53	20246	3238	3814	16	59	56	28489	1000	15947	13228	14233	1000	4000	1000	29271	29383	29366	29305	29366

Count: 8

Code:

  ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	80054	643	0	0	0	0	0	0	34	0	0	80042	1	6	6	0	63	480156	80100	320056	80000	80100	320000	80000	480499	479999	7680020	80038	0	80057	80058	0	0	3	39	480100	200	80000	320000	200	160000	320000	80057	80196	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	13	80013	1	0	12	80012	6	0	9	17	0	0	5125	1	16	1	1	80054	1	80000	9	6	80000	320000	80100	80197	80058	80058	80058	80198
400204	80057	643	0	0	0	0	0	0	154	0	0	80042	1	0	6	0	25	480156	80100	320056	80076	80100	320000	80000	480499	480010	7680020	80038	0	80197	80055	0	0	26	39	480100	200	80075	320000	200	160000	320000	80054	80054	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	15	80013	1	0	19	80000	6	1	12	13	0	0	5109	1	25	1	1	80054	0	80000	9	6	80000	320000	80100	80058	80196	80058	80044	80058
400204	80057	643	0	0	0	0	0	0	22	0	0	80030	1	6	6	0	25	480168	80100	320056	80228	80100	320000	80000	480499	480019	7680020	80038	0	80057	80057	20	0	3	39	480556	200	80000	320000	200	160000	320320	80045	80054	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	17	80013	4	0	1001	80012	6	1	10	13	0	0	5109	1	17	1	1	80054	1	80000	9	9	80000	320000	80100	80058	80058	80058	80058	80197
400204	80057	643	0	0	0	0	0	0	22	88	1	80039	1	0	6	0	25	480148	80100	320056	80000	80100	320000	80000	480970	480007	7680020	80038	0	80058	80057	0	15	3	39	480100	200	80000	320000	200	160000	320000	80057	80194	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	17	80013	0	0	13	80013	6	0	9	17	0	0	5109	1	17	1	1	80054	1	80080	9	6	80000	320000	80100	80058	80058	80058	80059	80058
400204	80057	644	0	0	0	0	0	0	34	0	0	80042	1	6	6	22	25	480156	80100	320056	80000	80100	320000	80000	480499	480014	7680020	80039	0	80057	80057	0	0	3	39	480544	200	80000	320000	200	160000	320000	80057	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	17	80013	1	0	14	80009	6	0	0	17	0	0	5109	1	17	1	1	80054	1	80000	9	6	80000	320000	80100	80058	80197	80058	80058	80058
400204	80043	643	0	0	0	0	0	0	35	0	0	80182	1	6	0	0	63	480156	80100	320304	80000	80100	320000	80000	480499	480006	7680020	80038	0	80057	80057	0	0	3	39	480558	200	80000	320000	200	160150	320000	80042	80054	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	13	80000	0	0	12	80012	6	1	10	17	0	0	5109	1	17	1	1	80054	0	80000	9	6	80000	320000	80100	80043	80058	80058	80058	80058
400204	80057	643	0	0	0	0	0	0	19	0	0	80042	1	6	6	0	25	480156	80100	320304	80000	80100	320000	80000	480499	480011	6033408	80038	0	80057	80057	0	0	3	39	480100	200	80000	320000	200	160162	320000	80057	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	13	80000	0	0	13	80013	6	1	0	17	0	0	5123	1	17	1	1	80054	0	80000	9	9	80000	320000	80100	80058	80056	80058	80058	80058
400204	80057	644	0	0	0	0	0	0	19	0	0	80042	1	6	6	0	25	480156	80100	320056	80000	80100	320000	80000	480499	481701	4206144	80038	0	80195	80057	0	0	26	39	480100	200	80080	320000	200	160154	320300	80057	80057	2	1	80201	100	99	100	100	80000	80000	1	100	80000	0	13	80013	0	0	878	80013	6	1	0	17	0	0	5109	1	17	1	1	80287	1	80000	9	10	80000	320000	80100	80058	80197	80197	80058	80058
400204	80042	643	1	0	0	0	0	0	19	88	0	80042	1	6	6	0	25	480156	80100	320056	80000	80100	320304	80000	480499	480011	7680024	80038	0	80057	80059	0	0	26	39	480100	200	80000	320000	200	160000	320000	80057	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80013	0	0	13	80016	6	1	10	18	0	0	5109	1	17	1	1	80039	0	80000	9	6	80000	320000	80100	80055	80043	80058	80058	80058
400204	80195	643	0	0	0	0	0	0	19	0	0	80042	1	6	6	0	25	480156	80100	320304	80000	80100	320000	80000	480499	480011	6272140	80038	0	80042	80057	0	0	3	39	480100	200	80000	320000	200	160000	320000	80057	80055	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	13	80013	0	0	895	80000	6	1	10	17	0	0	5109	2	17	1	1	80054	0	80000	9	0	80000	320000	80100	80058	80055	80043	80058	80058

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80058	621	0	1	0	0	0	0	0	21	0	1	0	80045	1	6	6	0	25	480082	80010	320072	80000	80010	320000	80000	480049	481661	9600020	0	0	80026	80042	80060	0	0	3	39	480010	20	80000	320000	20	160000	320000	80060	80057	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	18	80015	1	0	0	80015	6	1	14	20	5019	0	0	0	2	17	2	2	80057	1	80000	0	10	80000	320000	80010	80061	80063	80061	80061	80061
400024	80057	620	0	0	0	0	0	0	0	34	0	1	0	80045	1	6	6	0	25	480082	80010	320072	80000	80010	320000	80000	480049	480021	8640020	0	0	80041	80060	80060	0	0	3	39	480010	20	80000	320000	20	160000	320000	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80000	0	0	19	80015	6	1	15	0	5019	0	0	0	2	17	2	2	80057	1	80000	13	0	80000	320000	80010	84086	82814	80456	80058	80058
400024	80060	621	0	0	0	0	0	0	0	22	0	1	0	80180	1	6	6	0	25	480082	80010	320072	80000	80010	320320	80000	480049	480015	8640020	0	0	80038	80060	80060	20	0	3	39	480010	20	80000	320000	20	160000	320000	80061	80060	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80015	0	0	17	80017	6	1	14	0	5019	0	0	0	1	17	2	2	80057	1	80000	13	10	80000	320000	80010	80061	80043	80061	80046	80196
400024	80060	621	0	0	0	0	0	0	0	34	0	1	0	80027	1	6	6	0	25	480082	80010	320072	80000	80010	320000	80083	480049	480005	8640020	0	0	80041	80042	80060	0	0	3	24	480010	20	80000	320000	20	160000	320000	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	20	80015	1	0	14	80015	6	1	13	20	5019	0	0	0	2	17	1	2	80054	0	80000	13	10	80000	320000	80010	80061	80061	80043	80043	80061
400024	80195	621	0	0	0	0	0	0	0	21	0	1	0	80045	1	6	6	0	25	480082	80010	320072	80000	80010	320000	80000	480049	479998	8640020	0	0	80041	80061	80057	0	0	3	42	480490	20	80000	320000	20	160000	320000	80057	80060	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	20	80015	0	0	0	80016	6	1	16	20	5019	0	0	0	4	17	2	2	80054	0	80000	11	0	80000	320000	80010	80061	80061	80058	80061	80046
400024	80042	621	0	0	0	0	0	0	0	154	0	1	0	80045	1	6	6	0	25	480070	80010	320072	80000	80010	320000	80000	480049	480014	8640020	0	0	80023	80060	80060	0	0	3	42	480010	20	80000	320000	20	160000	320000	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	20	80015	1	0	895	80016	6	1	14	20	5019	0	0	0	1	17	1	2	80057	1	80000	13	0	80000	320000	80010	80061	80061	80061	80061	80061
400024	80060	620	0	0	0	0	0	0	0	20	0	1	0	80042	1	0	6	0	25	480082	80085	320072	80000	80010	320000	80000	480049	480021	8640020	0	0	80041	80060	80042	0	0	3	39	480010	20	80000	320000	20	160000	320308	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80015	2	0	16	80013	6	1	15	0	5019	0	0	0	2	17	2	2	80163	1	80000	0	13	80000	320000	80010	80061	80061	80043	80061	80061
400024	80057	620	0	0	0	0	0	0	0	22	0	1	0	80182	1	6	6	0	25	480082	80010	320072	80000	80085	320000	80000	480049	480011	8640020	0	0	80041	80195	80060	0	0	3	39	480010	20	80000	320324	20	160000	320000	80148	80042	2	1	80021	10	9	10	10	80000	80000	0	10	80158	2	18	80178	0	0	1776	80173	6	1	14	20	5034	0	0	0	1	25	1	3	80163	1	81440	13	10	80000	320000	80010	80195	80197	80198	80087	80197
400024	80351	622	0	0	1	0	0	1	1	418	88	1	0	80179	1	6	0	22	63	480898	80171	323224	81279	81447	324468	81517	489084	510378	5416816	0	0	80146	80193	80506	40	16	73	96	480970	20	80079	320624	20	160150	320644	80351	80197	3	1	80021	10	9	10	10	80000	80000	0	10	80157	2	20	80099	0	0	901	80090	6	1	13	20	5019	0	0	0	2	17	2	2	80057	0	80000	13	15	80000	320000	80010	80058	80046	80061	80058	80058
400024	80060	621	0	0	0	0	0	0	0	22	0	0	0	80045	1	6	6	0	25	480082	80010	320060	80000	80010	320000	80000	480049	480015	8640020	0	0	80041	80060	80060	0	0	3	34	480010	20	80000	320000	20	160000	320000	80042	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	20	80016	0	0	18	80016	6	1	14	0	5019	0	0	0	2	17	1	1	80057	1	80000	10	13	80000	320000	80010	80061	80061	80061	80061	80061

LD4R (post-index, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations