Firestorm: LD4R (post-index, 8B) measurements

Code:

  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 6.008

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	1e	23	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
65005	29321	221	1	0	32	0	1	22	0	0	3	0	4562	28855	0	1	1	16938	6000	1000	4016	1000	1000	4000	1000	5000	5000	47420	17	22821	29101	29329	3	10	6000	1000	4000	2000	4000	29235	29164	1	1	61001	1000	1000	1000	0	2	1000	0	0	0	1000	2	0	3	0	0	0	12797	9103	6803	3033	12	60	20245	3071	3815	21	58	57	28426	1000	16274	13291	14234	1000	4000	1000	29351	29326	29240	29270	29362
65004	29370	220	0	0	26	0	0	23	0	0	2	0	4681	28866	1	0	0	16939	6008	1000	4012	1000	1000	4000	1000	5000	5000	47551	3	22970	29219	29388	3	10	6000	1000	4000	2000	4000	29242	29112	1	1	61001	1000	1000	1001	2	2	1003	0	1	1	1001	2	1	0	1	1	351	13366	9226	6891	3080	10	67	20294	3336	3815	18	63	62	28019	1000	16318	13115	14462	1000	4000	1000	29299	29363	29236	29307	29300
65004	29488	228	0	1	23	1	0	24	1	0	3	0	4522	28838	0	0	0	16993	6008	1000	4008	1000	1000	4000	1000	5000	5000	47420	3	22893	29126	29396	3	10	6000	1000	4000	2000	4000	29189	29285	1	1	61001	1000	1000	1000	0	0	1000	0	0	0	1000	2	0	2	0	0	0	13083	9248	6865	3092	13	56	20282	3094	3821	19	58	59	28406	1000	16334	13239	14261	1000	4000	1000	29294	29242	29464	29320	29545
65004	29356	220	0	0	22	0	0	21	0	0	4	0	4667	28860	0	0	1	17030	6008	1000	4008	1000	1000	4000	1000	5000	5000	47552	3	22864	29027	29394	3	10	6000	1000	4000	2000	4000	29196	29188	1	1	61001	1000	1000	1000	0	2	1000	0	0	0	1000	2	0	2	0	0	0	12831	9263	6825	3146	6	58	20201	3078	3816	23	58	57	28506	1000	16404	13204	14509	1000	4000	1000	29283	29335	29391	29424	29342
65004	29324	219	0	0	26	0	0	22	0	0	0	0	4547	28860	0	0	0	16995	6016	1000	4008	1000	1000	4000	1000	5000	5000	47584	0	22883	29146	29249	3	10	6000	1000	4000	2000	4000	29169	29182	1	1	61001	1000	1000	1000	0	2	1000	3	0	3	1000	0	0	0	0	0	0	12940	9230	6861	3064	11	58	20106	3048	3813	17	55	57	28469	1000	16233	13116	14328	1000	4000	1000	29350	29352	29282	29392	29371
65004	29289	219	0	0	24	0	0	25	0	0	3	0	4581	28886	0	1	1	16958	6008	1000	4016	1000	1000	4000	1000	5000	5000	47597	3	22851	29054	29294	3	10	6000	1000	4000	2000	4000	29156	29200	1	1	61001	1000	1000	1000	0	0	1000	0	0	0	1000	0	0	2	0	0	0	12998	9281	6882	3078	11	59	20197	3066	3815	15	72	61	28489	1000	16420	13336	14342	1000	4000	1000	29343	29295	29318	29273	29282
65004	29359	220	0	0	23	0	0	22	0	0	2	0	4683	28837	0	1	0	17030	6000	1000	4016	1000	1000	4000	1000	5000	5000	47548	0	22706	29216	29359	3	10	6000	1000	4000	2000	4000	29262	29194	1	1	61001	1000	1000	1000	0	3	1002	6	0	0	1000	2	1	0	0	0	0	12789	9062	6836	3034	9	66	20273	3049	3819	20	50	58	28522	1000	16371	13220	14256	1000	4000	1000	29333	29402	29317	29329	29343
65004	29474	242	0	0	22	0	0	24	0	0	0	0	4599	28804	0	0	0	16963	6008	1000	4008	1000	1000	4000	1000	5000	5000	47552	6	22887	29104	29403	3	10	6000	1000	4000	2000	4000	29223	29266	1	1	61001	1000	1000	1000	0	3	1000	0	0	2	1000	0	2	2	0	0	0	12766	9190	6842	3072	4	61	20342	3105	3817	20	53	54	28424	1000	16438	13199	14535	1000	4000	1000	29291	29336	29433	29413	29261
65004	29299	220	0	1	21	1	0	21	1	0	5	0	4699	28808	1	0	0	17132	6004	1000	4004	1000	1000	4000	1000	5000	5000	47436	3	22881	29085	29324	3	10	6000	1000	4000	2000	4000	29228	29147	1	1	61001	1000	1000	1001	4	3	1003	0	2	1	1001	0	2	3	1	3	0	12842	9130	6833	3044	9	71	20303	3108	3811	19	59	59	28406	1000	16067	13256	14432	1000	4000	1000	29241	29311	29325	29435	29439
65004	29232	220	0	1	22	0	0	22	1	0	4	0	4578	28831	0	0	0	16908	6008	1000	4008	1000	1000	4000	1000	5000	5000	47582	2	22874	29132	29309	3	10	6000	1000	4000	2000	4000	29259	29231	1	1	61001	1000	1000	1000	0	2	1000	0	0	0	1000	2	0	0	0	0	0	12946	9222	6831	3066	11	68	20186	3105	3815	23	60	62	28539	1000	16250	13089	14230	1000	4000	1000	29384	29291	29262	29333	29278

Count: 8

Code:

  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	80069	599	0	0	0	1	0	0	0	19	0	0	0	80042	1	6	6	0	25	480156	80100	320052	80000	80100	320000	80000	480499	480005	7680020	0	80038	80057	80057	0	0	3	39	480100	200	80000	320000	200	160000	320000	80054	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	13	80000	0	0	12	80013	6	1	10	0	0	0	0	5109	1	17	2	1	80055	1	80000	4	6	80000	320000	80100	80058	80058	80058	80058	80058
400204	80054	620	0	0	0	0	0	0	0	52	0	0	0	80042	1	6	6	0	25	480100	80100	320048	80000	80100	320000	80000	480499	480005	7680020	0	80038	80057	80057	0	0	3	39	480100	200	80000	320324	200	160000	320000	80057	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	13	80013	1	0	19	80087	6	1	10	17	0	0	0	5109	1	17	1	1	80054	0	80000	9	6	80000	320000	80100	80058	80058	80058	80046	80058
400204	80057	620	0	0	0	0	0	0	0	20	0	0	0	80030	1	6	6	0	25	480100	80100	320048	80000	80100	320000	80000	480499	480005	4159992	0	80038	80057	80057	0	0	3	89	480100	200	80000	320000	200	160000	320000	80042	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	17	80090	1	0	13	80012	6	1	10	17	0	0	0	5109	1	25	1	1	80054	0	80000	0	6	80000	320000	80100	80043	80043	80058	80058	80058
400204	80057	620	0	0	0	0	0	0	0	19	0	0	0	80042	1	0	6	0	25	480564	80100	320056	80000	80100	320000	80000	480499	480007	7680020	0	80038	80057	80057	0	0	3	39	480100	200	80000	320000	200	160000	320000	80196	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	17	80013	0	0	117	80013	6	1	9	17	0	0	0	5109	1	17	1	1	80054	0	80000	9	7	80000	320000	80100	80058	80058	80058	80058	80195
400204	80047	621	0	0	0	0	0	0	0	18	0	0	0	80042	1	6	6	0	25	480156	80100	320048	80062	80100	320000	80000	480499	480005	7680020	0	80038	80057	80057	0	0	3	39	494496	200	80000	320000	200	160000	320000	80057	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80000	0	3	25	80013	6	1	10	17	0	0	0	5109	1	17	1	1	80054	1	80000	9	0	80000	320000	80100	80058	80058	80043	80055	80043
400204	80057	620	0	0	1	0	0	0	0	19	0	0	0	80042	0	6	6	0	25	480156	80180	320024	80000	80100	320000	80000	480499	480006	8960020	0	80038	80057	80057	0	0	3	39	480100	200	80000	320000	200	160000	320000	80057	80054	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80013	0	1	13	80013	6	1	0	17	0	0	0	5109	1	17	1	1	80054	1	80000	9	9	80000	320000	80100	80055	80058	80058	80058	80196
400204	80057	620	0	0	0	0	0	0	0	19	0	0	0	80042	0	6	6	0	25	480156	80100	320056	80000	80100	320000	80000	480499	480013	7680020	0	80023	80042	80057	0	0	3	39	480100	200	80000	320000	200	160000	320000	80057	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	13	80013	1	0	18	80012	6	1	10	0	0	0	0	5109	1	17	1	1	80054	0	80000	9	9	80000	320000	80100	80058	80058	80058	80058	80058
400204	80057	620	0	0	0	0	0	0	0	23	0	0	0	80042	0	6	6	0	25	480156	80100	320048	80000	80100	320000	80000	480499	479998	7680020	0	80038	80057	80057	0	0	3	24	480100	200	80000	320000	200	160150	320000	80045	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	13	80013	0	0	12	80010	0	1	0	0	0	0	0	5109	1	17	1	1	80039	1	80000	0	9	80000	320000	80100	80058	80058	80058	80058	80058
400204	80043	620	0	0	0	0	0	0	0	0	0	0	0	80039	1	0	6	0	25	480164	80100	320056	80000	80100	320000	80000	480499	481695	4159992	0	80038	80042	80042	0	0	3	24	480100	200	80000	320000	200	160108	320000	80057	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	13	80012	0	0	19	80000	0	0	0	0	0	1	0	5109	1	17	1	1	80054	1	80000	9	9	80000	320000	80100	80058	80058	80058	80058	80058
400204	80057	621	0	0	0	0	0	0	0	19	0	0	0	80042	0	0	6	0	25	480156	80100	320056	80000	80100	320000	80000	480499	480006	8639988	0	80038	80057	80057	0	0	3	36	480100	200	80000	320000	200	160000	320000	80057	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	13	80013	0	1	18	80012	6	1	13	0	0	0	0	5109	1	17	1	1	80166	1	80000	9	9	80000	320000	80100	80058	80058	80058	80197	80058

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80070	622	0	0	0	0	0	0	0	1	32	0	1	0	0	0	80194	1	6	6	0	25	480082	80010	320060	80000	80010	320000	80000	480049	480019	8960020	0	80038	0	80057	80057	0	0	3	39	480010	20	80000	320280	20	160000	320000	80057	80057	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	18	80014	1	0	20	80014	6	1	14	18	0	5019	1	17	1	1	80055	1	80000	10	10	80000	320000	80010	80061	80061	80197	80059	80058
400024	80057	621	0	0	0	0	0	0	0	0	22	0	1	0	0	0	80181	1	6	6	0	25	480070	80010	320240	80000	80010	320304	80000	480049	480007	8640020	0	80038	0	80057	80057	20	0	3	42	480010	20	80000	320000	20	160000	320000	80057	80057	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	18	80014	0	0	14	80014	6	1	14	18	0	5019	1	17	1	1	80054	0	80000	10	11	80000	320000	80010	80058	80058	80058	80058	80058
400024	80197	620	0	0	0	0	0	0	0	1	20	0	1	0	0	0	80042	1	6	6	0	25	480070	80010	320060	80000	80010	320000	80000	480049	480011	8640020	0	80038	0	80057	80057	0	0	3	39	480010	20	80000	320000	20	160000	320000	80057	80042	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80014	1	0	14	80013	6	1	14	18	0	5019	1	17	1	2	80054	1	80000	10	10	80000	320000	80010	80058	80058	80058	80058	80058
400024	80057	620	0	0	0	0	0	0	0	0	32	0	0	0	0	0	80042	1	6	6	0	25	480070	80010	320060	80000	80010	320000	80000	480049	480011	8640020	0	80038	0	80057	80045	0	0	3	39	480010	20	80000	327004	22	164476	330240	80451	80057	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	18	80014	0	0	13	80014	6	1	13	18	0	5019	1	17	1	1	80054	1	80000	10	10	80000	320000	80010	80058	80058	80058	80058	80058
400024	80060	620	0	0	0	0	0	0	0	0	20	0	1	0	0	0	80042	1	6	6	0	25	480070	80010	320060	80000	80010	320000	80080	480049	480012	8640020	0	80038	0	80057	80057	0	0	3	39	480010	20	80000	320000	20	160000	320000	80057	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80000	0	0	14	80013	6	1	14	18	0	5019	1	17	1	1	80054	1	80000	13	10	80000	320000	80010	80058	80058	80058	80058	80059
400024	80057	620	0	0	0	0	1	1	1	0	20	0	0	0	1	0	80042	1	6	6	0	25	480070	80010	320060	80000	80010	320000	80000	480049	480007	8640020	0	80038	0	80057	80057	0	0	25	39	480010	20	80000	320000	20	160000	320000	80057	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80013	0	0	13	80013	6	1	14	18	0	5019	1	17	1	1	80054	0	80000	10	10	80000	320000	80010	80058	80058	80058	80059	80058
400024	80057	621	0	0	0	0	0	0	0	0	20	0	0	0	1	0	80042	1	6	6	0	25	480082	80010	320072	80000	80010	320000	80000	480049	480011	8640020	0	80038	0	80057	80057	0	0	3	39	480010	20	80000	320000	20	160000	320000	80057	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80014	1	0	13	80013	6	1	14	18	0	5019	1	17	1	1	80054	1	80000	10	10	80000	320000	80010	80058	80058	80058	80059	80058
400024	80042	620	0	0	0	0	1	1	0	0	20	0	0	0	1	0	80027	1	6	6	0	62	480070	80010	320060	80000	80010	320000	80000	480049	480007	8640020	0	80038	0	80057	80057	0	0	3	39	480010	20	80000	320000	20	160150	320000	80057	80057	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80014	0	0	14	80013	6	1	14	18	0	5019	1	17	1	1	80054	1	80000	0	13	80000	320000	80010	80348	80058	80058	80058	80058
400024	80057	620	0	0	0	0	1	0	0	0	20	0	0	0	1	0	80042	1	6	6	0	25	480070	80091	320060	80000	80010	320000	80000	480049	480007	8640020	0	80038	0	80057	80057	0	0	3	42	480010	20	80000	320000	20	160000	320000	80057	80196	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80000	1	0	13	80014	6	1	14	18	0	5019	1	17	1	1	80054	1	80075	10	10	80000	320000	80010	80061	80061	80058	80197	80058
400024	80058	621	0	0	1	0	1	0	2	2	152	88	0	0	0	0	80796	1	6	6	22	102	480480	80172	320320	80080	80010	320000	80080	480526	483381	7735888	0	80276	0	80348	80195	40	275	414	1134	480970	20	80076	320644	20	160320	320320	80350	80349	2	1	80021	10	9	10	10	80000	80000	0	10	80069	0	18	80092	0	0	2654	80169	6	1	14	18	0	5049	1	25	2	1	82271	0	81285	10	10	80000	320000	80010	80351	80203	80199	80197	80504

LD4R (post-index, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations