Firestorm: LD4R (post-index, 8H) measurements

Code:

  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 6.012

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
65005	29395	236	22	0	0	12	0	0	0	0	15	0	0	0	0	4709	28778	0	0	0	16847	6012	1000	4012	1000	1000	4000	1000	5000	5000	47587	16	0	0	22974	29220	29320	3	10	6000	1000	4000	2000	4000	29237	29263	1	1	61001	1000	1000	0	1000	0	2	1001	0	0	0	0	1000	2	1	3	0	0	13175	9322	6945	3120	7	37	20295	3339	3810	5	36	36	28592	1000	15913	13024	14404	1000	4000	1000	29439	29357	29312	29430	29311
65004	29358	235	14	0	0	12	0	0	0	0	2	0	0	0	0	4664	28882	0	0	0	17116	6008	1000	4008	1000	1000	4000	1000	5000	5000	47530	3	0	0	22966	29108	29276	3	10	6000	1000	4000	2000	4000	29201	29292	1	1	61001	1000	1000	0	1000	0	2	1000	0	0	0	0	1000	2	0	2	0	0	13332	9477	6978	3103	14	41	20380	3288	3811	7	47	37	28562	1000	16060	13220	14089	1000	4000	1000	29381	29329	29350	29265	29343
65004	29316	236	17	0	0	17	0	0	0	0	2	0	1	0	0	4699	28977	0	0	0	17124	6008	1000	4008	1000	1000	4000	1000	5000	5000	47548	11	0	0	22926	29188	29281	3	10	6000	1000	4000	2000	4000	29261	29071	1	1	61001	1000	1000	0	1000	0	2	1000	0	1	0	3	1000	2	0	2	0	0	13344	9529	6927	3102	8	34	20199	3257	3815	5	37	35	28654	1000	16273	12908	14246	1000	4000	1000	29453	29335	29317	29431	29250
65004	29351	235	13	0	0	17	0	0	0	0	2	0	0	0	0	4685	29027	0	0	0	17121	6008	1000	4008	1000	1000	4000	1000	5000	5000	47536	3	0	0	23014	29222	29359	3	10	6000	1000	4000	2000	4000	29350	29100	1	1	61001	1000	1000	0	1000	0	3	1001	0	0	0	0	1000	2	0	3	0	0	13125	9330	6880	3092	5	36	20228	3271	3804	4	42	34	28573	1000	16287	13330	14211	1000	4000	1000	29385	29444	29458	29273	29457
65004	29387	236	13	0	0	15	0	0	0	0	2	0	1	0	0	4676	28915	0	0	1	17073	6012	1000	4008	1000	1000	4000	1000	5000	5000	47520	3	0	0	22981	29291	29386	3	10	6000	1000	4000	2000	4004	29300	29217	2	1	61001	1000	1000	0	1000	0	2	1000	0	0	0	0	1001	2	0	3	0	0	13123	9471	7016	3200	9	34	20451	3210	3808	6	39	34	28648	1000	16106	13365	14276	1000	4000	1000	29326	29263	29370	29360	29306
65004	29441	236	9	0	0	12	0	0	0	0	2	0	0	0	0	4727	28853	0	0	1	17136	6008	1000	4012	1000	1000	4000	1000	5000	5000	47573	9	0	0	22922	29144	29356	3	10	6000	1000	4000	2000	4000	29226	29193	1	1	61001	1000	1000	1	1000	0	2	1000	0	0	0	0	1001	2	0	3	0	0	13315	9358	6906	3154	8	38	20319	3278	3811	8	41	44	28501	1000	16331	13129	14305	1000	4000	1000	29420	29352	29345	29590	29401
65004	29290	237	15	0	0	15	0	0	0	0	3	0	0	0	0	4735	28841	0	0	0	17058	6008	1000	4008	1000	1000	4000	1000	5000	5000	47520	8	1	0	22919	29255	29343	3	10	6000	1000	4000	2000	4000	29233	29185	1	1	61001	1000	1000	0	1000	0	2	1000	0	0	0	1	1001	2	1	2	0	0	13262	9420	6941	3168	5	33	20338	3297	3807	7	36	37	28592	1000	16174	13334	14260	1000	4000	1000	29272	29269	29454	29354	29250
65004	29401	236	16	0	0	16	0	0	0	0	2	0	0	0	0	4656	28813	0	0	1	17078	6012	1000	4008	1000	1000	4000	1000	5000	5000	47532	12	0	0	22954	29181	29335	3	10	6018	1000	4000	2000	4000	29355	29283	1	1	61001	1000	1000	0	1000	0	3	1000	0	0	0	3	1000	2	0	2	0	0	13241	9337	6930	3147	5	34	20255	3232	3810	6	35	41	28635	1000	16289	13201	14237	1000	4000	1000	29362	29384	29264	29326	29328
65004	29237	235	11	0	0	15	0	0	0	0	29	0	1	0	0	4682	28889	0	1	0	16987	6012	1000	4012	1001	1000	4000	1000	5000	5000	47502	8	0	0	22943	29106	29390	3	10	6000	1000	4000	2000	4000	29204	29231	1	1	61001	1000	1000	0	1000	0	3	1000	0	1	0	1	1000	2	0	2	0	0	13080	9450	6960	3159	2	37	20278	3338	3807	13	41	41	28640	1000	15933	13018	14387	1000	4000	1000	29383	29354	29435	29413	29362
65004	29269	235	12	0	0	16	0	0	0	0	3	0	0	0	0	4654	28905	0	0	0	16948	6008	1000	4008	1000	1000	4000	1000	5000	5000	47583	2	0	0	22943	29270	29398	3	10	6000	1000	4000	2000	4000	29296	29217	1	1	61001	1000	1000	0	1000	0	2	1000	0	1	0	0	1000	2	0	2	0	0	13155	9385	6977	3155	8	29	20236	3347	3816	5	29	33	28578	1000	16442	12930	14332	1000	4000	1000	29480	29424	29390	29377	29396

Count: 8

Code:

  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	80069	621	1	0	0	0	0	0	1	0	0	0	35	0	0	0	0	80051	1	6	6	3	25	480160	80100	320072	80000	80100	320000	80000	480499	480048	8640020	0	80041	80048	80066	0	0	3	48	480100	200	80000	320000	200	160000	320000	80060	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80006	0	0	0	17	80023	6	1	0	27	0	0	5109	3	17	3	3	80057	1	80000	0	0	80000	320000	80100	80067	80067	80048	80061	80067
400204	80060	621	0	0	1	0	0	0	0	0	0	0	5	0	0	0	0	80045	1	6	6	0	25	480172	80100	320072	80000	80100	320000	80000	480499	480041	8640020	1	80041	80060	80060	0	0	3	42	480100	200	80000	320000	200	160000	320000	80060	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80016	0	1	0	0	80000	6	1	13	27	0	0	5109	3	17	3	3	80054	1	80000	13	10	80000	320000	80100	80058	80067	80067	80061	80043
400204	80060	620	0	0	1	0	0	0	0	0	0	0	34	0	0	0	0	80051	1	6	0	0	25	480172	80100	320072	80000	80100	320000	80000	480499	480018	8640020	0	80028	80042	80060	0	0	3	43	480100	200	80000	320000	200	160000	320000	80060	80060	1	1	80201	100	99	100	100	80000	80000	0	100	80006	6	0	80015	0	0	1	19	80023	6	1	15	27	0	0	5109	3	17	3	2	80063	1	80000	13	0	80000	320000	80100	80043	80061	80067	80070	80061
400204	80060	621	0	0	0	0	0	0	1	1	0	0	33	0	0	0	0	80045	1	6	6	0	25	480172	80100	320072	80000	80100	320000	80000	480499	480509	8640020	0	80026	80060	80060	0	0	3	24	480100	200	80000	320000	200	160000	320000	80042	80042	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80000	0	0	0	19	80015	0	0	16	20	0	0	5109	4	17	5	4	80060	0	80000	13	10	80000	320000	80100	80061	80061	80061	80061	80043
400204	80057	621	0	0	0	0	0	0	0	0	0	0	22	0	0	0	0	80032	0	6	0	0	25	480172	80100	320072	80000	80100	320000	80000	480499	480033	8640020	0	80038	80042	80060	0	0	3	25	480100	200	80000	320000	200	160000	320000	80042	80045	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80000	0	0	0	3	80013	6	0	14	20	0	0	5109	3	17	3	3	80057	1	80000	0	0	80000	320000	80100	80061	80058	80061	80061	80058
400204	80060	620	0	0	0	0	0	0	0	0	0	0	22	0	0	0	0	80027	1	6	6	0	25	480172	80100	320000	80000	80100	320000	80000	480499	480090	8640020	0	80026	80060	80048	0	0	3	24	480100	200	80000	320000	200	160000	320000	80066	80066	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	27	80014	0	0	0	32	80000	6	1	29	20	0	1	5109	3	17	3	3	80057	1	80000	13	13	80000	320000	80100	80061	80061	80061	80043	80061
400204	80042	620	0	0	0	0	0	0	0	0	0	0	46	0	1	0	0	80045	1	0	6	0	25	480172	80100	320048	80000	80100	320000	80000	480499	480047	10880304	1	80041	80060	80060	0	0	3	42	480100	200	80000	320000	200	160000	320000	80042	80066	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80016	0	0	0	32	80014	0	1	14	0	0	0	5109	2	17	3	2	80057	0	80000	13	10	80000	320000	80100	80061	80043	80061	80043	80061
400204	80045	622	1	0	0	0	0	0	0	1	0	0	35	0	0	0	0	80027	0	0	6	0	25	480172	80100	320048	80000	80100	320000	80000	480499	480733	8640020	0	80023	80060	80057	0	0	3	42	480100	200	80000	320000	200	160000	320000	80060	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80016	0	0	0	0	80015	6	1	15	0	0	0	5109	3	17	3	2	80054	0	80000	13	11	80000	320000	80100	80061	80061	80061	80058	80061
400204	80060	621	0	0	0	0	0	0	0	0	0	0	21	0	0	0	0	80027	1	6	0	0	25	480172	80100	320072	80000	80100	320000	80000	480499	480603	8640024	0	80041	80045	80060	0	0	3	42	480100	200	80000	320000	200	160000	320000	80060	80060	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80016	0	0	0	16	80014	6	1	0	20	0	0	5109	3	17	4	3	80057	1	80000	0	13	80000	320000	80100	80061	80061	80061	80061	80061
400204	80060	620	0	0	0	0	0	0	0	1	0	0	40	0	0	0	0	80027	0	6	6	0	25	480172	80100	320000	80000	80100	320000	80000	480499	480761	8640020	0	80041	80060	80042	0	0	3	42	480100	200	80000	320000	200	160000	320000	80062	80057	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	18	80000	0	0	0	0	80016	6	0	14	0	6	1	5109	3	17	4	2	80063	1	80000	13	15	80000	320000	80100	80061	80048	80196	80352	80198

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	80058	621	0	0	0	0	1	0	0	30	0	0	0	80033	1	6	6	0	25	480058	80010	320056	80000	80010	320000	80000	480049	480020	10560016	0	80043	80062	80062	0	0	3	68	480010	20	80000	320000	20	160000	320000	80064	80051	1	1	80021	10	9	10	10	80000	80000	10	80005	6	0	80088	0	0	0	24	80018	0	1	24	23	6	0	0	5019	10	17	3	3	80059	1	80000	9	9	80000	320000	80010	80063	80063	80063	80063	80063
400024	80062	620	1	0	0	0	0	0	0	41	0	0	0	80047	0	6	6	0	25	480466	80010	320056	80000	80010	320000	80000	480049	480023	5440024	0	80043	80062	80062	0	0	3	44	480010	20	80000	320000	20	160000	320000	80062	83893	28	1	80021	10	9	10	10	80000	80000	10	80000	0	17	80000	0	0	0	13	80000	6	1	0	17	0	0	0	5019	9	17	3	3	80054	0	80000	9	6	80000	320000	80010	80058	80058	80058	80058	80058
400024	80057	620	0	0	0	0	0	0	0	0	0	0	0	80042	1	6	6	0	25	480066	80010	320056	80000	80010	320000	80000	480049	480005	4159992	0	80038	80057	80057	0	0	3	39	480010	20	80000	320000	20	160000	320000	80057	80660	1	1	80021	10	9	10	10	80000	80000	10	80000	0	13	80012	0	1	0	18	80013	6	1	13	0	0	0	0	5019	8	17	3	3	80054	1	80000	9	6	80000	320000	80010	80058	80058	80058	80058	80058
400024	80057	620	0	0	0	0	0	0	0	19	0	0	0	80042	1	6	6	0	25	480066	80010	320060	80000	80010	320000	80000	480497	480011	7680020	0	80038	80057	80042	0	0	3	24	480490	20	80000	320000	20	160000	320000	80057	80057	1	1	80021	10	9	10	10	80000	80000	10	80000	0	13	80013	0	1	0	895	80000	6	0	10	17	0	0	0	5019	12	17	3	3	80039	1	80000	9	9	80000	320000	80010	80058	80058	80055	80058	80043
400024	80057	620	0	0	0	0	0	0	0	0	0	0	0	80039	1	0	6	0	25	480066	80010	320056	80000	80010	320000	80000	480049	480005	4159992	0	80038	80057	80057	0	0	3	36	480010	20	80000	320000	20	160000	320000	80057	80057	1	1	80021	10	9	10	10	80000	80000	10	80000	0	13	80013	0	0	0	13	80012	6	1	9	17	0	0	0	5019	7	17	3	3	80054	1	80000	9	6	80000	320000	80010	80058	80058	80058	80058	80058
400024	80057	620	0	0	0	0	0	0	0	28	0	0	0	80027	1	6	6	0	25	480066	80010	320068	80000	80010	320000	80000	480049	480013	4798864	0	80035	80057	80057	0	0	3	39	480010	20	80000	320000	20	160000	320000	80057	80054	1	1	80021	10	9	10	10	80000	80000	10	80000	0	13	80013	0	0	0	3	80073	0	1	13	17	0	0	0	5019	5	17	3	3	80054	1	80000	9	9	80000	320000	80010	80043	80058	80058	80058	80061
400024	80195	624	0	0	0	0	0	0	0	31	0	0	0	80042	0	6	6	0	25	480066	80010	320000	80000	80010	320000	80000	480049	480014	7680020	0	80038	80057	80057	0	0	3	39	480010	20	80000	320000	20	160000	320000	80057	80057	1	1	80021	10	9	10	10	80000	80000	10	80000	0	13	80013	0	0	0	15	80013	6	1	9	17	0	0	0	5019	13	17	3	3	80054	1	80000	9	6	80000	320000	80010	80058	80058	80058	80058	80055
400024	80042	620	0	1	0	0	0	0	0	19	0	0	0	80042	0	6	6	0	25	480066	80010	320056	80000	80010	320000	80000	480049	480007	8640020	0	80038	80057	80057	0	0	3	39	480010	20	80000	320000	20	160000	320000	80504	80057	1	1	80021	10	9	10	10	80000	80000	10	80000	0	13	80091	0	0	0	16	80013	6	1	10	17	0	0	0	5019	8	17	3	3	80051	1	80000	9	9	80000	320000	80010	80058	80058	80159	80058	80058
400024	80057	620	0	0	0	0	0	0	0	19	0	0	0	80180	1	6	6	0	25	480066	80010	320056	80000	80091	320000	80000	480049	480013	8639992	0	80038	80192	80057	0	0	34	39	480010	20	80000	320000	20	160000	320000	80054	80057	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	80012	0	0	0	0	80012	6	1	9	17	0	0	0	5019	8	17	3	3	80054	0	80000	9	6	80000	320000	80010	80058	80058	80058	80058	80058
400024	80057	621	0	0	0	0	0	0	0	18	0	0	0	80042	1	6	6	0	25	480066	80010	320056	80000	80010	320000	80000	480049	480011	4201932	0	80038	80057	80045	0	0	3	36	480010	20	80000	320000	20	160000	320000	80057	80057	1	1	80021	10	9	10	10	80000	80000	10	80000	0	18	80013	0	1	0	19	80012	6	1	9	17	0	0	0	5019	8	17	3	3	80054	0	80000	9	6	80000	320000	80010	80058	80058	80055	80055	80058

LD4R (post-index, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations