Firestorm: LD4 (multiple, 16B) measurements

Code:

  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 12.022

Integer unit issues: 0.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.022

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
72005	29369	219	1	17	1	14	0	0	0	36	0	0	0	0	4741	29103	0	0	0	15432	12022	8022	4000	8000	4000	20335	98391	2	0	0	24719	0	29189	29307	3	10	12000	4000	8000	4000	20000	29250	29222	1	1	61001	1000	1000	0	4005	5	8	4006	0	1	1	6	4000	6	1	6	8	4	0	12822	9303	6843	3050	9	47	19288	3077	3824	7	46	41	28486	16293	12972	13589	4000	8000	29354	29251	29260	29347	29303
72004	29329	219	1	21	1	16	1	0	0	264	0	1	0	0	4528	29135	0	0	0	15383	12022	8022	4000	8000	4000	20347	98443	1	0	5	24769	0	29191	29321	3	10	12000	4000	8000	4000	20000	29220	29308	1	1	61001	1000	1000	0	4005	5	12	4007	0	0	2	6	4002	6	1	6	8	4	0	12822	9160	6821	3040	6	41	19329	3103	3821	9	46	46	28633	16459	13092	13492	4000	8000	29321	29362	29342	29344	29302
72004	29357	220	1	12	0	14	1	0	0	297	0	1	0	0	4597	29061	0	0	0	15349	12022	8008	4000	8000	4000	20311	98440	1	0	5	24791	0	29383	29354	3	10	12000	4000	8000	4000	20000	29208	29231	1	1	61001	1000	1000	1	4006	5	0	4007	0	1	0	4	4002	6	0	6	0	4	1	12922	9058	6808	3007	8	44	19245	3032	3819	14	47	42	28539	16368	13048	13719	4000	8000	29372	29289	29325	29414	29382
72004	29306	219	1	13	1	14	1	0	0	321	0	1	0	0	4500	29084	0	0	0	15363	12022	8022	4000	8000	4000	20330	98431	0	0	0	24741	0	29147	29293	3	10	12000	4000	8000	4000	20000	29251	29312	1	1	61001	1000	1000	0	4005	5	8	4007	0	0	1	4	4002	6	0	6	8	4	1	12889	9111	6842	3026	6	46	19364	3089	3820	18	44	49	28517	16475	13146	13599	4000	8000	29411	29352	29282	29322	29286
72004	29271	219	1	15	1	13	1	0	0	339	0	1	0	0	4507	29107	0	4	0	15342	12022	8008	4000	8000	4000	20343	98412	0	0	0	24797	0	29179	29254	3	10	12000	4000	8000	4000	20000	29257	29258	1	1	61001	1000	1000	0	4004	5	8	4008	0	0	2	6	4000	0	0	6	8	4	2	12955	9072	6820	3036	9	47	19389	3146	3821	18	47	45	28522	16423	13031	13681	4000	8000	29249	29275	29327	29291	29304
72004	29266	220	1	14	1	12	1	0	0	334	0	0	0	0	4517	29097	0	0	0	15360	12022	8032	4000	8000	4000	20323	98528	3	0	0	24833	0	29212	29275	3	10	12000	4000	8000	4000	20000	29308	29262	1	1	61001	1000	1000	0	4005	6	8	4008	0	0	1	6	4006	6	1	6	12	4	1	13236	9160	6856	3038	9	46	19278	3106	3824	16	46	50	28581	16508	13150	13541	4000	8000	29286	29284	29347	29319	29317
72004	29396	219	1	11	1	12	1	0	0	12	0	0	0	0	4520	29064	0	0	0	15291	12008	8022	4000	8000	4000	20338	98471	2	1	5	24774	0	29225	29340	3	10	12000	4000	8000	4000	20000	29181	29282	1	1	61001	1000	1000	0	4006	5	8	4008	0	0	1	6	4002	6	1	6	8	4	2	12837	9349	6949	3077	6	40	19401	3079	3820	14	47	48	28521	16363	13010	13536	4000	8000	29293	29323	29291	29346	29266
72004	29323	219	1	14	1	13	1	0	0	324	0	1	0	0	4478	29047	0	0	0	15364	12022	8020	4000	8000	4000	20343	98396	1	0	0	24793	0	29176	29329	3	10	12000	4000	8000	4000	20000	29262	29201	1	1	61001	1000	1000	0	4006	5	8	4007	0	0	1	6	4008	6	0	6	0	4	2	12827	9142	6822	3037	9	49	19373	3068	3823	13	39	42	28474	16488	13155	13784	4000	8000	29403	29346	29383	29347	29283
72004	29264	219	1	14	1	17	0	0	0	279	0	1	0	0	4564	29103	0	0	0	15280	12022	8022	4000	8000	4000	20341	98605	1	0	0	24756	0	29204	29303	3	10	12000	4000	8000	4000	20000	29209	29200	1	1	61001	1000	1000	0	4006	5	12	4013	0	1	1	12	4008	0	1	6	8	4	1	12806	9140	6847	3048	8	45	19308	3073	3821	8	44	42	28508	16239	13076	13609	4000	8000	29265	29343	29318	29328	29343
72004	29301	219	1	10	1	14	1	0	0	281	0	1	0	0	4506	29106	0	0	0	15277	12032	8022	4000	8000	4000	20337	98155	0	0	0	24801	0	29225	29346	3	10	12000	4000	8000	4000	20000	29235	29260	1	1	61001	1000	1000	1	4006	6	8	4008	0	0	2	6	4002	6	1	4	8	4	2	12902	9196	6830	3023	7	44	19300	3108	3819	18	41	41	28564	16414	13140	13560	4000	8000	29267	29284	29262	29328	29287

Count: 8

Code:

  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	0e	0f	18	19	1e	1f	22	23	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960205	160073	1199	0	0	0	0	0	245	352	1	0	160044	3	12	12	25	960156	100	640056	320000	100	640000	320000	500	1680408	18560012	1	160024	160063	160059	0	0	3	41	960100	200	320000	640000	200	320000	1600000	160059	160059	1	1	80201	100	99	100	100	80000	80000	1	100	320000	35	0	320032	0	6	0	0	320032	6	1	32	35	0	0	5109	2	17	4	1	160476	0	10	0	1	320000	640000	100	161213	161072	160044	160060	160060
960204	160059	1204	0	1	0	0	0	43	686	1	0	160574	3	12	12	59	960156	100	640000	320000	100	640000	320000	500	1680458	18560012	1	160040	160059	160748	0	0	21	41	960908	200	320136	641604	200	320000	1600000	160059	160744	1	1	80201	100	99	100	100	80000	80000	0	100	320000	35	0	320032	0	0	0	35	320000	6	0	32	35	0	0	5109	1	17	1	1	160040	0	10	10	1	320000	640000	100	160061	160060	160060	160060	160060
960204	160059	1199	0	0	1	1	0	38	0	0	0	160044	0	0	12	25	960156	100	640000	320000	100	640000	320000	500	1680458	8160000	1	160040	160068	160059	0	0	3	41	960100	200	320000	640000	200	320000	1600000	160059	160043	1	1	80201	100	99	100	100	80000	80000	0	100	320000	35	0	320000	0	0	0	32	320032	6	1	0	0	0	0	5109	1	17	1	1	160056	0	10	10	0	320000	640000	100	160060	160060	160060	160060	160060
960204	160059	1199	0	0	0	0	0	38	0	1	0	160028	3	12	12	25	960156	100	640540	320000	100	640000	320000	500	1680415	18560012	1	160041	160059	160059	0	0	3	25	960100	200	320000	640000	200	320000	1600000	160059	160059	1	1	80201	100	99	100	100	80000	80000	1	100	320000	35	0	320000	0	0	0	9	320032	6	1	32	0	0	0	5109	1	17	1	1	160040	0	0	0	1	320000	640000	100	160060	160060	160060	160060	160044
960204	160059	1199	0	1	1	0	0	38	0	0	0	160044	3	12	12	57	960156	100	640056	320000	100	640000	320000	500	1680415	18560012	1	160040	160059	160059	0	0	3	41	960100	200	320000	640000	200	320000	1600000	160191	160043	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	0	320032	0	0	0	0	320032	0	0	32	35	0	0	5109	1	17	1	1	160040	0	10	10	1	320000	640000	100	160062	160060	160060	160060	160060
960204	160043	1199	0	0	0	0	0	38	0	1	0	160028	3	12	12	25	960156	100	640056	320000	100	640000	320000	500	1680001	8160000	1	160040	160059	160059	0	0	3	41	960100	200	320000	640000	200	320000	1600000	160059	160059	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	0	320032	0	5	0	32	320032	6	0	32	0	0	0	5109	1	17	2	1	160056	0	0	0	0	320000	640000	100	160060	160044	160060	160060	160044
960204	160045	1199	0	0	0	0	0	38	0	0	1	160028	3	12	12	25	960100	100	640056	320130	100	640000	320000	500	1680001	18560012	1	160040	160059	160059	0	0	3	41	960100	200	320000	640000	200	320000	1600000	160059	160043	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	0	320000	0	0	0	32	320000	6	1	0	35	0	0	5109	1	17	1	1	160056	0	10	10	1	320000	640000	100	160060	160060	160060	160060	160044
960204	160043	1199	0	0	0	0	0	38	0	0	1	160044	3	0	12	25	960156	100	640056	320000	100	640000	320000	500	1680001	18560020	1	160040	160062	160043	0	0	3	25	960100	200	320000	640000	200	320000	1600000	160059	160043	1	1	80201	100	99	100	100	80000	80000	0	100	320000	35	0	320032	0	0	0	35	320032	0	1	32	0	0	0	5109	1	17	1	1	160040	0	10	10	1	320000	640000	100	160045	160060	160060	160060	160044
960204	160059	1198	0	1	1	0	0	38	0	0	1	160028	0	0	12	25	960100	100	640056	320000	100	640000	320000	500	1680415	8160000	1	160024	160059	160059	0	0	3	41	960100	200	320000	640000	200	320000	1600000	160043	160059	1	1	80201	100	99	100	100	80000	80000	0	100	320000	35	0	320032	0	0	0	32	320032	0	1	0	35	0	0	5109	1	17	1	1	160056	0	0	10	1	320000	640000	100	160060	160060	160060	160060	160060
960204	160059	1199	0	0	0	0	0	38	0	0	1	160044	3	12	12	25	960156	100	640056	320000	100	640000	320000	500	1683725	18560012	1	160040	160043	160059	0	0	3	25	960100	200	320000	640000	200	320000	1600000	160059	160059	1	1	80201	100	99	100	100	80000	80000	0	100	320000	35	0	320032	0	0	0	0	320032	6	1	32	35	0	0	5109	1	17	1	1	160056	0	10	10	1	320000	640000	100	160060	160060	160060	160063	160060

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960025	160074	1199	1	0	0	2	0	0	0	0	73	0	0	0	1	160059	16	4	18	10	1	25	960074	10	640072	320000	10	640000	320000	50	1681512	21761472	0	160037	0	160056	160074	0	0	3	56	960010	20	320000	640000	20	320000	1600000	160074	160074	1	1	80021	10	9	10	10	80000	80000	0	10	320013	14	58	0	320066	0	0	0	67	320024	6	1	67	44	13	1	5019	5	17	7	5	160073	0	10	10	5	320000	640000	10	160057	160075	160075	160075	160075
960024	160056	1199	1	0	0	0	0	0	0	0	38	0	0	0	1	160059	25	4	18	0	1	25	960050	10	640072	320000	10	640000	320000	50	1680370	21761472	0	160055	0	160074	160074	8	29	3	56	960010	20	320000	640000	20	320000	1600000	160057	160074	1	1	80021	10	9	10	10	80000	80000	0	10	320014	14	58	0	320037	1	0	1	38	320024	6	1	67	0	13	1	5019	5	17	7	5	160053	0	10	10	3	320000	640000	10	160075	160075	160072	160058	160075
960024	160074	1199	1	0	0	0	0	0	0	0	73	0	0	0	1	160059	16	0	18	0	0	25	960050	10	640040	320000	10	640000	320000	50	1681523	16640032	0	160055	0	160057	160074	8	0	3	56	960010	20	320000	640000	20	320000	1600000	160074	160057	1	1	80021	10	9	10	10	80000	80000	0	10	320014	14	0	0	320067	1	9	0	67	320054	6	1	38	0	13	0	5019	5	17	7	5	160071	0	10	0	0	320000	640000	10	160075	160075	160075	160075	160075
960024	160074	1199	1	0	0	1	0	0	0	0	73	0	0	0	1	160150	16	0	0	0	1	25	960050	10	640076	320000	10	640000	320000	50	1681512	21761472	1	160057	0	160055	160056	9	0	3	37	960010	20	320000	640000	20	320000	1600000	160074	160076	1	1	80021	10	9	10	10	80000	80000	0	10	320142	13	58	0	320067	0	0	1	38	320054	6	1	38	44	13	1	5019	7	17	7	5	160071	0	10	10	3	320000	640000	10	160058	160057	160075	160058	160075
960024	160055	1198	1	0	0	2	1	0	0	0	38	0	1	0	1	160059	16	0	18	0	0	25	960050	10	640076	320000	10	640000	320000	50	1680354	16640032	1	160037	0	160074	160074	8	0	3	56	960010	20	320000	640000	20	320000	1600000	160074	160074	1	1	80021	10	9	10	10	80000	80000	0	10	320013	13	0	0	320067	0	0	1	68	320025	6	0	38	44	13	1	5019	5	17	7	5	160071	0	10	10	3	320000	640000	10	160075	160075	160075	160057	160075
960024	160057	1199	1	0	0	1	0	1	0	0	682	0	0	0	1	160059	16	4	18	10	1	25	960046	10	640036	320000	10	640000	320000	50	1681512	21761472	1	160055	0	160057	160074	8	0	3	56	960010	20	320000	640000	20	320000	1600000	160074	160057	1	1	80021	10	9	10	10	80000	80000	0	10	320013	14	58	0	320038	0	0	1	67	320054	6	1	67	0	13	2	5019	4	17	5	7	160071	0	10	10	5	320000	640000	10	160075	160075	160075	160057	160058
960024	160074	1199	1	0	0	1	0	0	0	0	73	0	1	0	1	160061	16	4	18	10	1	25	960086	10	640064	320000	10	640000	320000	50	1681512	21761472	1	160055	0	160074	160074	0	0	3	56	960010	20	320000	640000	20	320000	1600000	160074	160055	1	1	80021	10	9	10	10	80000	80000	0	10	320014	14	58	0	320067	1	0	1	68	320054	6	0	67	44	13	1	5019	7	17	7	5	160071	0	0	0	0	320000	640000	10	160056	160075	160075	160075	160059
960024	160056	1199	1	0	0	1	0	0	0	0	38	0	0	0	1	160059	16	4	0	0	0	25	960086	10	640076	320000	10	640000	320000	50	1681512	21761472	1	160057	0	160055	160074	0	0	3	56	960406	20	320000	640264	20	320000	1600000	160074	160056	1	1	80021	10	9	10	10	80000	80000	0	10	320014	15	58	0	320038	3	4	0	70	320054	0	1	67	44	13	0	5019	5	17	5	7	160071	0	10	0	4	320000	640000	10	160057	160075	160075	160075	160075
960024	160074	1199	1	0	0	1	1	1	2	0	85	0	0	0	1	160041	16	0	0	0	1	25	960086	10	640300	320000	10	640000	320136	50	1680379	21761472	1	160037	0	160057	160056	8	0	3	56	960010	20	320000	640000	20	320000	1600000	160074	160057	1	1	80021	10	9	10	10	80000	80000	0	10	320013	14	58	0	320067	1	0	0	67	320024	6	0	67	43	13	1	5019	5	17	7	5	160052	0	0	10	0	320000	640000	10	160075	160058	160057	160075	160075
960024	160057	1199	1	0	0	1	1	0	0	0	38	112	1	0	1	160041	16	4	18	10	80	58	960082	10	640072	320000	10	640000	320000	50	1681516	21761620	1	160055	0	160056	160074	8	0	3	56	960010	20	320000	640000	20	320000	1600000	160076	160074	1	1	80021	10	9	10	10	80000	80000	0	10	320014	13	58	0	320068	2	0	0	67	320024	6	0	66	44	13	1	5019	5	17	5	7	160054	0	0	0	21	320000	640000	10	160075	160059	160075	160075	160058

LD4 (multiple, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations