Firestorm: LD4 (multiple, 2D) measurements

Code:

  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 12.026

Integer unit issues: 0.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.028

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
72005	29357	219	1	15	1	0	13	1	1	0	0	0	4	1	0	4552	29064	2	4	4	15333	12032	8028	4000	8000	4000	20323	98448	9	24729	29164	29290	3	10	12000	4000	8000	4000	20000	29171	29200	1	1	61001	1000	1000	0	4005	5	0	4007	0	0	1	4	4002	6	0	10	12	4	1	12708	9203	6856	3064	10	44	19229	3047	3823	12	39	44	28447	16444	12921	13573	4000	8000	29202	29352	29318	29278	29244
72004	29289	220	1	16	1	1	18	1	0	0	0	0	16	1	0	4519	29031	0	4	4	15280	12008	8028	4000	8000	4000	20311	98616	7	24811	29188	29278	3	10	12000	4000	8000	4000	20000	29250	29319	1	1	61001	1000	1000	0	4005	6	8	4007	1	0	2	10	4006	6	1	10	8	4	1	12978	9080	6903	3128	7	39	19225	3076	3827	13	41	46	28501	16341	13011	13523	4000	8000	29329	29364	29284	29320	29285
72004	29381	219	1	12	1	1	11	1	0	0	0	0	18	1	0	4600	29157	0	0	0	15308	12032	8026	4000	8000	4000	20341	98022	10	24784	29124	29281	3	10	12000	4000	8000	4000	20000	29293	29227	1	1	61001	1000	1000	0	4005	4	12	4011	1	0	1	12	4006	6	0	12	12	4	1	12935	9196	6835	3045	5	44	19291	3016	3825	10	38	40	28450	16276	12833	13333	4000	8000	29298	29268	29298	29371	29351
72004	29288	219	1	12	1	1	12	1	0	0	0	0	16	1	0	4582	29045	0	4	0	15303	12028	8028	4000	8000	4000	20310	98456	11	24720	29180	29275	3	10	12000	4000	8000	4000	20000	29233	29216	1	1	61001	1000	1000	0	4005	6	11	4012	0	0	3	4	4006	6	1	12	12	4	2	12770	9170	6853	3083	9	36	19253	3081	3824	11	35	45	28457	16213	13044	13666	4000	8000	29286	29283	29259	29322	29288
72004	29345	219	1	15	1	1	17	1	0	0	0	0	16	1	0	4568	29095	2	0	0	15212	12022	8022	4000	8000	4000	20328	98533	7	24719	29267	29333	3	10	12000	4000	8000	4000	20000	29216	29118	1	1	61001	1000	1000	0	4006	4	12	4013	0	0	0	4	4008	5	1	6	8	4	1	12760	9198	6848	3080	5	43	19341	3088	3821	10	41	40	28544	16251	12797	13595	4000	8000	29348	29289	29418	29360	29320
72004	29294	220	1	14	1	1	15	1	0	0	0	0	16	1	0	4563	29074	0	4	0	15285	12032	8022	4000	8000	4000	20325	98404	4	24763	29104	29255	3	10	12000	4000	8000	4000	20000	29193	29221	1	1	61001	1000	1000	0	4004	6	8	4011	0	0	1	6	4002	6	0	10	12	4	2	12926	9087	6818	3034	6	40	19281	3080	3820	15	41	40	28541	16387	12965	13524	4000	8000	29253	29353	29324	29330	29266
72004	29260	220	1	12	1	1	15	1	0	0	0	0	12	0	0	4530	29025	2	4	0	15254	12008	8028	4000	8000	4000	20339	98384	5	24732	29225	29288	3	10	12000	4000	8000	4000	20000	29294	29166	1	1	61001	1000	1000	0	4005	5	8	4011	0	0	1	10	4006	6	1	4	12	4	1	12934	9183	6814	3070	6	39	19273	3071	3830	11	42	40	28505	16390	13027	13497	4000	8000	29341	29349	29377	29273	29256
72004	29342	219	1	13	0	0	14	1	0	0	0	0	18	1	0	4500	29059	0	0	0	15326	12032	8026	4000	8000	4000	20329	98094	8	24480	29201	29344	3	10	12000	4000	8000	4000	20000	29224	29227	1	1	61001	1000	1000	0	4005	6	8	4007	0	0	1	4	4000	6	1	10	0	4	2	12733	9120	6805	3010	7	39	19343	3103	3825	10	37	42	28478	16539	13023	13650	4000	8000	29346	29335	29309	29276	29316
72004	29249	220	1	20	1	1	13	1	0	0	0	0	18	1	0	4565	29041	2	0	4	15317	12008	8028	4000	8000	4000	20326	98332	4	24754	29172	29260	3	10	12000	4000	8000	4000	20000	29291	29249	1	1	61001	1000	1000	0	4005	4	0	4011	0	0	2	9	4008	6	0	6	12	4	2	12867	9020	6816	3054	2	42	19320	3033	3824	16	39	37	28520	16429	12938	13546	4000	8000	29296	29313	29313	29229	29254
72004	29320	219	1	13	1	1	23	0	0	0	0	0	18	0	0	4574	29092	0	4	0	15273	12032	8028	4000	8000	4000	20323	98541	7	24813	29190	29226	3	10	12000	4000	8000	4000	20000	29253	29204	1	1	61001	1000	1000	1	4004	5	8	4012	1	0	2	6	4002	6	1	4	12	4	2	12916	9258	6864	3066	10	45	19232	3078	3828	12	40	38	28531	16366	12968	13602	4000	8000	29282	29280	29284	29272	29361

Count: 8

Code:

  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960205	160069	1199	0	0	0	0	0	0	0	38	0	1	0	0	0	160044	3	0	0	0	0	25	960156	100	640056	320000	100	640000	320000	500	1680406	18560012	1	160040	0	160064	160060	0	0	3	25	960100	200	320000	640000	200	320000	1600000	160059	160059	1	1	80201	100	99	100	100	80000	80000	0	100	320013	14	0	0	320054	0	0	13	320040	6	1	32	35	0	0	0	0	5109	1	17	1	1	160056	14	10	0	320000	640000	100	160060	160044	160044	160044	160060
960204	160059	1199	0	0	0	0	0	0	0	38	0	1	0	0	0	160044	3	0	12	0	0	25	960156	100	640056	320000	100	640000	320000	500	1680415	18560012	1	160040	0	160059	160059	0	0	3	41	960100	200	320000	640000	200	320000	1600000	160043	160059	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	35	0	320037	0	0	32	320000	6	1	32	0	0	0	0	0	5109	1	17	1	1	160056	10	10	1	320000	640000	100	160060	160044	160060	160060	160141
960204	160059	1199	0	0	0	0	0	0	0	38	0	1	0	0	0	160049	0	12	12	0	0	25	960100	100	640056	320000	100	640000	320000	500	1680458	18560012	1	160040	0	160059	160059	0	0	3	41	960100	200	320000	640000	200	320000	1600000	160059	160059	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	35	0	320032	63	0	32	320000	6	1	0	35	0	0	0	0	5109	1	17	1	1	160056	10	10	1	320000	640000	100	160060	160060	160044	160060	160044
960204	160043	1199	0	0	0	0	0	0	0	38	0	0	0	0	2	160044	0	12	0	0	0	25	960156	100	640064	320000	100	640000	320000	500	1680001	18560012	1	160045	0	160059	160059	0	0	3	41	960100	200	320144	640000	200	320000	1600000	160066	160043	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	35	0	320032	0	0	0	320032	0	1	0	35	0	0	0	0	5109	1	17	1	1	160061	10	10	1	320000	640000	100	160044	160060	160044	160065	160060
960204	160059	1198	0	0	0	0	0	0	0	38	0	0	0	0	2	160044	3	12	0	0	0	25	960156	100	640056	320000	100	640000	320000	500	1680437	18560012	1	160040	0	160059	160059	0	0	3	41	960100	200	320000	640000	200	320000	1600000	160059	160043	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	35	0	320032	0	0	32	320032	6	1	32	35	0	0	0	0	5109	1	17	1	1	160056	0	0	1	320000	640000	100	160044	160060	160060	160060	160060
960204	160047	1199	0	0	0	0	0	0	0	92	0	0	0	0	0	160028	3	12	0	0	0	25	960100	100	640056	320000	100	640000	320000	500	1680415	8160000	0	160046	0	160059	160059	0	0	3	41	960100	200	320000	640000	200	320000	1600000	160059	160043	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	35	0	320032	0	0	32	320000	6	0	0	35	0	0	0	0	5109	1	17	1	1	160040	10	0	1	320000	640000	100	160060	160060	160060	160044	160065
960204	160043	1199	0	0	0	0	0	0	0	0	0	0	0	0	0	160031	0	12	12	0	0	25	960156	100	640056	320000	100	640000	320000	500	1680881	18560012	0	160040	0	160059	160059	0	0	3	41	960100	200	320000	640000	200	320000	1600000	160059	160059	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	35	0	320032	0	0	0	320032	6	1	0	0	0	0	0	0	5109	1	17	1	1	160040	10	10	1	320000	640000	100	160060	160044	160060	160060	160060
960204	160043	1199	0	0	0	0	0	0	0	0	0	1	0	0	0	160044	3	12	12	0	0	25	960156	100	640000	320000	100	640000	320000	500	1680408	18560012	1	160040	0	160043	160059	0	0	3	25	960100	200	320000	640000	200	320000	1600000	160059	160059	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	35	0	320000	38	0	32	320032	6	1	0	0	0	0	0	0	5109	1	17	1	1	160056	10	10	1	320000	640000	100	160060	160060	160060	160060	160060
960204	160059	1198	0	0	0	0	0	0	0	38	0	0	0	0	2	160044	3	0	12	0	0	25	960156	100	640056	320000	100	640000	320000	500	1680001	18560012	1	160040	0	160059	160059	0	0	3	25	960100	200	320000	640000	200	320000	1600000	160059	160059	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	35	0	320032	0	0	3	320032	6	1	32	35	0	0	0	0	5109	1	17	1	1	160056	10	14	1	320000	640000	100	160060	160052	160047	160060	160060
960204	160043	1198	0	0	0	0	0	0	0	0	0	1	0	0	0	160044	3	12	12	0	0	25	960100	100	640064	320000	100	640000	320000	500	1680458	18560012	1	160045	0	160066	160059	0	0	3	41	960100	200	320000	640000	200	320000	1600000	160062	160043	1	1	80201	100	99	100	100	80000	80000	1	100	320000	0	35	0	320032	0	0	32	320037	6	1	32	0	0	0	0	0	5109	1	17	1	1	160056	10	10	1	320000	640000	100	160060	160060	160044	160060	160047

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960025	160072	1199	0	0	0	0	0	0	0	59	0	0	3	160054	0	6	0	5	25	960078	10	640056	320000	10	640000	320000	50	1681193	21760752	1	160050	0	160069	160069	0	0	3	46	960010	20	320000	640000	20	320000	1600000	160059	160043	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	35	0	320000	0	0	0	0	320000	6	1	0	40	0	0	0	0	5019	0	15	17	0	14	10	160056	0	10	1	320000	640000	10	160065	160044	160065	160065	160044
960024	160059	1199	0	0	0	0	0	0	0	13	1	0	3	160034	2	6	6	5	25	960066	10	640016	320000	10	640000	320000	50	1681188	21760752	1	160050	0	160049	160069	0	0	3	25	960010	20	320000	640000	20	320000	1600000	160059	160059	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	0	0	320037	0	0	0	0	320037	6	0	37	40	0	0	0	0	5019	0	17	17	0	15	16	160061	14	14	0	320000	640000	10	160065	160065	160065	160065	160065
960024	160043	1199	0	0	0	0	0	0	0	59	1	0	2	160051	3	12	12	0	25	960010	10	640064	320000	10	640000	320000	50	1680890	8160000	1	160045	0	160043	160064	0	0	3	41	960010	20	320000	640000	20	320000	1600000	160044	160059	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	35	0	320037	0	1	0	0	320032	6	0	32	40	0	0	1	0	5019	0	16	17	0	15	11	160061	0	0	1	320000	640000	10	160060	160044	160060	160153	160065
960024	160064	1199	0	0	0	0	0	0	0	59	0	0	0	160044	0	0	0	0	25	960074	10	640064	320000	10	640000	320000	50	1680881	18560012	1	160045	0	160064	160043	0	0	3	46	960010	20	320000	640000	20	320000	1600000	160043	160059	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	35	0	320037	0	0	0	37	320037	6	1	32	0	0	0	0	0	5019	0	15	17	0	17	12	160066	13	13	4	320000	640000	10	160050	160070	160050	160070	160050
960024	160069	1199	1	0	1	0	0	0	0	419	0	0	1	160034	2	0	6	5	25	960066	10	640056	320000	10	640000	320000	50	1680048	11520024	1	160050	3	160069	160049	3	0	3	46	960010	20	320000	640000	20	320000	1600000	160059	160059	1	1	80021	10	9	10	10	80000	80000	1	10	320000	0	0	0	320032	0	0	0	0	320037	6	0	32	0	0	0	0	0	5019	0	14	17	0	15	11	160056	10	0	1	320000	640000	10	160060	160065	160065	160065	160044
960024	160064	1198	0	0	0	1	0	0	0	13	1	0	2	160028	3	12	12	0	25	960074	10	640064	320000	10	640000	320000	50	1680408	18560008	1	160046	0	160064	160064	0	0	3	25	960010	20	320000	640000	20	320000	1600000	160064	160059	1	1	80022	10	9	10	10	80000	80000	0	10	320000	0	0	0	320000	0	1	0	37	320032	6	1	32	0	0	0	0	0	5019	0	15	17	0	15	15	160066	7	0	2	320000	640000	10	160050	160070	160050	160070	160070
960024	160049	1199	1	0	1	0	0	0	0	59	1	0	2	160049	3	12	12	0	25	960074	10	640056	320000	10	640000	320000	50	1680881	21760004	1	160045	0	160043	160064	0	0	3	51	960010	20	320000	640000	20	320000	1600000	160069	160069	1	1	80021	10	9	10	10	80000	80000	0	10	320013	14	44	0	320054	0	0	1	53	320040	6	1	53	44	13	0	0	0	5019	0	11	17	0	11	15	160066	32	13	2	320000	640000	10	160050	160070	160050	160070	160050
960024	160069	1199	1	0	0	0	0	0	0	59	1	0	2	160049	0	12	12	0	25	960074	10	640064	320000	10	640000	320000	50	1680413	21759996	1	160024	0	160043	160043	0	0	3	41	960010	20	320000	640000	20	320000	1600000	160064	160059	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	0	0	320000	0	0	0	37	320037	6	1	32	40	0	0	0	0	5019	0	11	17	0	12	16	160061	14	0	1	320000	640000	10	160060	160065	160044	160065	160065
960024	160064	1198	0	0	0	0	0	0	0	59	1	0	3	160054	0	6	6	0	25	960066	10	640016	320000	10	640000	320000	50	1680046	11520024	1	160050	0	160049	160049	3	0	3	51	960010	20	320000	640000	20	320000	1600000	160049	160070	2	1	80021	10	9	10	10	80000	80000	0	10	320013	14	0	0	320013	1	0	2	53	320040	0	1	53	0	13	2	0	0	5019	0	10	17	0	10	14	160040	0	10	1	320000	640000	10	160060	160065	160065	160044	160065
960024	160064	1199	0	0	0	0	0	0	0	59	1	0	0	160049	3	12	0	0	25	960074	10	640064	320000	10	640000	320000	50	1680890	18560012	0	160141	0	160064	160064	0	0	3	57	960010	20	320000	640000	20	320000	1600000	160064	160043	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	35	0	320037	0	1	0	37	320037	0	0	0	40	0	0	0	0	5019	0	16	17	0	12	16	160061	14	0	1	320000	640000	10	160065	160044	160065	160060	160065

LD4 (multiple, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations