Firestorm: LD4 (multiple, 2S) measurements

Code:

  ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.016

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.016

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	19	1e	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
66005	29391	220	1	23	2	0	17	1	0	0	0	8	1	0	4566	28790	0	2	0	16805	6016	4016	2000	4000	2000	10000	47554	4	22984	29104	29248	3	10	6000	2000	4000	2000	8000	29044	29115	1	1	61001	1000	1000	0	2004	4	4	2005	0	0	2	2002	4	2	4	2	2	12749	9292	6870	3080	5	44	20091	3084	3813	8	47	45	28409	16390	13158	14793	2000	4000	29281	29213	29294	29298	29271
66004	29329	219	1	19	1	1	20	1	0	0	0	10	1	0	4580	28837	0	0	0	16783	6004	4004	2000	4000	2000	10000	47498	3	23007	29004	29160	3	10	6000	2000	4000	2000	8000	29025	29044	1	1	61001	1000	1000	0	2003	4	0	2004	0	1	2	2002	6	4	6	2	2	12983	9208	6866	3045	9	40	19981	3133	3808	12	41	45	28424	16336	13332	14680	2000	4000	29172	29284	29276	29279	29227
66004	29304	219	1	19	1	2	17	0	0	0	0	8	1	0	4573	28733	0	0	0	16845	6016	4020	2000	4000	2000	10000	47506	7	23101	29107	29229	3	10	6000	2000	4000	2000	8000	29062	29095	1	1	61001	1000	1000	0	2002	2	6	2004	0	2	5	2000	0	4	0	2	0	12907	9299	6849	3059	6	43	20073	3117	3812	9	47	41	28423	16233	13237	14629	2000	4000	29264	29179	29191	29271	29265
66004	29192	219	1	21	1	1	18	0	0	0	0	8	0	0	4635	28792	2	0	1	16835	6004	4016	2000	4000	2000	10000	47432	7	23005	29007	29258	3	10	6000	2000	4000	2000	8000	29089	29126	1	1	61001	1000	1000	0	2002	4	4	2004	0	1	2	2002	4	2	4	2	1	12921	9041	6841	3054	9	36	20140	3088	3810	12	37	38	28404	16073	13234	14803	2000	4000	29287	29255	29332	29270	29284
66004	29270	218	1	17	1	0	16	1	0	0	0	2	1	0	4726	28826	0	2	0	16891	6016	4004	2000	4000	2000	10000	47562	8	23045	29150	29298	3	10	6000	2000	4000	2000	8000	29071	29128	1	1	61001	1000	1000	0	2004	4	6	2004	0	0	5	2002	4	4	4	2	2	12955	9265	6838	3059	7	40	20029	3104	3815	10	39	38	28378	16461	13455	14975	2000	4000	29206	29279	29260	29227	29189
66004	29223	218	1	17	1	1	16	1	0	0	0	2	1	0	4560	28721	0	0	0	16816	6004	4016	2000	4000	2000	10000	47674	2	23028	29133	29220	3	10	6000	2000	4000	2000	8000	29138	29157	1	1	61001	1000	1000	0	2002	4	6	2004	0	0	2	2002	4	4	4	2	2	12954	9220	6836	3089	6	41	19987	3088	3817	13	44	42	28418	16296	13148	14744	2000	4000	29198	29329	29235	29265	29172
66004	29284	220	1	20	1	1	19	1	0	0	0	8	0	0	4577	28773	0	1	2	16820	6012	4016	2000	4000	2000	10000	47500	5	22973	29157	29311	3	10	6000	2000	4000	2000	8000	29113	29106	1	1	61001	1000	1000	0	2005	3	6	2003	0	0	4	2002	4	4	4	2	0	12926	9194	6827	3063	6	40	20047	3119	3812	8	44	44	28309	16205	13163	14890	2000	4000	29198	29252	29318	29266	29182
66004	29240	219	1	13	1	1	13	1	0	0	0	8	0	0	4659	28842	0	0	1	16805	6020	4016	2000	4000	2000	10017	47592	3	22977	29145	29320	3	10	6000	2000	4000	2000	8000	29120	29129	1	1	61001	1000	1000	0	2003	2	6	2002	0	1	4	2002	0	4	0	2	0	13111	9053	6844	3085	7	39	20136	3082	3813	15	41	41	28420	16525	13278	14989	2000	4000	29236	29280	29246	29352	29259
66004	29285	220	1	13	0	0	15	1	0	0	0	5	0	0	4582	28811	2	0	0	16883	6016	4012	2000	4000	2000	10000	47662	8	22972	29134	29232	3	10	6000	2000	4000	2000	8000	29189	29190	1	1	61001	1000	1000	0	2002	3	4	2003	0	0	2	2002	4	2	6	2	2	12890	9163	6870	3057	8	38	19993	3085	3813	8	44	48	28368	16333	13248	14815	2000	4000	29270	29188	29240	29168	29310
66004	29174	219	1	22	1	1	16	1	0	1	0	8	0	0	4580	28789	0	0	2	16824	6004	4016	2000	4000	2000	10000	47564	3	23012	29095	29305	3	10	6000	2000	4000	2000	8000	29176	29221	1	1	61001	1000	1000	0	2004	2	0	2003	0	1	2	2002	0	4	0	2	0	12929	9173	6820	3031	5	44	20054	3086	3814	6	42	43	28397	16253	13337	14860	2000	4000	29215	29192	29269	29313	29253

Count: 8

Code:

  ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480205	80070	599	0	0	1	1	0	1	0	2	80049	2	0	12	0	25	480184	100	320076	160000	100	320000	160000	500	800042	9600000	1	80045	0	80060	80064	0	3	42	480100	200	160000	320000	200	160000	640000	80041	80059	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	0	160036	0	0	36	160039	6	0	0	0	1	5109	2	17	1	1	80057	0	0	10	0	160000	320000	100	80065	80065	80065	80042	80065
480204	80041	599	1	0	0	0	0	0	0	2	80026	2	12	12	0	25	480184	100	320000	160000	100	320000	160000	500	800853	6975964	1	80022	0	80064	80064	0	3	42	480100	200	160000	320000	200	160000	640000	80064	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	0	160032	0	0	36	160000	6	1	32	40	0	5109	1	17	1	1	80061	0	14	10	0	160000	320000	100	80065	80065	80065	80042	80065
480204	80064	600	0	0	0	0	42	1	0	0	80049	2	12	12	0	25	480184	100	320084	160000	100	320000	160000	500	804079	9600000	1	80022	0	80064	80041	0	3	46	480100	200	160000	320000	200	160000	640000	80064	80060	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	0	160032	0	0	36	160032	6	1	32	0	0	5109	1	17	1	2	80041	0	0	7	0	160000	320000	100	80042	80065	80065	80065	80065
480204	80041	600	0	0	0	0	42	0	0	2	80045	2	12	0	0	25	480184	100	320084	160000	100	320000	160000	500	800377	9600000	1	80041	0	80064	80060	0	3	46	480100	200	160000	320000	200	160000	640000	80064	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	160000	0	0	0	160032	6	0	0	0	0	5109	1	17	1	1	80061	0	0	0	0	160000	320000	100	80065	80042	80065	80065	80065
480204	80064	600	0	0	0	0	0	1	0	2	80049	0	0	12	0	25	480184	100	320084	160000	100	320000	160000	500	800377	10880000	0	80022	0	80041	80041	0	3	42	480100	200	160000	320000	200	160000	640000	80060	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	0	160032	0	0	0	160032	0	1	36	0	0	5109	1	17	1	1	80061	1	14	0	0	160000	320000	100	80065	80042	80042	80042	80065
480204	80041	599	0	0	0	1	0	0	0	2	80049	2	12	12	0	25	480184	100	320000	160000	100	320000	160000	500	800375	9600000	0	80045	0	80064	80064	0	3	46	480100	200	160000	320000	200	160000	640000	80064	80060	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	160036	0	0	36	160032	6	1	32	0	0	5109	1	17	1	1	80061	1	10	10	0	160000	320000	100	80065	80061	80065	80065	80061
480204	80064	600	0	0	1	0	0	0	0	0	80049	0	12	12	0	25	480100	100	320084	160000	100	320000	160000	500	800377	10879996	1	80022	0	80065	80152	0	3	46	480100	200	160000	320000	200	160000	640000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	0	160036	0	0	36	160000	6	1	32	40	0	5109	1	17	1	1	80061	0	14	0	0	160000	320000	100	80043	80065	80065	80065	80065
480204	80064	600	0	0	1	0	42	0	0	2	80026	0	0	0	0	25	480100	100	320084	160000	100	320000	160000	500	803798	9600000	1	80041	0	80064	80064	0	3	46	480100	200	160000	320000	200	160000	640000	80060	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	0	160036	1	0	36	160000	6	1	36	40	0	5109	1	17	2	2	80038	1	14	0	0	160000	320000	100	80042	80065	80147	80045	80042
480204	80064	599	0	0	1	0	42	0	0	0	80049	2	0	0	0	25	480184	100	320000	160000	100	320000	160000	500	801187	10880752	1	80045	0	80064	80064	0	3	23	480100	200	160000	320000	200	160000	640000	80060	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	160036	0	0	36	160039	6	1	36	40	0	5109	1	17	1	1	80038	0	10	0	0	160000	320000	100	80042	80065	80065	80065	80061
480204	80064	599	1	0	0	0	42	0	0	0	80026	0	12	0	0	25	480100	100	320000	160000	100	320000	160000	500	801187	6722740	0	80045	0	80064	80041	0	3	23	480100	200	160000	320000	200	160000	640000	80060	80060	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	160036	0	0	0	160039	6	0	32	40	0	5109	1	17	1	1	80061	0	14	10	0	160000	320000	100	80065	80065	80065	80065	80065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0e	0f	1e	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480025	80060	600	0	1	1	0	47	0	0	0	80045	0	12	0	25	480010	10	320076	160000	10	320000	160000	50	800374	3840000	80022	80060	80060	0	3	23	480010	20	160000	320000	20	160000	640000	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160000	0	137	160032	6	1	32	35	0	0	5019	3	17	3	3	80057	1	10	0	160000	320000	10	80061	80061	80061	80061	80042
480025	80060	599	0	0	0	0	38	0	0	0	80045	2	12	0	25	480086	10	320000	160000	10	320000	160000	50	800414	9600000	80041	80041	80060	0	3	42	480010	20	160000	320000	20	160000	640000	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160000	0	99	160032	0	1	0	0	0	0	5019	3	17	3	2	80057	1	10	10	160000	320000	10	80061	80061	80061	80061	80061
480024	80060	599	0	0	0	0	0	1	0	0	80045	2	0	12	25	480010	10	320076	160000	10	320000	160000	50	800103	9600000	80041	80041	80060	0	3	42	480010	20	160000	320000	20	160000	640000	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160032	0	171	160000	0	1	0	0	0	0	5019	3	17	2	3	80057	1	28	10	160000	320000	10	80061	80061	80061	80061	80061
480024	80060	599	0	0	0	0	38	1	0	0	80045	2	12	12	25	480086	10	320076	160000	10	320000	160000	50	800484	9600000	80041	80060	80041	0	3	42	480010	20	160000	320000	20	160000	640000	80060	80060	1	1	80021	10	9	10	10	80000	80000	1	10	160000	35	160032	0	12	160032	6	1	0	35	0	0	5019	3	17	4	6	80171	0	10	10	160000	320000	10	80061	80042	80061	80061	80061
480024	80072	599	0	0	0	0	38	1	0	0	80045	0	0	0	25	480010	10	320076	160000	10	320000	160000	50	800000	9600000	80022	80060	80060	0	3	42	480010	20	160000	320000	20	160000	640000	80041	80060	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160032	0	269	160032	6	1	32	35	0	0	5019	2	17	3	3	80057	1	14	10	160000	320000	10	80061	80061	80061	80061	80042
480024	80060	599	0	0	0	0	38	1	0	0	80026	0	12	12	25	480086	10	320076	160000	10	320000	160000	50	800377	9600000	80041	80060	80060	0	3	42	480010	20	160000	320000	20	160000	640000	80061	80044	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	160000	0	281	160032	0	0	32	0	0	0	5019	3	17	3	3	80057	0	10	10	160000	320000	10	80042	80042	80061	80061	80042
480024	80060	600	0	0	0	0	38	0	0	0	80045	2	12	12	25	480086	10	320076	160000	10	320000	160000	50	800431	9600000	80041	80060	80060	0	3	23	480010	20	160000	320000	20	160000	640000	80060	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	160032	0	52	160032	6	0	32	35	0	0	5019	2	17	3	3	80038	0	10	10	160000	320000	10	80061	80042	80061	80061	80061
480024	80069	600	0	0	0	0	38	0	0	0	80045	2	12	0	25	480086	10	320076	160000	10	320000	160000	50	800482	9600000	80041	80060	80060	0	3	42	480010	20	160000	320000	20	160000	640000	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	160032	0	295	160032	0	1	32	35	0	0	5019	3	17	3	3	80057	1	14	0	160000	320000	10	80042	80061	80061	80042	80061
480024	80069	599	0	0	0	0	38	0	0	0	80045	0	12	12	25	480010	10	320076	160000	10	320000	160000	50	800377	9600000	80085	80041	80060	0	3	42	480010	20	160000	320000	20	160000	640000	80041	80060	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	160032	0	51	160000	6	1	32	35	0	0	5019	3	17	3	3	80057	1	0	10	160000	320000	10	80061	80042	80061	80042	80061
480024	80067	600	0	0	0	0	38	1	0	0	80045	0	12	12	25	480094	10	320076	160000	10	320000	160000	50	800464	3840000	80041	80060	80042	0	3	23	480010	20	160000	320000	20	160000	640000	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160000	0	283	160032	6	0	32	35	0	0	5019	3	17	3	3	80057	1	0	0	160000	320000	10	80042	80061	80042	80061	80061

LD4 (multiple, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations