Firestorm: LD4 (multiple, 4H) measurements

Code:

  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.008

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	1e	22	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
66005	29300	219	20	25	0	0	0	0	0	1	4615	28874	0	0	16913	6012	4008	2000	4000	2000	10000	47518	10	23015	29126	29310	3	10	6000	2000	4000	2000	8000	29065	29083	1	1	61001	1000	1000	0	2000	6	2000	0	2	2000	4	2	4	12833	9233	6852	3070	7	75	20094	3060	3813	11	52	55	28391	16347	13342	14717	2000	4000	29274	29336	29252	29207	29244
66004	29272	219	21	18	0	0	0	0	0	1	4583	28875	1	2	16851	6012	4012	2000	4000	2000	10003	47526	3	22983	29211	29239	3	10	6000	2000	4000	2000	8000	29205	29125	1	1	61001	1000	1000	0	2000	4	2000	0	0	2000	4	0	4	12861	9244	6811	3075	11	54	20149	3078	3804	11	57	55	28470	16289	13195	14834	2000	4000	29374	29264	29306	29230	29313
66004	29288	219	24	19	0	0	0	0	5	1	4616	28795	2	0	16862	6012	4012	2000	4000	2000	10000	47522	8	22975	29139	29229	3	10	6000	2000	4000	2000	8000	29170	29092	1	1	61001	1000	1000	0	2000	4	2000	0	0	2002	4	2	4	12947	9273	6864	3042	15	49	20079	3092	3810	13	55	55	28420	15973	13402	14926	2000	4000	29334	29269	29350	29285	29256
66004	29293	220	26	19	0	0	0	0	5	1	4671	28843	0	0	16845	6008	4008	2000	4000	2000	10000	47520	5	22974	29058	29203	3	10	6000	2000	4000	2000	8000	28997	29162	1	1	61001	1000	1000	0	2000	4	2000	0	0	2000	4	0	4	13078	9305	6854	3103	9	48	20051	3083	3808	10	48	52	28457	16359	13275	14884	2000	4000	29347	29327	29284	29316	29268
66004	29340	219	22	15	0	0	0	0	6	1	4619	28876	2	0	16831	6008	4000	2000	4000	2000	10000	47532	6	23005	29076	29286	3	10	6000	2000	4000	2000	8000	29189	29061	1	1	61001	1000	1000	0	2000	4	2000	0	0	2000	4	0	4	12763	9203	6871	3030	5	47	20040	3079	3811	8	51	44	28405	16360	13249	14738	2000	4000	29234	29429	29357	29437	29206
66004	29317	220	21	17	1	0	0	0	5	0	4543	28769	0	0	16869	6008	4000	2000	4000	2000	10000	47506	4	23027	29052	29304	3	10	6000	2000	4000	2000	8000	29194	29236	1	1	61001	1000	1000	0	2000	0	2000	0	0	2000	0	0	4	12912	9265	6836	3063	10	54	20102	3087	3809	8	55	52	28473	16285	13524	14825	2000	4000	29305	29274	29265	29219	29292
66004	29252	220	22	21	0	0	0	0	0	1	4583	28826	0	0	16899	6008	4008	2000	4000	2000	10000	47528	4	23038	29099	29322	3	10	6000	2000	4000	2000	8000	29154	29182	1	1	61001	1000	1000	0	2000	4	2000	0	0	2000	4	0	6	12931	9184	6811	3028	7	53	20077	3081	3810	8	58	56	28379	16175	13173	14753	2000	4000	29370	29314	29369	29343	29342
66004	29429	219	20	24	0	0	0	0	7	1	4542	28853	0	0	16926	6008	4008	2000	4000	2000	10000	47536	4	22977	29113	29307	3	10	6000	2000	4000	2000	8000	29175	29185	1	1	61001	1000	1000	0	2000	4	2000	0	0	2000	4	0	4	12931	9202	6871	3059	13	53	20092	3100	3815	9	59	63	28466	16247	13274	14908	2000	4000	29261	29315	29267	29286	29261
66004	29292	219	23	16	0	0	0	0	5	1	4605	28850	0	2	16877	6000	4008	2000	4000	2000	10000	47496	5	23001	29091	29245	3	10	6000	2000	4000	2000	8000	29255	29194	1	1	61001	1000	1000	0	2000	4	2000	0	0	2000	4	0	4	12942	9149	6878	3055	14	51	20018	3074	3807	12	54	59	28451	16342	13375	14930	2000	4000	29266	29255	29269	29264	29322
66004	29271	220	20	23	0	0	0	0	0	1	4560	28843	0	0	16867	6008	4008	2000	4000	2000	10000	47528	4	22999	29122	29321	3	10	6000	2000	4000	2000	8000	29132	29169	1	1	61001	1000	1000	0	2000	4	2000	0	3	2000	4	0	4	13040	9188	6836	3100	9	44	20040	3114	3812	12	55	71	28480	15728	13316	14863	2000	4000	29309	29213	29245	29273	29237

Count: 8

Code:

  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	1f	22	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480205	80085	600	1	0	0	1	0	42	0	1	2	80049	2	0	12	5	25	480100	100	320072	160000	100	320000	160000	500	800377	9600000	1	80045	80064	80064	0	0	3	47	480100	200	160000	320000	200	160000	640000	80060	80060	1	1	80201	100	99	100	100	80000	80000	1	100	160000	0	0	160053	0	1	52	160000	6	1	32	35	0	5109	1	17	1	1	80038	1	14	10	0	160000	320000	100	80065	80079	80061	80042	80042
480204	80041	599	0	1	1	0	0	540	108	0	0	80049	2	12	12	0	25	480176	100	320024	160000	100	320000	160000	500	800000	3840000	1	80022	80064	80065	0	0	3	42	480322	200	160000	320000	200	160000	640000	80047	80069	1	1	80201	100	99	100	100	80000	80000	1	100	160000	0	35	160032	0	0	0	160000	6	1	32	0	0	5109	1	17	1	1	80038	1	10	10	0	160000	320000	100	80065	80066	80065	80065	80065
480204	80060	600	0	0	0	1	0	0	0	0	0	80049	0	12	12	0	25	480176	100	320084	160000	100	320000	160000	500	800853	9600000	1	80045	80064	80041	0	0	3	42	480100	200	160000	320000	200	160000	640000	80064	80041	1	1	80201	100	99	100	100	80000	80000	1	100	160000	0	0	160000	0	0	36	160036	6	1	0	0	0	5109	1	17	1	1	80061	0	14	14	0	160000	320000	100	80065	80065	80065	80065	80065
480204	80064	599	0	0	0	0	0	38	0	0	0	80049	2	12	0	0	25	480184	100	320084	160000	100	320000	160000	500	800853	9600000	0	80027	80041	80060	0	0	3	47	480100	200	160000	320000	200	160000	640000	80064	80060	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	160036	0	0	36	160036	0	0	32	0	0	5109	1	17	1	1	80061	0	13	0	4	160000	320000	100	80048	80048	80070	80048	80070
480204	80047	600	1	1	1	0	0	38	0	0	0	80049	1	12	12	0	25	480184	100	320000	160000	100	320000	160000	500	800000	9600000	1	80045	80041	80064	0	0	3	46	480100	200	160000	320000	200	160000	640000	80064	80060	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	160036	0	0	0	160036	6	0	0	35	0	5109	1	17	1	1	80061	0	0	10	0	160000	320000	100	80065	80065	80042	80065	80065
480204	80064	600	0	0	0	0	0	42	0	0	2	80049	0	12	12	0	25	480176	100	320084	160000	100	320000	160000	500	800853	3840000	1	80045	80064	80041	0	0	3	46	480100	200	160000	320000	200	160000	640000	80041	80060	1	1	80201	100	99	100	100	80000	80000	0	100	160013	0	0	160036	0	0	48	160036	6	1	32	40	0	5109	1	17	1	1	80038	0	14	14	0	160000	320000	100	80065	80066	80334	80061	80042
480204	80064	600	0	0	0	0	0	42	0	0	2	80049	0	12	12	0	25	480184	100	320084	160000	100	320000	160000	500	800853	10879996	1	80022	80064	80041	0	0	3	23	480100	200	160000	320000	200	160000	640000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160000	0	0	36	160000	6	1	36	0	0	5109	1	17	1	1	80061	0	0	14	0	160000	320000	100	80070	80061	80065	80042	80065
480204	80064	600	0	0	0	0	0	38	0	1	0	80049	2	12	12	0	25	480100	100	320084	160000	100	320000	160000	500	800853	3840000	1	80045	80064	80064	0	0	3	46	480100	200	160000	320000	200	160000	640000	80064	80060	1	1	80201	100	99	100	100	80000	80000	0	100	160015	13	35	160036	0	0	13	160000	6	1	13	43	0	5109	1	17	1	1	80038	0	0	0	0	160000	320000	100	80065	80065	80065	80065	80065
480204	80064	600	0	0	0	0	0	42	0	1	0	80029	2	12	12	0	25	480124	100	320064	160000	100	320000	160000	500	801186	10880752	1	80045	80041	80041	0	0	3	46	480100	200	160000	320000	200	160000	640000	80064	80060	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	160036	0	0	36	160036	0	0	51	0	12	5109	1	17	1	1	80038	0	0	10	0	160000	320000	100	80048	80065	80065	80042	80065
480204	80041	600	0	0	0	0	0	42	0	1	2	80049	2	0	12	0	25	480184	100	320000	160000	100	320000	160000	500	800853	3840000	1	80045	80041	80065	0	0	3	46	480100	200	160000	320000	200	160000	640000	80041	80060	1	1	80201	100	99	100	100	80000	80000	1	100	160000	0	35	160036	0	0	36	160036	6	0	32	40	0	5109	1	17	1	1	80038	0	0	14	0	160000	320000	100	80065	80065	80061	80065	80065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	19	1e	22	23	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480025	80069	600	1	0	0	0	38	1	0	80045	2	12	12	0	25	480086	10	320076	160000	10	320000	160000	50	800374	9600000	1	80041	80060	80060	3	42	480010	20	160000	320000	20	160000	640000	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160000	0	0	32	160032	6	1	0	35	0	0	5019	26	17	0	27	18	80057	1	10	10	160000	320000	10	80061	80061	80061	80061	80061
480024	80060	600	0	0	0	0	38	1	0	80045	2	12	0	0	25	480086	10	320076	160000	10	320000	160000	50	800372	9600000	1	80041	80041	80060	3	42	480010	20	160000	320000	20	160000	640000	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	160032	0	0	0	160032	6	0	32	0	0	0	5019	17	17	0	16	27	80057	1	10	10	160000	320000	10	80042	80061	80061	80061	80061
480024	80060	600	0	0	0	0	125	1	0	80045	2	12	12	0	25	480086	10	320076	160000	10	320000	160000	50	800402	9600000	1	80041	80060	80060	3	42	480010	20	160000	320000	20	160000	640000	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160032	0	0	32	160032	6	1	32	35	0	0	5019	15	17	0	28	15	80057	1	10	10	160000	320000	10	80061	80061	80061	80061	80042
480024	80060	599	0	0	0	0	38	1	0	80045	2	12	12	0	25	480086	10	320076	160000	10	320000	160000	50	800374	9280012	1	80041	80060	80060	3	42	480010	20	160000	320000	20	160000	640000	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160032	0	0	32	160032	6	1	32	35	0	0	5019	27	17	0	14	25	80057	1	10	10	160000	320000	10	80061	80061	80061	80061	80060
480024	80041	600	0	0	0	0	38	1	0	80045	2	0	12	0	25	480086	10	320076	160000	10	320000	160000	50	800377	3840000	1	80041	80060	80060	3	42	480010	20	160000	320000	20	160000	640000	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	160032	0	0	32	160032	0	1	32	35	0	0	5019	15	17	0	26	18	80038	1	10	10	160000	320000	10	80061	80061	80061	80042	80061
480024	80060	600	0	0	1	0	38	1	0	80045	2	12	12	0	25	480086	10	320076	160000	10	320000	160000	50	800000	9600000	1	80041	80060	80060	3	42	480010	20	160000	320000	20	160000	640000	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160032	0	0	32	160032	6	1	32	35	0	0	5019	26	17	0	27	30	80057	1	10	10	160000	320000	10	80061	80061	80061	80061	80061
480024	80060	600	0	0	0	0	38	1	0	80026	2	12	12	0	25	480086	10	320000	160000	10	320000	160000	50	800374	9600000	1	80041	80060	80060	3	42	480010	20	160000	320000	20	160000	640000	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160032	0	0	32	160032	0	1	32	35	0	0	5019	25	17	0	27	18	80057	1	10	10	160000	320000	10	80042	80061	80061	80061	80061
480024	80060	600	0	0	0	0	38	1	0	80045	2	0	12	0	25	480086	10	320076	160000	10	320000	160000	50	800374	9600000	1	80041	80060	80060	3	42	480010	20	160000	320000	20	160000	640000	80060	80041	1	1	80021	10	9	10	10	80000	80000	1	10	160000	35	160032	0	0	32	160032	6	1	32	35	0	0	5019	26	17	0	25	27	80057	1	10	10	160000	320000	10	80061	80147	80061	80042	80061
480024	80041	599	0	0	0	0	38	1	0	80045	2	12	12	0	25	480086	10	320076	160000	10	320000	160000	50	800377	3840000	1	80041	80060	80060	3	42	480010	20	160000	320000	20	160000	640000	80060	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160031	0	0	32	160032	6	1	32	35	0	0	5019	26	17	0	28	18	80057	1	10	10	160000	320000	10	80061	80061	80042	80061	80042
480024	80060	600	0	0	0	0	38	1	0	80045	2	12	12	0	25	480086	10	320076	160000	10	320000	160000	50	800372	9600000	1	80041	80060	80041	3	42	480010	20	160000	320000	20	160000	640000	80041	80060	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160032	0	0	0	160032	6	1	32	35	0	0	5019	28	17	0	27	28	80057	1	10	10	160000	320000	10	80061	80061	80061	80061	80042

LD4 (multiple, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations