Firestorm: LD4 (multiple, 4S) measurements

Code:

  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 12.014

Integer unit issues: 0.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.014

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	0e	0f	18	1e	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
72005	29317	220	25	19	0	0	0	0	1	0	4629	29048	2	2	0	15339	12014	8014	4000	8000	4000	20323	98250	2	24758	29190	29335	3	10	12000	4000	8000	4000	20000	29285	29296	1	1	61001	1000	1000	0	4000	8	4002	0	5	4000	5	1	5	8	12924	9200	6849	3124	6	76	19368	3109	3822	12	63	55	28683	16319	13022	13530	4000	8000	29271	29349	29419	29283	29300
72004	29215	218	15	15	0	0	0	9	1	0	4476	29102	0	0	0	15222	12014	8014	4000	8000	4000	20330	98350	5	24743	29108	29255	3	10	12000	4000	8000	4000	20000	29201	29269	1	1	61001	1000	1000	0	4000	0	4006	0	6	4008	6	0	5	0	13197	9293	6840	3143	11	56	19343	3085	3821	19	58	58	28600	16493	12963	13616	4000	8000	29356	29469	29405	29308	29266
72004	29348	220	22	29	0	1	0	10	0	0	4631	29117	0	0	4	15362	12000	8000	4000	8000	4000	20321	98365	1	24782	29146	29310	3	10	12000	4000	8000	4000	20000	29178	29325	1	1	61001	1000	1000	0	4000	8	4000	0	6	4000	5	0	2	8	13021	9223	6814	3065	9	64	19342	3089	3820	19	62	58	28558	16355	12959	13504	4000	8000	29299	29245	29291	29299	29340
72004	29362	219	26	11	1	0	0	0	1	0	4562	29119	2	0	0	15203	12014	8014	4000	8000	4000	20341	98328	5	24769	29254	29299	3	10	12000	4000	8000	4000	20000	29195	29191	1	1	61001	1000	1000	0	4000	0	4000	0	0	4002	6	0	0	12	12973	9194	6854	3082	10	60	19334	3134	3824	21	56	55	28461	16337	13072	13597	4000	8000	29234	29298	29377	29354	29241
72004	29289	220	17	28	1	1	0	8	0	0	4549	29036	2	0	0	15238	12014	8024	4000	8000	4000	20385	98336	1	24769	29154	29210	3	10	12000	4000	8000	4000	20000	29157	29176	1	1	61001	1000	1000	0	4000	12	4003	0	83	4000	6	1	0	12	12963	9113	6869	3026	10	60	19250	3017	3821	17	56	59	28524	16261	13121	13524	4000	8000	29353	29353	29290	29410	29392
72004	29360	220	19	19	0	0	0	8	0	0	4551	29075	0	0	0	15347	12000	8014	4000	8000	4000	20322	98064	3	24768	29216	29304	3	10	12000	4000	8000	4000	20000	29255	29193	1	1	61001	1000	1000	0	4000	0	4002	0	5	4005	6	1	2	0	12931	9236	6836	3029	5	56	19311	3035	3820	14	59	57	28594	16361	12998	13557	4000	8000	29269	29404	29344	29310	29293
72004	29315	220	20	24	0	0	0	8	0	0	4555	29078	0	0	0	15331	12014	8014	4000	8000	4000	20313	98013	0	24741	29231	29290	3	10	12000	4000	8000	4000	20000	29334	29255	1	1	61001	1000	1000	0	4000	0	4003	0	107	4003	6	1	2	8	12863	9003	6847	3150	12	60	19348	3092	3822	18	52	61	28493	16469	12737	13506	4000	8000	29358	29381	29354	29215	29389
72004	29318	220	21	22	1	0	0	8	0	0	4547	29114	2	0	0	15293	12028	8014	4000	8000	4000	20334	98405	2	24750	29252	29249	3	10	12000	4000	8000	4000	20000	29185	29245	1	1	61001	1000	1000	0	4000	0	4002	0	8	4002	6	1	0	8	12925	9166	6934	3115	9	51	19316	3068	3821	17	56	59	28483	16170	13127	13573	4000	8000	29298	29346	29359	29387	29296
72004	29342	220	24	20	0	1	0	0	0	0	4496	29129	0	0	0	15356	12000	8000	4000	8000	4000	20325	98324	3	24783	29188	29365	3	10	12000	4000	8000	4000	20000	29199	29213	1	1	61001	1000	1000	0	4000	11	4003	0	8	4005	0	1	3	0	12930	9402	6837	3065	9	64	19260	3131	3827	16	57	60	28539	16398	12894	13426	4000	8000	29368	29329	29284	29282	29269
72004	29335	220	19	15	0	0	0	0	1	0	4579	29020	0	0	0	15299	12014	8014	4000	8000	4000	20314	98401	0	24705	29229	29331	3	10	12000	4000	8000	4000	20000	29291	29200	1	1	61001	1000	1000	0	4000	0	4002	0	0	4002	6	1	0	8	12801	9157	6813	3025	10	55	19229	3097	3824	12	64	57	28417	16341	12868	13587	4000	8000	29306	29264	29387	29323	29321

Count: 8

Code:

  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960205	160069	1199	0	0	0	0	0	0	0	53	0	1	0	0	0	160044	3	12	12	0	0	25	960156	100	640000	320000	100	640000	320000	500	1680482	18560012	1	160040	0	160043	160043	0	0	3	25	960100	200	320000	640000	200	320000	1600000	160059	160059	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	35	0	320682	4	0	320032	6	1	0	35	0	0	0	5109	0	2	17	1	3	160056	10	10	1	320000	640000	100	160060	160044	160044	160060	160044
960204	160043	1199	0	0	0	0	0	0	0	0	0	1	0	0	0	160044	3	0	12	0	0	25	960156	100	640056	320000	100	640000	320000	500	1680935	18560012	1	160040	0	160043	160059	0	0	3	41	960100	200	320000	640000	200	320000	1600000	160059	160059	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	35	0	320032	0	239	320032	0	1	32	35	0	0	0	5109	0	1	17	1	4	160056	0	10	1	320000	640000	100	160060	160060	160060	160044	160044
960204	160043	1199	0	0	0	0	0	0	0	38	0	0	0	0	0	160044	3	0	12	0	17	25	960100	100	640056	320086	100	640000	320000	500	1680467	18560016	1	160040	0	160059	160043	0	0	3	41	960100	200	320000	640000	200	320000	1600000	160043	160059	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	35	0	320032	30	32	320032	6	1	32	0	0	0	0	5109	0	1	17	2	3	160042	14	10	0	320000	640000	100	160044	160060	160060	160044	160060
960204	160059	1199	0	0	0	0	0	0	0	38	0	1	0	0	0	160129	3	12	12	0	0	25	960156	100	640056	320000	100	640000	320000	500	1680001	8160000	0	160040	0	160059	160061	0	0	3	25	960100	200	320000	640000	200	320000	1600000	160059	160043	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	0	0	320000	0	0	320032	0	1	0	35	0	0	0	5109	0	1	17	3	4	160056	0	10	1	320000	640000	100	160060	160044	160044	160044	160044
960204	160045	1199	0	0	0	0	1	0	0	38	0	0	0	0	0	160028	3	12	0	0	0	25	960156	100	640000	320000	100	640000	320000	500	1680001	18560012	0	160024	0	160059	160059	0	0	3	41	960100	200	320000	640000	200	320000	1600000	160043	160043	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	35	0	320032	0	32	320032	0	1	32	0	0	0	0	5109	0	4	17	4	3	160040	0	0	0	320000	640000	100	160061	160060	160044	160044	160060
960204	160059	1199	0	0	0	0	0	0	0	12	0	1	0	0	0	160044	3	0	12	0	0	25	960156	100	640000	320000	100	640000	320000	500	1680001	8160000	0	160024	0	160043	160059	0	0	3	25	960100	200	320000	640300	200	320000	1600000	160043	160059	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	0	16	320032	0	32	320032	6	1	0	35	0	0	0	5137	0	2	17	2	4	160056	10	10	1	320000	640000	100	160060	160060	160044	160060	160044
960204	160059	1199	0	0	0	0	0	0	0	0	0	0	0	0	0	160028	0	0	12	0	0	228	962372	100	640064	320000	100	640800	320796	500	1708445	9853392	0	160812	0	163245	162600	0	0	3	41	960100	200	320000	640000	200	320000	1600000	160045	160043	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	35	0	320000	0	32	320032	6	1	32	35	0	0	0	5109	0	5	17	5	3	160040	0	14	1	320000	640000	100	160060	160060	160044	160060	160060
960204	160043	1198	0	0	0	0	0	0	0	38	0	1	0	0	0	160028	0	12	0	0	0	25	960156	100	640056	320000	100	640000	320096	500	1681086	18560016	0	160024	0	160059	160059	0	0	3	41	960100	200	320000	640000	200	320000	1600000	160059	160060	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	35	0	320032	0	0	320032	6	1	32	35	0	0	0	5109	0	2	17	3	3	160061	10	0	1	320000	640000	100	160060	160060	160060	160044	160044
960204	160059	1199	0	0	0	0	0	0	0	0	0	0	0	0	0	160028	0	12	0	0	0	25	960156	100	640056	320000	100	640000	320000	500	1680001	18560012	0	160040	0	160043	160059	0	0	3	25	960100	200	320000	640000	200	320000	1600000	160059	160059	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	0	0	320032	0	32	320032	6	0	0	0	0	0	0	5109	0	2	17	3	4	160040	10	0	1	320000	640000	100	160060	160060	160044	160060	160060
960204	160059	1199	0	0	0	0	1	0	0	0	0	0	0	0	0	160028	3	12	0	0	0	25	960156	100	640064	320000	100	640000	320000	500	1680415	18560012	0	160024	0	160059	160059	0	0	3	41	960100	200	320000	640000	200	320000	1600000	160059	160059	1	1	80202	100	99	100	100	80000	80000	0	100	320000	0	35	0	320032	0	38	320000	0	1	32	0	0	0	0	5109	0	4	17	4	2	160056	0	10	1	320000	640000	100	160060	160060	160044	160044	160060

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960025	160056	1199	0	0	0	0	0	0	0	30	0	0	0	160050	3	12	12	0	25	960054	10	640044	320000	10	640000	320000	50	1680242	16639980	0	160024	160056	160056	0	0	3	38	960010	20	320000	640000	20	320152	1600000	160056	160056	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	27	0	320024	0	0	0	24	320000	6	0	24	0	0	0	0	0	5019	3	17	5	3	160040	6	6	1	320000	640000	10	160057	160057	160044	160057	160057
960024	160056	1199	0	0	0	0	0	0	0	30	0	1	0	160041	1	12	0	0	45	960054	10	640044	320000	10	640000	320000	50	1680227	16639980	0	160037	160056	160056	0	0	3	25	960010	20	320000	640000	20	320000	1600000	160056	160043	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	27	0	320024	1	3	0	0	320000	6	0	24	27	0	0	0	0	5019	3	17	5	3	160053	6	6	0	320000	640000	10	160044	160057	160044	160057	160057
960024	160056	1199	0	0	0	1	0	0	0	30	0	0	0	160041	3	12	12	0	25	960054	10	640140	320000	10	640000	320000	50	1680045	16639980	1	160037	160043	160043	0	0	3	25	960010	20	320000	640000	20	320000	1600000	160055	160056	1	1	80021	10	9	10	10	80000	80000	1	10	320000	0	27	0	320000	0	0	0	24	320024	6	0	0	27	0	0	0	0	5019	4	17	4	4	160053	6	6	1	320000	640000	10	160057	160057	160057	160044	160136
960024	160053	1199	0	0	0	0	0	0	0	30	0	1	0	160050	3	0	12	0	25	960058	10	640000	320000	10	640000	320000	50	1680001	16639980	0	160024	160056	160046	0	0	3	25	960010	20	320000	640000	20	320000	1600000	160043	160056	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	27	0	320024	0	0	0	0	320000	6	0	0	27	0	0	0	0	5019	4	17	4	4	160053	6	0	1	320000	640000	10	160057	160044	160057	160057	160044
960024	160056	1199	0	0	0	0	0	0	0	0	0	1	0	160041	3	0	12	0	25	960054	10	640044	320000	10	640532	320408	50	1680001	16000020	1	160024	160056	160056	0	0	3	38	960010	20	320000	640000	20	320000	1600000	160056	160043	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	27	0	320000	0	0	0	24	320024	6	1	24	27	0	0	0	0	5019	2	17	4	4	160040	0	6	1	320000	640000	10	160044	160044	160044	160057	160044
960024	160056	1198	0	0	0	0	0	0	0	30	0	1	0	160041	3	12	0	0	25	960010	10	640044	320000	10	640000	320000	50	1680247	8160000	1	160024	160056	160043	0	0	3	38	960010	20	320000	640000	20	320000	1600000	160056	160056	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	27	0	320000	0	63	0	24	320024	0	1	24	27	0	0	0	0	5019	3	17	5	5	160053	6	6	0	320000	640000	10	160057	160044	160044	160057	160044
960024	160056	1199	0	0	0	0	0	0	0	30	0	1	0	160041	0	12	12	0	25	960054	10	640044	320000	10	640000	320000	50	1680242	16639980	1	160037	160056	160056	0	0	3	25	960010	20	320000	640000	20	320000	1600000	160056	160056	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	0	0	320024	0	0	0	871	320024	0	1	0	27	0	0	0	0	5019	3	17	5	5	160053	0	6	1	320000	640000	10	160057	160044	160057	160057	160057
960024	160056	1199	0	0	0	0	0	0	0	30	0	0	0	160041	3	12	0	0	25	960054	10	640044	320000	10	640000	320000	50	1680242	16639980	1	160037	160056	160043	0	0	3	25	960010	20	320000	640000	20	320000	1600000	160043	160056	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	0	0	320024	0	0	0	0	320024	0	0	24	27	0	0	0	0	5019	4	17	3	4	160053	0	0	1	320000	640000	10	160044	160057	160057	160057	160047
960024	160043	1199	0	0	0	0	0	0	0	0	0	1	0	160041	3	0	12	0	25	960010	10	640000	320000	10	640000	320000	50	1680001	16639980	0	160024	160043	160043	0	0	3	25	960010	20	320000	640000	20	320000	1600000	160056	160056	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	27	0	320024	0	0	0	24	320032	6	1	24	0	0	0	0	1	5019	4	17	4	4	160053	6	6	0	320000	640000	10	160044	160044	160057	160044	160057
960024	160043	1199	0	0	0	0	0	0	0	0	0	1	0	160041	2	12	12	0	25	960054	10	640044	320000	10	640000	320000	50	1680001	8160000	1	160027	160043	160044	0	0	3	38	960010	20	320000	640000	20	320000	1600000	160044	160046	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	27	0	320025	0	0	0	0	320000	6	1	24	27	0	0	0	0	5019	4	17	5	3	160040	0	6	0	320000	640000	10	160057	160057	160045	160044	160044

LD4 (multiple, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations