Firestorm: LD4 (multiple, 8B) measurements

Code:

  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.008

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	0e	0f	18	19	1e	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
66005	29038	225	2	0	0	0	0	0	4	1	0	0	5141	28234	2	2	2	15970	6000	4012	2000	4000	2000	10000	47500	3	23035	0	28316	28332	3	10	6000	2000	4000	2000	8000	28186	28167	1	1	61001	1000	1000	0	2000	0	4	2004	1	4	2002	2	2	4	13883	10052	7258	3430	1	51	19227	3435	3818	17	38	38	28020	14298	12146	12921	2000	4000	28210	28289	28200	28283	28353
66004	28326	213	0	0	0	1	0	0	4	1	0	0	5171	28262	0	2	2	15995	6012	4012	2000	4000	2000	10000	47574	2	23055	0	28230	28394	3	10	6000	2000	4000	2000	8000	28416	28128	1	1	61001	1000	1000	0	2000	0	4	2000	0	0	2002	0	4	4	13504	10049	7134	3392	0	40	19098	3296	3815	13	44	36	27975	14149	12304	13252	2000	4000	28511	28497	28453	28259	28281
66004	28349	212	0	0	0	0	0	0	0	1	0	0	4939	28247	2	0	0	15833	6008	4012	2000	4000	2000	10000	47552	4	23014	0	28133	28325	3	10	6000	2000	4000	2000	8000	28432	28272	1	1	61001	1000	1000	0	2000	0	4	2000	0	4	2004	2	2	4	14045	10228	7143	3293	1	39	19117	3397	3821	10	42	43	27852	14630	11908	13227	2000	4000	28430	28361	28366	28425	28387
66004	28330	214	0	0	0	0	0	0	6	1	0	0	5050	28005	2	2	2	15798	6012	4012	2000	4000	2000	10000	47584	4	23032	0	28048	28298	3	10	6000	2000	4000	2000	8000	28289	28258	1	1	61001	1000	1000	1	2000	0	4	2004	0	4	2004	2	2	4	13655	10008	7071	3399	0	42	19322	3312	3820	11	47	39	27831	14319	12024	13679	2000	4000	28389	28471	28175	28332	28413
66004	28362	213	0	0	0	0	0	0	8	1	0	0	5083	28124	2	2	2	15922	6012	4012	2000	4000	2000	10000	47556	4	23064	0	28250	28431	3	10	6000	2000	4000	2000	8000	28339	28202	1	1	61001	1000	1000	1	2000	0	4	2004	0	4	2002	0	4	0	13863	10080	7117	3318	0	41	19274	3385	3820	9	37	40	28077	14541	12042	13446	2000	4000	28257	28421	28254	28458	28263
66004	28368	213	0	0	1	1	0	0	4	1	0	0	4982	28037	0	2	2	15949	6008	4000	2000	4000	2000	10000	47528	4	23061	0	28264	28220	3	10	6000	2000	4000	2000	8000	28291	28392	1	1	61001	1000	1000	0	2000	0	4	2002	0	0	2004	2	4	4	13579	9978	7192	3448	0	43	19327	3347	3815	13	44	40	27924	14128	11902	13162	2000	4000	28361	28356	28424	28334	28231
66004	28303	212	1	0	0	0	0	0	4	1	0	0	4895	28094	2	2	2	15874	6008	4012	2000	4000	2000	10000	47578	6	23079	0	28212	28368	3	10	6000	2000	4000	2000	8000	28359	28341	1	1	61001	1000	1000	0	2000	0	4	2002	1	7	2004	2	2	4	13936	9853	7065	3376	0	44	19120	3250	3824	13	40	41	28052	14743	12121	13700	2000	4000	28431	28524	28437	28322	28372
66004	28339	213	2	0	0	0	0	0	0	1	0	0	4958	28248	0	2	0	15825	6012	4012	2000	4000	2000	10000	47552	6	23031	0	28168	28321	3	10	6000	2000	4000	2000	8000	28368	28316	1	1	61001	1000	1000	0	2000	0	4	2002	0	2	2002	2	2	4	13614	10157	7162	3392	0	38	19170	3409	3815	15	40	37	27951	14549	11943	12967	2000	4000	28362	28303	28256	28398	28339
66004	28294	212	0	0	0	0	0	0	4	1	0	0	5000	28159	0	2	2	16148	6012	4000	2000	4000	2000	10000	47526	8	23038	0	28234	28246	3	10	6000	2000	4000	2000	8000	28165	28305	1	1	61001	1000	1000	0	2000	0	4	2002	0	2	2000	2	4	4	13637	9836	7210	3194	0	45	19152	3313	3813	8	43	42	27954	14429	11876	13259	2000	4000	28295	28308	28414	28385	28408
66004	28272	213	1	0	0	0	0	0	0	1	0	0	5147	28296	0	2	2	16076	6012	4012	2000	4000	2000	10000	47540	7	22993	0	28250	28433	3	10	6000	2000	4000	2000	8000	28403	28306	1	1	61001	1000	1000	0	2000	0	4	2004	0	2	2002	2	4	4	13766	10036	7068	3442	0	39	19191	3313	3812	14	35	43	28025	14929	12296	13624	2000	4000	28464	28409	28214	28284	28318

Count: 8

Code:

  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480205	80072	599	1	1	0	0	1	0	0	0	58	0	0	2	80054	2	5	5	5	0	25	480172	100	320072	160000	100	320000	160000	500	800048	5440028	0	80050	0	80069	80069	3	3	51	480100	200	160000	320000	200	160000	640000	80047	80069	1	1	80201	100	99	100	100	80000	80000	0	100	160013	15	43	0	160053	1	1	56	160039	6	1	52	43	12	0	5109	1	17	1	1	80066	13	13	4	160000	320000	100	80070	80049	80070	80070	80070
480204	80069	599	1	1	1	1	0	0	0	0	57	1	0	0	80054	0	5	0	5	0	25	480124	100	320072	160000	100	320000	160000	500	801187	10880752	0	80028	0	80069	80047	0	3	51	480100	200	160000	320000	200	160000	640000	80069	80047	1	1	80201	100	99	100	100	80000	80000	0	100	160013	13	43	0	160052	0	1	51	160000	6	1	51	43	13	2	5109	1	17	1	1	80066	13	13	0	160000	320000	100	80048	80048	80048	80070	80070
480204	80069	600	1	0	0	0	0	0	0	0	58	1	0	0	80032	0	5	5	0	0	25	480172	100	320024	160000	100	320000	160000	500	801187	10880752	1	80028	0	80069	80047	3	3	29	480100	200	160000	320000	200	160000	640000	80069	80069	1	1	80201	100	99	100	100	80000	80000	0	100	160012	14	43	0	160054	0	2	52	160000	0	1	51	43	13	0	5109	1	17	1	1	80066	13	13	0	160000	320000	100	80070	80070	80070	80048	80048
480204	80070	600	1	0	0	0	0	0	0	0	58	1	0	2	80032	0	5	5	5	0	25	480164	100	320064	160000	100	320000	160000	500	800042	10880752	0	80050	0	80047	80069	0	3	29	480100	200	160000	320000	200	160000	640000	80047	80069	1	1	80201	100	99	100	100	80000	80000	0	100	160015	14	0	0	160052	0	2	52	160039	0	0	51	43	12	0	5109	1	17	1	1	80066	0	13	5	160000	320000	100	80070	80070	80070	80070	80049
480204	80069	599	1	1	0	0	0	0	0	0	58	1	0	2	80054	2	5	5	5	0	25	480172	100	320072	160000	100	320000	160000	500	801179	10880888	0	80050	0	80069	80047	3	3	51	480100	200	160000	320000	200	160000	640000	80047	80069	1	1	80201	100	99	100	100	80000	80000	0	100	160014	13	43	0	160052	0	1	52	160000	6	1	52	43	13	2	5109	1	17	1	1	80044	0	13	4	160000	320000	100	80070	80070	80070	80048	80070
480204	80047	599	1	1	1	0	0	0	0	0	12	1	0	2	80032	2	0	5	5	0	25	480172	100	320072	160000	100	320000	160000	500	800042	10880752	0	80050	0	80069	80069	0	3	29	480100	200	160000	320000	200	160000	640000	80069	80069	1	1	80201	100	99	100	100	80000	80000	0	100	160014	12	43	0	160013	0	2	55	160000	0	1	52	43	13	0	5109	1	17	1	1	80066	0	13	5	160000	320000	100	80070	80070	80070	80070	80048
480204	80069	599	1	0	0	1	0	0	0	0	21	1	0	3	80054	2	0	5	5	0	25	480164	100	320072	160000	100	320000	160000	500	801179	5440032	0	80050	0	80069	80069	3	3	52	480514	200	160000	320000	200	160000	640000	80069	80069	1	1	80201	100	99	100	100	80000	80000	0	100	160012	14	43	0	160012	1	2	52	160039	6	1	12	0	12	0	5109	1	17	1	1	80044	13	13	0	160000	320000	100	80070	80048	80070	80048	80048
480204	80069	599	1	0	1	1	0	0	0	0	73	1	0	2	80054	0	0	5	5	0	25	480164	100	320064	160000	100	320000	160000	500	801181	10880752	0	80028	0	80071	80069	3	3	53	480100	200	160000	320000	200	160000	640000	80069	80069	1	1	80201	100	99	100	100	80000	80000	0	100	160015	14	0	0	160053	0	0	13	160039	0	0	52	43	13	0	5109	1	17	1	1	80066	13	13	0	160000	320000	100	80070	80048	80070	80070	80048
480204	80069	600	1	0	1	0	0	0	0	0	58	1	0	2	80054	2	5	5	5	0	25	480172	100	320024	160000	100	320000	160000	500	800048	10880752	0	80028	0	80069	80069	3	3	51	480100	200	160000	320000	200	160000	640000	80069	80047	1	1	80201	100	99	100	100	80000	80000	0	100	160014	14	43	0	160052	0	1	51	160039	6	1	12	43	13	0	5109	1	17	1	1	80044	0	13	5	160000	320000	100	80070	80048	80070	80048	80070
480204	80069	600	1	1	1	1	1	1	0	0	58	1	0	2	80032	2	0	5	5	0	25	480124	100	320072	160138	100	320000	160000	500	800043	10880752	0	80028	0	80047	80069	0	3	29	480100	200	160000	320000	200	160000	640000	80048	80047	1	1	80201	100	99	100	100	80000	80000	0	100	160015	13	43	0	160054	0	1	52	160039	6	1	52	0	12	1	5109	1	17	1	1	80066	0	13	0	160000	320000	100	80070	80070	80048	80070	80070

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480025	80056	599	1	0	1	0	0	0	57	0	1	0	80041	2	12	12	0	25	480070	10	320060	160000	10	320000	160000	50	800222	8320000	0	80037	0	80056	80056	0	0	3	38	480010	20	160000	320000	20	160000	640000	80056	80056	1	1	80021	10	9	10	10	80000	80000	1	10	160000	0	27	0	160023	0	24	160024	6	1	24	27	0	5019	12	17	2	3	80053	1	6	6	0	160000	320000	10	80057	80057	80042	80057	80042
480024	80056	600	0	0	0	0	0	0	30	0	1	0	80041	0	0	12	0	25	480070	10	320060	160000	10	320000	160000	50	800000	3840000	0	80022	0	80056	80041	0	0	3	38	480010	20	160000	320000	20	160000	640000	80056	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	0	0	160000	0	0	160000	6	1	24	27	0	5019	6	17	2	3	80053	0	6	6	0	160000	320000	10	80057	80057	80337	80505	80057
480024	80056	599	0	0	0	0	0	0	324	164	0	0	80501	2	12	12	0	59	480070	10	320060	160000	10	320000	160000	50	800000	8320000	0	80022	0	80338	80056	0	0	56	39	480010	20	160260	320260	20	160000	640000	80056	80056	2	1	80021	10	9	10	10	80000	80000	0	10	160504	2	27	0	160024	0	24	160024	6	0	24	27	0	5019	2	26	2	3	80708	1	6	6	0	160000	320000	10	80057	80057	80057	80057	80057
480024	80056	599	0	0	0	1	0	1	30	0	0	0	87128	0	12	0	1300	1724	493610	10	332100	166754	10	333320	167452	50	979235	6487344	0	86815	0	88641	88422	1254	702	3	38	480010	20	160000	320000	20	160000	640000	80041	80044	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160024	0	24	160000	0	1	0	0	0	5019	2	17	6	2	80038	1	6	6	0	160000	320000	10	80057	80057	80042	80138	80057
480024	80056	600	0	0	0	0	0	0	30	0	1	0	80041	2	12	12	0	25	480070	10	320000	160000	10	320000	160000	50	800218	8320000	0	80037	0	80056	80056	0	0	3	38	480010	20	160000	320000	20	160000	640000	80056	80056	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	0	0	160024	0	24	160024	0	1	24	27	0	5019	2	17	2	2	80053	1	6	6	0	160000	320000	10	80057	80057	80057	80057	80042
480024	80056	599	0	0	0	0	0	0	30	0	1	0	80041	2	0	0	0	25	480070	10	320060	160000	10	320000	160000	50	800221	8320000	0	80037	0	80056	80056	0	0	3	38	480010	20	160000	320000	20	160000	640000	80041	80056	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160024	0	0	160024	6	1	24	27	0	5019	2	17	2	6	80038	0	0	6	0	160000	320000	10	80057	80057	80042	80057	80057
480024	80056	600	0	0	0	0	0	0	756	0	1	0	80041	0	12	12	0	25	480066	10	320060	160000	10	320000	160000	50	800000	8320000	0	80037	0	80041	80056	0	0	3	38	480010	20	160000	320000	20	160000	640000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160000	0	24	160000	6	0	24	0	0	5019	2	17	2	2	80053	1	6	6	0	160000	320000	10	80057	80057	80057	80042	80057
480024	80056	600	0	0	0	0	0	0	30	0	1	0	80041	2	12	0	0	25	480070	10	320060	160000	10	320000	160000	50	800219	3840000	0	80037	0	80116	80056	0	0	3	38	480010	20	160000	320000	20	160000	640000	80056	80056	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160024	0	0	160024	6	1	24	27	0	5019	2	17	2	6	80053	1	0	6	0	160000	320000	10	80042	80057	80057	80042	80057
480024	80056	600	0	0	0	0	0	0	30	0	1	0	80041	2	12	12	0	25	480070	10	320076	160000	10	320000	160000	50	800000	8320000	0	80037	0	80056	80056	0	0	3	38	480010	20	160000	320000	20	160000	640000	80056	80056	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160024	0	24	160024	6	1	24	0	0	5019	6	17	6	2	80053	1	0	6	0	160000	320000	10	80042	80057	80057	80057	80042
480024	80056	599	0	0	0	0	0	0	843	0	0	0	80026	0	12	0	0	25	480010	10	320060	160000	10	320000	160000	50	800219	8320000	0	80037	0	80041	80056	0	0	3	38	480010	20	160000	320000	20	160000	640000	80056	80056	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160000	0	0	160024	6	1	24	27	0	5050	2	17	2	6	80053	1	6	6	0	160000	320000	10	80057	80057	80057	80107	80057

LD4 (multiple, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations