Firestorm: LD4 (multiple, 8H) measurements

Code:

  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 12.014

Integer unit issues: 0.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.014

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	0e	0f	1e	1f	22	24	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
72005	28442	211	18	22	0	0	8	0	1	0	5114	28059	4	2	14234	12014	8014	4000	8000	4000	20337	98277	8	0	0	24785	28035	28178	3	10	12000	4000	8000	4000	20000	28465	28213	1	1	61001	1000	1000	0	4000	8	4004	0	2	4000	0	1	4	8	0	13793	10280	7258	3508	7	50	18103	3485	3814	16	45	48	27902	14085	11738	11930	4000	8000	28256	28271	28381	28210	28265
72004	28535	211	12	14	0	0	8	0	0	0	5215	28127	4	0	14213	12000	8000	4000	8000	4000	20336	98321	9	0	0	24779	28044	28307	3	10	12000	4000	8000	4000	20000	28233	28139	1	1	61001	1000	1000	0	4000	8	4004	0	0	4000	0	0	0	0	0	13450	9617	7258	3508	8	38	18006	3401	3813	14	44	43	27878	15175	12119	11780	4000	8000	28133	28446	28246	28031	28087
72004	28113	210	19	14	0	0	10	0	1	0	5114	28137	0	4	14084	12000	8014	4000	8000	4000	20341	98232	3	0	0	24720	28239	28083	3	10	12000	4000	8000	4000	20000	28203	28426	1	1	61001	1000	1000	1	4000	8	4004	0	0	4004	4	1	4	0	0	13336	10276	7166	3433	7	41	18109	3421	3810	13	42	44	27870	13998	11725	12046	4000	8000	28502	28645	28381	28400	28125
72004	28684	212	21	17	0	0	8	0	0	0	5167	28127	0	4	14172	12014	8000	4000	8000	4000	20343	98076	4	0	0	24719	28135	28070	3	10	12000	4000	8000	4000	20000	28150	28294	1	1	61001	1000	1000	0	4000	8	4004	0	4	4002	4	0	4	8	0	13918	10515	7208	3242	9	40	18410	3517	3805	9	42	43	27875	14187	12044	12299	4000	8000	28140	28155	28168	28132	28091
72004	28193	211	16	12	1	0	8	0	1	0	5050	28121	0	4	14085	12014	8014	4000	8000	4000	20340	98247	12	0	0	24726	28088	28057	3	10	12000	4000	8000	4000	20000	28319	28185	1	1	61001	1000	1000	0	4000	0	4004	0	6	4004	4	0	4	8	0	13954	10259	7155	3501	9	46	18125	3577	3804	11	49	44	27988	15107	11770	12255	4000	8000	28127	28213	28237	28341	28098
72004	28154	210	16	19	0	0	0	0	0	0	5265	27928	4	0	14062	12014	8014	4000	8000	4000	20347	98387	7	0	0	24711	28103	28182	3	10	12000	4000	8000	4000	20000	28097	28147	1	1	61001	1000	1000	0	4000	8	4000	0	2	4000	4	1	4	0	0	13927	9893	7037	3497	9	44	18198	3437	3811	17	45	56	27975	14203	11552	12025	4000	8000	28104	28276	28136	28177	28055
72004	28157	211	13	19	0	1	0	0	0	0	5186	28063	4	0	14029	12000	8014	4000	8000	4000	20330	98295	6	0	0	24715	28153	28533	3	10	12000	4000	8000	4000	20000	28075	28043	1	1	61001	1000	1000	1	4000	8	4004	0	4	4004	4	0	4	8	0	13807	10298	7238	3455	11	37	18129	3407	3809	13	44	42	27958	13974	11696	12087	4000	8000	28274	28099	28480	28159	28290
72004	28547	212	15	18	0	0	8	0	0	0	5185	28189	4	4	14243	12014	8000	4000	8000	4000	20335	98281	9	0	0	24712	28137	28349	3	10	12000	4000	8000	4000	20000	28088	28176	1	1	61001	1000	1000	0	4000	8	4004	0	7	4004	0	0	0	8	0	13780	10239	7037	3337	6	39	18109	3402	3816	15	44	46	27939	14554	11903	12051	4000	8000	28195	28292	28391	28443	28099
72004	28572	212	19	16	0	0	9	0	0	0	5084	28050	4	4	14265	12014	8014	4000	8000	4000	20340	98309	3	0	0	24700	28024	28154	3	10	12000	4000	8000	4000	20000	28186	28411	1	1	61001	1000	1000	0	4000	8	4003	0	4	4002	4	0	2	8	0	14077	10268	7008	3466	5	42	18011	3429	3812	7	43	40	27777	14167	11738	11858	4000	8000	28115	28192	28204	28079	28064
72004	28050	211	16	13	0	0	8	0	1	0	5237	27999	4	4	13992	12000	8000	4000	8000	4000	20343	98291	8	0	0	24742	28065	28099	3	10	12000	4000	8000	4000	20000	28192	28063	1	1	61001	1000	1000	1	4000	8	4000	0	2	4004	4	1	4	8	0	13881	10148	7222	3435	8	44	18130	3362	3817	12	45	46	27873	14030	11746	12223	4000	8000	28042	28188	28434	28230	28060

Count: 8

Code:

  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960205	160072	1199	1	0	1	0	0	1	0	0	0	0	63	0	1	0	3	160054	2	6	6	0	0	25	960541	100	640068	320000	100	640000	320000	500	1681236	11520028	1	160030	0	160069	160069	4	0	3	51	960544	200	320000	640000	200	320000	1600000	160069	160049	1	1	80201	100	99	100	100	80000	80000	0	100	320014	13	44	0	320053	0	0	0	53	320000	6	1	53	44	13	0	0	0	5109	4	17	4	4	160066	13	13	0	320000	640000	100	160070	160070	160070	160050	160070
960204	160049	1199	1	0	1	0	0	1	0	0	0	0	13	0	1	0	3	160054	2	6	6	5	0	25	960156	100	640060	320000	100	640000	320000	500	1681236	11520028	0	160050	0	160049	160050	3	0	3	51	960100	200	320000	640000	200	320000	1600000	160071	160049	1	1	80201	100	99	100	100	80000	80000	0	100	320013	14	44	0	320053	0	0	1	53	320040	6	1	13	44	13	1	0	0	5109	4	17	4	4	160066	13	13	2	320000	640000	100	160070	160070	160050	160070	160164
960204	160069	1199	1	0	0	0	0	1	0	0	0	0	13	0	0	0	2	160054	0	0	0	0	0	25	960168	100	640016	320000	100	640000	320000	500	1680098	21760752	0	160050	0	160069	160048	3	0	3	31	960100	200	320000	640000	200	320000	1600000	160069	160069	1	1	80201	100	99	100	100	80000	80000	0	100	320014	13	44	0	320053	0	0	1	53	320039	0	0	53	44	13	2	0	0	5109	4	17	4	4	160045	0	0	0	320000	640000	100	160050	160070	160050	160070	160070
960204	160069	1199	1	0	1	0	0	1	0	0	0	0	13	0	1	0	3	160054	2	6	0	5	0	25	960160	100	640068	320130	100	640000	320000	500	1681565	21760752	0	160050	0	160049	160049	66	0	3	51	960100	200	320000	640000	200	320000	1600000	160069	160049	1	1	80201	100	99	100	100	80000	80000	0	100	320013	14	0	0	320053	0	2	0	56	320000	6	0	53	44	13	0	0	0	5109	4	17	4	4	160068	13	0	2	320000	640000	100	160050	160050	160070	160070	160070
960204	160069	1202	1	0	0	0	0	0	0	0	0	0	59	0	0	0	0	160034	2	0	6	5	0	25	960116	100	640056	320000	100	640000	320000	500	1681236	21760752	0	160030	0	160049	160069	3	0	3	31	960100	200	320000	640000	200	320124	1600000	160069	160069	1	1	80201	100	99	100	100	80000	80000	0	100	320014	13	43	0	320053	0	0	0	56	320040	6	0	53	44	13	0	0	0	5129	4	17	4	3	160066	0	13	2	320000	640000	100	160070	160070	160070	160070	160070
960204	160069	1199	1	0	0	0	0	0	0	0	0	0	59	0	0	0	3	160054	2	6	6	6	0	25	960168	100	640068	320000	100	640000	320000	500	1681238	21760752	1	160050	0	160049	160069	3	0	27	31	960100	200	320000	640000	200	320000	1600000	160069	160069	1	1	80201	100	99	100	100	80000	80000	0	100	320014	14	44	0	320053	1	0	1	14	320040	6	0	13	44	13	1	0	0	5109	4	17	4	4	160066	13	13	4	320000	640000	100	160070	160052	160050	160070	160070
960204	160069	1199	1	0	1	0	0	0	0	0	0	0	13	0	0	0	0	160054	1	6	6	0	0	25	960156	100	640060	320000	100	640000	320000	500	1681249	21760752	0	160030	0	160069	160071	0	0	3	51	960100	200	320000	640000	200	320000	1600000	160049	160069	1	1	80201	100	99	100	100	80000	80000	0	100	320013	14	0	0	320054	0	0	0	13	320040	6	1	53	44	13	1	0	0	5109	4	17	6	4	160046	13	13	2	320000	640000	100	160072	160050	160050	160070	160050
960204	160069	1199	1	0	0	0	0	1	0	0	0	0	59	0	0	0	3	160034	2	6	6	0	0	25	960116	100	640068	320000	100	640000	320000	500	1681244	21760752	0	160030	0	160049	160049	3	0	3	31	960100	200	320000	640000	200	320000	1600000	160069	160049	1	1	80201	100	99	100	100	80000	80000	0	100	320014	13	44	0	320054	1	0	1	53	320040	6	1	53	44	13	1	0	0	5113	5	17	4	2	160066	0	13	2	320000	640000	100	160070	160070	160071	160070	160070
960204	160069	1199	1	0	1	0	0	0	0	0	0	0	59	0	0	0	0	160054	2	0	6	5	0	25	960156	100	640016	320000	100	640000	320000	500	1681236	21760752	1	160050	0	160049	160069	0	0	3	31	960100	200	320000	640000	200	320000	1600000	160049	160069	1	1	80201	100	99	100	100	80000	80000	0	100	320015	13	44	0	320053	1	1	1	56	320000	6	1	12	0	13	0	0	0	5109	4	17	3	11	160066	13	13	2	320000	640000	100	160050	160070	160050	160070	160204
960204	160069	1199	1	0	0	0	0	0	0	0	0	0	13	0	0	0	4	160054	2	6	6	5	0	25	960168	100	640016	320000	100	640000	320000	500	1680098	21760752	0	160050	0	160069	160049	0	0	3	51	960100	200	320000	640000	200	320000	1600000	160069	160069	1	1	80201	100	99	100	100	80000	80000	0	100	320015	13	44	0	320013	1	0	0	53	320040	6	1	13	44	13	2	0	0	5109	4	17	4	4	160166	13	13	0	320000	640000	100	160070	160070	160070	160070	160050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960025	160059	1199	0	0	0	574	0	0	0	160049	3	12	0	0	25	960074	10	640064	320000	10	640000	320000	50	1680881	18560012	0	160029	0	160043	160064	0	0	3	46	960010	20	320000	640000	20	320000	1600000	160043	160059	1	1	80021	10	9	10	10	80000	80000	0	10	320000	35	320037	1	0	320037	6	1	0	40	0	0	0	5019	0	0	3	17	0	3	3	160056	10	10	0	320000	640000	10	160065	160065	160066	160065	160065
960024	160064	1199	0	1	0	98	1	0	2	160049	3	0	12	0	25	960074	10	640000	320000	10	640000	320000	50	1680881	21759996	0	160040	0	160059	160064	0	0	3	41	960010	20	320000	640000	20	320000	1600000	160043	160043	1	1	80021	10	9	10	10	80000	80000	0	10	320000	35	320032	1	50	320032	6	1	32	35	0	0	0	5019	0	0	3	17	0	3	2	160061	14	10	1	320000	640000	10	160060	160065	160065	160060	160044
960024	160043	1199	0	0	0	104	1	0	0	160049	3	12	0	0	25	960074	10	640064	320000	10	640000	320000	50	1680413	18560012	0	160045	0	160064	160064	0	0	3	46	960010	20	320000	640000	20	320000	1600000	160064	160059	1	1	80021	10	9	10	10	80000	80000	0	10	320000	35	320037	0	0	320037	6	1	37	0	0	0	0	5019	0	1	3	17	0	2	3	160061	0	10	1	320000	640000	10	160065	160044	160921	161648	160044
960024	160064	1199	0	0	0	125	1	0	0	160028	3	12	12	0	25	960066	10	640000	320000	10	640000	320000	50	1680001	8160000	1	160040	0	160064	160059	0	0	3	41	960010	20	320000	640000	20	320000	1600000	160059	160059	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	320037	0	0	320037	6	0	32	0	0	0	0	5019	0	0	3	17	0	2	3	160061	10	10	1	320000	640000	10	160044	160065	160065	160060	160060
960024	160064	1198	0	0	0	43	1	0	2	160049	3	12	12	0	25	960010	10	640000	320000	10	640000	320000	50	1680890	18560012	0	160045	0	160064	160064	0	0	3	46	960010	20	320000	640000	20	320000	1600000	160064	160059	1	1	80021	10	9	10	10	80000	80000	0	10	320000	35	320032	0	0	320037	0	1	32	40	0	0	0	5019	0	0	3	17	0	3	3	160061	14	0	0	320000	640000	10	160044	160065	160066	160065	160142
960024	160043	1199	0	0	0	69	1	0	0	160044	3	12	12	0	25	960449	10	640056	320000	10	640000	320000	50	1680881	8160000	0	160024	0	160059	160064	0	0	3	46	960010	20	320000	640000	20	320000	1600000	160043	160059	1	1	80022	10	9	10	10	80000	80000	0	10	320000	0	320037	0	37	320037	6	1	0	40	0	0	0	5019	0	0	3	17	0	2	3	160061	10	10	0	320000	640000	10	160065	160065	160060	160044	160060
960024	160043	1199	0	0	0	43	1	0	2	160028	3	0	12	0	25	960066	10	640000	320000	10	640000	320000	50	1680881	21759996	0	160046	0	160064	160154	0	0	3	41	960010	20	320000	640000	20	320000	1600000	160043	160059	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	320000	64	40	320000	6	1	32	0	0	0	0	5019	0	0	3	17	0	3	3	160056	14	10	1	320000	640000	10	160065	160065	160065	160044	160044
960024	160064	1199	0	0	0	38	1	0	0	160028	3	12	12	0	25	960074	10	640064	320000	10	640000	320000	50	1680881	18560012	0	160024	0	160064	160043	0	0	3	48	960010	20	320000	640000	20	320000	1600000	160064	160043	1	1	80021	10	9	10	10	80000	80000	1	10	320000	35	320032	0	0	320037	6	1	37	0	0	0	0	5019	4	0	3	17	0	3	3	160056	10	10	1	320000	640000	10	160067	160065	160065	160065	160065
960024	160059	1199	0	0	0	72	0	0	2	160028	3	12	12	0	25	960066	10	640056	320000	10	640000	320000	50	1680881	18560012	0	160045	0	160064	160064	0	0	3	25	960010	20	320000	640000	20	320000	1600000	160059	160043	1	1	80021	10	9	10	10	80000	80000	0	10	320000	35	320037	0	32	320037	6	0	0	35	0	0	0	5019	0	0	3	17	0	3	3	160040	14	14	1	320000	640000	10	160060	160044	160065	160060	160044
960024	160059	1198	0	0	0	109	0	0	2	160028	3	12	12	0	25	960074	10	640056	320000	10	640000	320000	50	1680881	18560012	0	160024	0	160059	160064	0	0	3	41	960010	20	320000	640000	20	320000	1600000	160064	160059	1	1	80021	10	9	10	10	80000	80000	1	10	320000	0	320000	0	32	320037	0	1	37	40	0	0	0	5019	0	0	3	17	0	3	3	160061	14	10	1	320000	640000	10	160065	160065	160044	160061	160065

LD4 (multiple, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations