Firestorm: LD4 (multiple, post-index, 16B) measurements

Code:

  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 13.022

Integer unit issues: 1.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.026

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	1e	22	24	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
72005	29272	219	1	1	3	1	1	1	1	1	0	9	0	0	4714	29128	0	4	15285	13032	1000	8028	4000	1000	8000	4000	5000	20309	98159	1	0	0	24773	29252	29347	3	10	13000	4000	8000	5000	20000	29244	29201	1	1	61001	1000	1000	0	4005	4	0	4007	0	0	4	4006	6	1	6	0	4	2	12887	9106	7000	3089	1	51	19284	3077	3812	7	47	48	28528	1000	16216	13042	13324	4000	8000	1000	29206	29255	29286	29223	29350
72004	29275	219	0	1	0	1	0	1	0	0	0	15	0	0	4630	29044	0	4	15326	13028	1000	8022	4000	1000	8000	4000	5000	20340	98370	12	0	0	24739	29199	29161	3	10	13000	4000	8000	5000	20000	29164	29273	1	1	61001	1000	1000	0	4007	6	12	4011	0	2	9	4002	0	1	7	0	4	0	12795	9073	6916	3096	0	48	19246	2997	3814	11	42	42	28518	1000	16466	13081	13275	4000	8000	1000	29185	29231	29346	29300	29299
72004	29273	220	0	1	0	1	0	1	0	0	0	12	0	0	4600	29044	0	0	15306	13026	1000	8008	4000	1000	8000	4000	5000	20309	98505	10	0	0	24805	29139	29322	3	10	13000	4000	8000	5000	20000	29247	29320	1	1	61001	1000	1000	1	4004	4	8	4008	0	1	6	4002	5	0	10	12	4	2	12811	9204	6849	3076	0	39	19184	3087	3811	15	40	44	28523	1000	16352	13004	13308	4000	8000	1000	29244	29253	29271	29306	29245
72004	29201	219	0	1	0	1	0	1	0	0	0	16	0	0	4613	29060	0	0	15325	13022	1000	8022	4000	1000	8000	4000	5000	20340	98534	1	0	0	24798	29136	29271	3	10	13000	4000	8000	5000	20000	29273	29261	1	1	61001	1000	1000	1	4006	6	8	4011	0	0	4	4005	6	1	6	12	4	1	12845	9122	6851	3089	1	39	19244	3085	3817	11	48	44	28476	1000	16316	12969	13428	4000	8000	1000	29260	29335	29283	29304	29219
72004	29264	219	0	1	0	1	0	1	0	0	0	4	0	0	4579	29009	0	0	15302	13022	1000	8026	4000	1000	8000	4000	5000	20309	98525	11	0	0	24771	29093	29110	3	10	13000	4000	8000	5000	20000	29267	29212	1	1	61001	1000	1000	0	4006	6	8	4007	1	2	4	4003	6	0	9	0	4	2	12853	9114	6883	3060	0	41	19283	3068	3806	12	41	35	28489	1000	16352	13117	13205	4000	8000	1000	29235	29294	29331	29243	29314
72004	29325	219	0	1	0	1	1	1	0	0	0	12	0	0	4535	29069	0	0	15279	13022	1000	8022	4000	1000	8000	4000	5000	20309	98317	2	0	0	24805	29216	29307	3	10	13000	4000	8000	5000	20000	29258	29274	1	1	61001	1000	1000	0	4005	5	0	4010	0	2	6	4000	6	1	4	11	4	2	13167	9310	6848	3065	0	46	19274	3034	3810	10	42	45	28481	1003	16127	13083	13108	4000	8000	1000	29318	29359	29332	29279	29181
72004	29355	220	0	1	0	1	1	0	0	0	0	4	0	0	4668	29053	0	0	15311	13022	1000	8026	4000	1000	8000	4000	5000	20301	98091	0	0	0	24767	29225	29341	3	10	13000	4000	8000	5000	20000	29165	29202	1	1	61001	1000	1000	0	4006	6	12	4012	0	2	6	4002	0	1	4	11	4	1	12945	9402	6848	3062	0	40	19253	3053	3809	15	42	41	28461	1000	16306	13035	13323	4000	8000	1000	29212	29319	29342	29239	29279
72004	29242	219	0	1	0	1	0	1	0	0	0	12	0	0	4596	29131	0	0	15293	13022	1000	8026	4000	1000	8000	4000	5000	20326	98472	0	0	0	24764	29086	29274	3	10	13000	4000	8000	5000	20000	29246	29174	1	1	61001	1000	1000	0	4005	4	11	4008	0	0	4	4006	6	1	4	8	4	2	12951	9118	6858	3136	0	49	19235	3087	3812	13	42	38	28491	1000	16455	13086	13385	4000	8000	1000	29334	29315	29246	29306	29204
72004	29280	219	0	1	0	1	0	1	0	0	0	9	0	0	4576	29067	0	0	15363	13028	1000	8028	4000	1000	8000	4000	5000	20315	98416	6	0	0	24743	29204	29323	3	10	13000	4000	8000	5000	20000	29221	29226	1	1	61001	1000	1000	0	4006	6	0	4011	0	1	9	4000	6	1	10	11	4	1	13005	9204	6838	3119	0	41	19317	3063	3814	13	42	48	28624	1000	16310	12965	13518	4000	8000	1000	29330	29285	29363	29391	29223
72004	29323	219	0	1	0	0	0	1	0	0	0	13	0	0	4560	29123	0	0	15269	13022	1000	8022	4000	1000	8000	4000	5000	20320	98516	3	0	0	24807	29188	29350	3	10	13000	4000	8000	5000	20000	29163	29136	1	1	61001	1000	1000	1	4006	6	8	4009	1	2	6	4006	0	0	6	0	4	2	12741	9042	6858	3055	0	40	19342	3147	3813	17	43	46	28507	1000	16326	13136	13350	4000	8000	1000	29263	29345	29339	29254	29262

Count: 8

Code:

  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960205	160072	1199	1	1	0	0	0	0	0	0	0	59	0	0	0	2	160054	2	6	6	0	0	25	1040160	80100	640060	320000	80100	640000	320000	479601	1681243	21760752	0	0	160024	0	160045	160059	0	0	3	26	1040100	200	320812	642312	200	403505	1609304	162283	162444	16	1	80201	100	99	100	100	80000	80000	1	100	320000	0	35	0	320032	0	1	0	58	320037	6	1	32	35	0	0	0	0	5109	1	16	1	1	160040	80000	10	10	0	320000	640000	80100	160060	160044	160044	160060	160065
960204	160064	1199	0	0	0	0	0	0	0	0	0	67	0	0	0	0	160028	3	12	12	0	0	25	1040164	80100	640064	320000	80100	640000	320000	479601	1680408	18560012	1	0	160024	0	160043	160066	0	0	3	26	1040100	200	320000	640000	200	400000	1600000	160043	160059	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	35	0	320000	0	0	0	0	320000	6	1	32	40	0	0	0	0	5109	1	16	1	1	160056	80000	0	10	0	320000	640000	80100	160060	160067	160065	160065	160065
960204	160043	1199	0	0	0	0	0	0	0	0	0	43	0	1	0	0	160054	2	6	6	6	0	25	1040168	80100	640068	320000	80100	640000	320000	479601	1681244	11520028	1	0	160030	0	160069	160049	3	0	3	54	1040100	200	320000	640000	200	400000	1600000	160071	160069	1	1	80201	100	99	100	100	80000	80000	0	100	320013	14	44	0	320053	1	0	1	53	320172	6	0	53	44	13	1	0	0	5109	1	16	1	0	160051	80000	14	10	0	320000	640000	80100	160060	160060	160049	160044	160065
960204	160043	1198	0	0	0	0	0	0	0	0	0	38	0	0	0	2	160049	0	0	0	0	0	25	1040164	80100	640064	320000	80100	640000	320000	479601	1680408	8160000	1	0	160024	0	160064	160064	0	0	3	47	1040100	200	320000	640000	200	400000	1600000	160043	160043	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	0	0	320000	0	0	0	37	320037	6	0	0	40	0	0	0	0	5109	1	16	1	1	160041	80000	14	10	0	320000	640000	80100	160044	160067	160065	160044	160125
960204	160059	1199	0	0	0	0	0	0	0	0	0	0	0	0	0	0	160049	0	12	12	0	0	25	1040156	80100	640064	320000	80100	640000	320000	479601	1680408	18560012	1	0	160024	0	160064	160064	0	0	3	26	1040100	200	320000	640000	200	400000	1600000	160064	160062	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	35	0	320037	0	0	0	37	320037	0	0	0	0	0	0	0	0	5109	1	16	1	1	160056	80000	10	10	0	320000	640000	80100	160065	160044	160065	160044	160065
960204	160064	1199	0	0	0	0	0	0	0	0	0	0	0	0	0	2	160044	3	12	0	0	0	25	1040100	80100	640000	320000	80100	640000	320000	479601	1680001	19200016	1	0	160045	0	160064	160043	0	0	3	31	1040100	200	320000	640000	200	400000	1600000	160059	160060	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	35	0	320032	0	0	0	3	320037	0	0	32	0	0	0	0	0	5109	1	16	1	1	160056	80000	14	10	0	320000	640000	80100	160065	160067	160065	160065	160065
960204	160064	1198	0	0	0	0	0	0	0	0	0	0	0	1	0	2	160028	3	12	12	1	0	25	1040100	80100	640064	320000	80100	640000	320000	479601	1680881	8160000	1	0	160024	0	160048	160043	0	0	3	26	1040100	200	320000	640000	200	400000	1600000	160064	160059	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	0	0	320037	0	0	0	0	320000	6	0	32	40	0	0	0	0	5109	1	16	1	1	160061	80000	14	10	0	320000	640000	80100	160224	160065	160067	160060	160044
960204	160043	1199	0	0	0	0	0	0	0	0	0	43	0	0	0	0	160049	3	12	0	0	0	25	1040100	80100	640260	320000	80100	640000	320000	479601	1680932	8160000	1	0	160024	0	160064	160043	0	0	3	47	1040100	200	320000	640000	200	400000	1600000	160043	160043	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	0	0	320000	0	0	0	37	320000	6	0	32	35	0	0	0	0	5109	1	16	1	1	160056	80000	0	10	0	320000	640000	80100	160044	160044	160067	160044	160060
960204	160043	1199	0	0	0	0	0	1	1	0	0	43	0	1	0	2	160044	3	12	12	0	0	25	1040100	80100	640056	320000	80100	640000	320000	479601	1680415	18560012	0	0	160024	0	160043	160066	0	0	3	42	1040100	200	320000	640000	200	400000	1600000	160064	160043	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	35	0	320037	0	0	0	32	320000	6	1	36	0	0	0	0	0	5109	1	16	1	1	160043	80000	0	10	0	320000	640000	80100	160060	160044	160065	160065	160067
960204	160064	1199	0	0	0	0	0	0	0	0	0	0	0	1	0	2	160044	3	12	12	0	0	25	1040164	80100	640056	320000	80100	640000	320000	479601	1680001	18560016	1	0	160045	0	160059	160059	0	0	3	42	1040100	200	320000	640000	200	400000	1600000	160064	160043	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	0	0	320000	0	0	0	35	320000	6	1	37	40	0	0	0	0	5109	1	16	1	1	160063	80000	0	0	0	320000	640000	80100	160062	160065	160065	160065	160065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0e	0f	1e	1f	22	23	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960025	160068	1199	0	0	0	1	80	0	1	0	1	160053	12	8	19	4	0	25	1040066	80010	640024	320000	80010	640000	320000	472041	1681228	21760608	0	1	160049	0	160051	160068	2	3	51	1040010	20	320000	640000	20	400000	1600000	160068	160068	1	1	80021	10	9	10	10	80000	80000	0	10	320000	55	320050	0	50	320050	6	1	50	43	0	0	5019	0	18	16	3	0	0	6	17	160065	80000	0	10	1	320000	640000	80010	160069	160052	160069	160051	160052
960024	160051	1199	0	0	0	0	56	0	1	0	0	160053	18	8	19	0	1	25	1040034	80010	640024	320000	80010	640000	320000	472041	1681225	21760608	0	1	160031	3	160068	160068	0	3	53	1040010	20	320000	640000	20	400000	1600000	160068	160068	1	1	80021	10	9	10	10	80000	80000	0	10	320000	55	320050	0	50	320018	6	1	17	0	0	0	5019	0	17	16	2	0	0	8	17	160065	80000	0	10	0	320000	640000	80010	160052	160071	160052	160051	160069
960024	160068	1199	0	1	0	0	59	0	1	0	1	160053	17	0	19	0	0	25	1040070	80010	640056	320000	80010	640000	320000	472041	1681225	21760608	0	1	160049	0	160068	160068	0	3	51	1040010	20	320000	640000	20	400000	1600000	160050	160068	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	320018	0	17	320017	6	0	50	44	0	0	5019	0	16	16	2	0	0	7	17	160065	80000	10	10	1	320000	640000	80010	160069	160069	160416	160226	160069
960024	160068	1199	0	0	0	0	17	0	1	0	0	160053	14	0	0	4	0	25	1040066	80010	640056	320000	80010	640000	320000	472041	1681221	21760608	0	1	160049	0	160068	160051	2	3	34	1040010	20	320000	640000	20	400000	1600000	160068	160068	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	320018	0	50	320187	6	0	50	44	0	0	5019	0	17	16	1	0	0	5	16	160065	80000	10	10	1	320000	640000	80010	160069	160051	160070	160069	160051
960024	160068	1199	0	0	0	0	56	0	0	0	1	160054	13	0	0	0	0	25	1040066	80010	640056	320000	80010	640000	320000	472041	1681228	21760604	0	1	160051	0	160068	160068	2	3	53	1040010	20	320000	640000	20	400000	1600000	160050	160068	1	1	80021	10	9	10	10	80000	80000	0	10	320000	54	320050	0	17	320050	0	1	50	44	0	0	5019	0	17	16	2	0	0	17	8	160048	80000	0	10	1	320000	640000	80010	160069	160069	160052	160069	160052
960024	160068	1199	0	0	0	0	18	0	0	0	1	160053	13	8	0	1	0	25	1040066	80010	640056	320000	80010	640000	320000	472041	1680099	21760608	0	1	160049	0	160145	160051	2	3	51	1040010	20	320000	640000	20	400000	1600000	160050	160068	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	320018	0	53	320050	6	1	50	0	0	0	5019	0	17	16	2	0	0	17	15	160067	80000	10	0	1	320000	640000	80010	160069	160069	160052	160051	165158
960024	160068	1199	0	0	0	0	17	0	0	0	0	160053	12	8	0	0	1	25	1040034	80010	640060	320000	80010	640000	320000	472041	1681225	12800028	0	1	160049	0	160068	160050	0	3	51	1040010	20	320000	640000	20	400000	1600000	160068	160053	1	1	80021	10	9	10	10	80000	80000	0	10	320000	54	320050	2	18	320050	0	0	17	0	0	0	5019	0	17	16	2	0	0	14	6	160065	80000	0	10	1	320000	640000	80010	160052	160069	160052	160051	160069
960024	160068	1199	0	0	0	0	68	0	1	0	1	160053	13	8	0	0	0	25	1040066	80010	640024	320000	80010	640000	320000	472041	1681194	21760608	0	1	160049	0	160068	160068	0	61	34	1040010	20	320000	640000	20	400000	1600000	160068	160634	5	1	80021	10	9	10	10	80000	80000	0	10	320000	55	320018	1	50	320050	6	1	17	43	0	0	5019	0	17	16	2	0	0	17	17	160065	80000	10	10	0	320000	640000	80010	160052	160051	160070	160069	160051
960024	160068	1199	0	0	1	0	56	0	1	0	0	160053	13	0	0	1	1	25	1040034	80010	640024	320000	80010	640000	320000	472041	1681257	13439996	0	1	160049	0	160068	160068	134	3	34	1040010	20	320000	640000	20	400000	1600000	160068	160068	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	320050	0	50	320050	6	0	17	44	0	0	5019	0	17	16	4	1	0	16	16	160065	80000	10	10	0	320000	640000	80010	160052	160051	160052	160069	160069
960024	160068	1199	0	0	0	0	17	0	0	0	0	160036	17	8	19	0	1	25	1040066	80010	640024	320000	80010	640000	320000	472041	1681228	12800028	0	1	160049	0	160068	160068	0	3	34	1040010	20	320000	640000	20	400000	1600000	160068	160068	1	1	80021	10	9	10	10	80000	80000	1	10	320000	54	320141	1	18	320050	0	1	50	43	0	0	5019	0	17	16	3	0	0	6	16	160065	80000	10	10	0	320000	640000	80010	160069	160069	160052	160069	160069

LD4 (multiple, post-index, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations