Firestorm: LD4 (multiple, post-index, 2D) measurements

Code:

  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 13.022

Integer unit issues: 1.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.022

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
72005	29225	218	8	0	0	1	0	0	0	10	0	0	4540	29046	2	0	2	15292	13014	1000	8014	4000	1000	8000	4000	5000	20327	98055	9	24844	29106	29222	3	88	13000	4000	8000	5000	20000	29266	29201	1	1	61001	1000	1000	1	4000	0	8	4005	0	0	0	0	4007	6	1	0	8	0	0	12690	9319	6861	3063	0	82	19289	3134	3817	20	53	53	28488	1000	16531	12963	13345	4000	8000	1000	29261	29280	29220	29257	29254
72004	29368	219	2	0	0	0	0	1	1	464	0	0	4550	29147	0	4	4	15334	13014	1000	8000	4000	1000	8000	4000	5000	20313	98293	9	24724	29156	29192	3	10	13000	4000	8000	5000	20000	29215	29203	1	1	61001	1000	1000	0	4000	0	11	4000	0	0	0	0	4006	5	1	5	0	0	0	12869	9253	6813	3061	1	47	19263	3040	3812	11	54	54	28475	1000	16561	13151	13360	4000	8000	1000	29320	29373	29351	29377	29360
72004	29285	219	2	0	0	0	0	0	0	10	1	0	4743	29048	1	0	2	15277	13018	1000	8014	4000	1000	8000	4000	5000	20336	98327	10	24761	29213	29288	3	10	13000	4000	8000	5000	20000	29133	29132	1	1	61001	1000	1000	0	4000	0	11	4000	0	0	0	5	4000	5	0	7	0	0	0	12866	9078	6837	3081	0	56	19306	3101	3817	15	51	54	28478	1000	16286	12961	13293	4000	8000	1000	29220	29255	29325	29328	29231
72004	29300	219	5	1	1	0	1	0	0	63	0	0	4790	29075	0	0	0	15253	13028	1000	8022	4000	1000	8000	4000	5000	20326	98330	3	24774	29157	29207	3	10	13000	4000	8000	5000	20000	29199	29161	1	1	61001	1000	1000	0	4005	5	8	4006	0	0	1	6	4000	6	0	6	8	4	1	12921	9265	6885	3086	0	55	19265	3052	3821	15	55	62	28530	1000	16429	12930	13259	4000	8000	1000	29279	29230	29418	29208	29255
72004	29276	219	3	1	1	0	1	0	0	28	1	0	4512	29069	0	0	0	15229	13022	1000	8022	4000	1000	8000	4000	5000	20331	98377	3	24782	29237	29332	3	10	13000	4000	8000	5000	20000	29157	29208	1	1	61001	1000	1000	0	4006	6	8	4008	0	1	1	9	4002	0	1	6	0	4	2	12960	9128	6851	3088	0	46	19193	3059	3813	15	54	52	28534	1000	15952	12948	13430	4000	8000	1000	29254	29306	29201	29244	29343
72004	29429	220	6	1	1	0	1	0	0	16	1	0	4588	29063	0	0	0	15291	13026	1000	8008	4000	1000	8000	4000	5000	20336	98074	5	24808	29256	29248	3	30	13000	4000	8000	5000	20000	29139	29223	1	1	61001	1000	1000	0	4005	4	12	4008	0	0	2	4	4000	0	1	8	12	4	0	12900	9576	6881	3067	2	57	19246	3046	3824	13	55	53	28568	1000	16328	12906	13318	4000	8000	1000	29279	29257	29276	29233	29339
72004	29244	220	5	1	0	0	1	0	0	355	1	0	5002	29111	0	0	0	15374	13030	1000	8022	4000	1000	8000	4000	5000	20315	98335	3	24764	29200	29195	3	10	13000	4000	8000	5000	20000	29196	29214	1	1	61001	1000	1000	0	4006	6	0	4008	0	0	2	6	4004	0	1	8	8	4	2	12879	9166	6878	3062	0	52	19285	3078	3818	14	53	52	28735	1000	15923	12851	13323	4000	8000	1000	29352	29320	29236	29253	29222
72004	29293	219	8	1	0	0	1	0	0	174	1	0	4595	29067	0	0	0	15278	13022	1000	8028	4000	1000	8000	4000	5000	20326	98388	0	24764	29157	29187	3	10	13000	4000	8000	5000	20000	29261	29234	1	1	61001	1000	1000	0	4006	5	8	4007	0	0	1	10	4000	0	1	6	15	4	2	13329	9160	7000	3022	2	58	19248	3223	3818	13	52	54	28479	1000	16281	12922	13242	4000	8000	1000	29384	29326	29292	29330	29197
72004	29417	220	4	1	1	0	1	0	0	388	1	0	4618	29058	0	0	0	15310	13022	1000	8030	4000	1000	8000	4000	5000	20333	98405	0	24830	29218	29243	3	10	13000	4000	8000	5000	20000	29203	29212	1	1	61001	1000	1000	0	4005	6	0	4007	0	0	2	10	4002	6	1	9	8	4	1	12935	9092	6877	3068	5	60	19244	3217	3818	16	58	56	28447	1000	16456	12813	13341	4000	8000	1000	29411	29250	29232	29421	29288
72004	29333	219	6	1	1	0	1	0	0	360	1	0	4624	29154	0	0	0	15233	13008	1000	8008	4000	1000	8000	4000	5000	20326	98348	0	24795	29145	29283	3	10	13000	4000	8000	5000	20000	29218	29224	1	1	61001	1000	1000	0	4006	4	0	4007	0	0	2	10	4002	5	1	4	15	4	2	12730	9074	6909	3141	1	54	19355	3067	3814	15	52	50	28509	1000	16447	12916	13408	4000	8000	1000	29259	29317	29192	29297	29453

Count: 8

Code:

  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	4e	4f	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960205	160069	1199	1	0	1	1	0	0	0	518	0	1	0	1	160034	2	0	0	0	0	0	25	1040168	80100	640068	320000	80100	640000	320000	479601	1681236	21760752	0	0	160050	160069	160071	3	0	3	31	1040100	200	320000	640000	200	400000	1600000	160071	160069	1	1	80201	100	99	100	100	80000	80000	0	100	320014	14	0	0	320053	1	0	2	13	320040	6	1	13	43	13	0	0	0	0	5109	0	1	16	1	1	160045	80000	13	0	2	320000	640000	80100	160050	160070	160050	160070	160050
960204	160049	1199	1	1	0	0	0	0	0	119	0	1	0	3	160054	2	6	6	5	0	0	25	1040116	80100	640060	320000	80100	640000	320000	479601	1680046	11520028	0	0	160050	160069	160069	3	0	3	32	1040100	200	320000	640000	200	400000	1600000	160049	160069	1	1	80201	100	99	100	100	80000	80000	0	100	320013	15	44	0	320053	0	0	0	53	320040	6	1	53	44	13	0	0	1	0	5109	0	1	16	1	1	160066	80000	13	13	1	320000	640000	80100	160050	160070	160050	160070	160070
960204	160069	1199	1	0	1	0	0	0	0	117	0	0	0	2	160054	2	0	6	5	0	0	46	1040156	80100	640016	320000	80100	640000	320000	479601	1681436	21760752	0	0	160050	160069	160071	3	0	3	52	1040100	200	320000	640000	200	400000	1600000	160050	160069	1	1	80201	100	99	100	100	80000	80000	0	100	320013	14	44	0	320053	1	0	0	53	320040	6	1	53	44	13	0	0	0	0	5109	0	1	16	1	1	160066	80000	13	0	2	320000	640000	80100	160070	160070	160050	160070	160070
960204	160049	1199	1	0	0	0	0	0	0	113	0	1	0	3	160034	2	6	0	5	0	0	25	1040116	80100	640060	320000	80100	640000	320000	479601	1681238	11520024	0	0	160030	160069	160049	3	0	3	52	1040100	200	320000	640000	200	400000	1600000	160069	160069	1	1	80201	100	99	100	100	80000	80000	0	100	320015	14	44	0	320053	1	5	1	53	320040	6	0	53	44	13	2	0	0	0	5109	0	1	16	1	1	160046	80000	0	13	1	320000	640000	80100	160070	160070	160070	160050	160070
960204	160069	1199	1	0	0	0	0	0	0	58	0	0	0	2	160054	0	6	0	5	0	0	25	1040160	80100	640068	320000	80100	640000	320000	479601	1682007	21760752	0	0	160050	160069	160069	0	0	3	52	1040100	200	320000	640000	200	400000	1600000	160069	160049	1	1	80201	100	99	100	100	80000	80000	0	100	320013	15	44	0	320053	0	0	0	53	320000	6	1	13	44	13	0	0	1	0	5109	0	1	16	1	1	160066	80000	13	13	2	320000	640000	80100	160072	160050	160050	160070	160070
960204	160069	1199	1	0	1	0	0	0	0	122	0	0	0	0	160034	2	6	6	5	0	0	25	1040164	80100	640056	320000	80100	640000	320000	479601	1680098	21760752	0	0	160050	160069	160049	0	0	3	52	1040100	200	320000	640000	200	400000	1600000	160069	160069	1	1	80201	100	99	100	100	80000	80000	0	100	320014	13	44	0	320053	0	0	0	13	320000	6	1	53	0	13	0	0	0	0	5109	0	1	16	1	0	160046	80000	0	0	0	320000	640000	80100	160050	160070	160070	160050	160070
960204	160069	1199	1	0	0	0	0	0	0	59	0	0	0	3	160054	0	6	6	5	35	0	25	1040160	80100	640056	320000	80100	640000	320000	479601	1680098	21760752	0	0	160050	160049	160069	3	0	3	52	1040100	200	320000	640000	200	400000	1600000	160069	160069	1	1	80201	100	99	100	100	80000	80000	0	100	320013	14	44	0	320054	1	0	0	53	320000	6	0	53	44	13	0	0	0	0	5109	0	1	16	1	1	160066	80000	13	13	0	320000	640000	80100	160070	160070	160070	160070	160070
960204	160069	1199	1	1	1	0	0	0	0	119	0	1	0	0	160034	2	6	6	0	0	0	25	1040160	80100	640068	320000	80100	640296	320000	479601	1680046	21760752	0	0	160030	160049	160069	3	0	3	52	1040100	200	320000	640000	200	400000	1600000	160049	160069	1	1	80201	100	99	100	100	80000	80000	0	100	320014	14	44	0	320052	1	0	1	54	320000	6	0	13	44	13	0	0	0	0	5109	0	1	16	1	1	160066	80000	13	0	1	320000	640000	80100	160050	160050	160050	160070	160070
960204	160069	1199	1	0	1	0	0	0	0	59	0	0	0	1	160054	0	0	0	0	0	0	25	1040116	80100	640068	320000	80100	640000	320000	479601	1681262	21760752	0	0	160030	160049	160049	0	0	3	52	1040100	200	320000	640000	200	400000	1600000	160069	160069	1	1	80201	100	99	100	100	80000	80000	0	100	320015	14	44	0	320054	0	0	0	53	320040	6	0	13	0	13	0	0	0	0	5109	0	1	17	1	1	160066	80000	0	13	2	320000	640000	80100	160050	160050	160070	160070	160070
960204	160069	1199	1	1	0	1	0	0	0	59	0	0	0	2	160054	2	6	6	5	0	0	25	1040116	80100	640056	320000	80100	640000	320000	479601	1681131	21760752	0	0	160050	160071	160069	3	0	3	31	1040100	200	320000	640000	200	400000	1600000	160071	160069	1	1	80201	100	99	100	100	80000	80000	0	100	320015	13	44	0	320054	0	0	0	53	320000	6	1	53	44	13	1	0	0	0	5109	0	1	16	1	1	160066	80000	0	13	2	320000	640000	80100	160050	160070	160050	160070	160070

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	0e	0f	19	1e	1f	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960025	160057	1199	0	0	1	0	0	0	38	0	0	0	0	1	160047	0	12	12	25	1040010	80010	640044	320000	80010	640000	320000	472041	1680246	16639980	0	0	160040	160059	160043	0	0	3	39	1040010	20	320000	640000	20	400000	1600000	160043	160056	1	1	80021	10	9	10	10	80000	80000	0	10	320000	27	320032	110	24	320000	6	1	24	35	0	0	0	5019	0	0	8	16	0	5	7	160040	80000	0	0	320000	640000	80010	160060	160057	160057	160060	160057
960024	160059	1199	0	0	0	0	1	0	38	0	0	0	0	1	160044	3	0	12	25	1040010	80010	640044	320000	80010	640000	320000	472041	1680001	8160000	0	0	160040	160059	160043	0	0	3	42	1040010	20	320000	640000	20	400000	1600000	160056	160056	1	1	80021	10	9	10	10	80000	80000	0	10	320000	27	320032	0	32	320000	0	0	24	27	0	0	2	5019	0	0	5	16	0	7	5	160056	80000	0	10	320000	640000	80010	160044	160060	160044	160060	160057
960024	160056	1199	0	0	0	0	0	0	37	0	1	0	0	1	160041	0	12	0	25	1040066	80010	640304	320130	80010	640000	320000	472041	1680001	16639980	0	0	160040	160056	160043	0	0	3	39	1040010	20	320000	640000	20	400000	1600000	160056	160056	1	1	80021	10	9	10	10	80000	80000	0	10	320000	27	320032	127	27	320024	0	0	24	35	0	0	0	5019	5	0	6	16	0	7	4	160053	80000	10	10	320000	640000	80010	160060	160044	160046	160057	160060
960024	160056	1199	0	0	0	0	1	0	122	0	0	0	0	0	160044	0	0	0	25	1040066	80010	640044	320000	80010	640000	320000	472041	1680242	16639980	0	5	160040	160059	160059	0	0	3	26	1040010	20	320000	640000	20	400000	1600000	160059	160056	1	1	80021	10	9	10	10	80000	80000	0	10	320000	27	320024	0	32	320032	6	1	0	0	0	0	0	5019	0	0	8	16	0	6	4	160040	80000	10	10	320000	640000	80010	160060	160044	160044	160057	160057
960024	160061	1199	0	0	0	0	0	4	9	0	0	0	0	1	160044	3	0	12	25	1040010	80010	640044	320000	80010	640000	320000	472041	1680001	16639980	1	0	160040	160056	160043	0	0	3	42	1040010	20	320000	640000	20	400000	1600000	160056	160046	2	1	80021	10	9	10	10	80000	80000	0	10	320000	0	320032	0	33	320032	6	1	32	35	0	0	0	5019	0	0	6	16	0	4	6	160056	80000	10	0	320000	640000	80010	160060	160044	160044	160044	160057
960024	160056	1199	0	0	0	0	0	0	38	0	1	0	0	0	160044	3	12	12	25	1040010	80010	640044	320000	80010	640000	320000	472041	1680406	16639980	0	0	160024	160060	160059	0	0	3	42	1040010	20	320000	640000	20	400000	1600000	160059	160043	1	1	80021	10	9	10	10	80000	80000	0	10	320128	27	320024	116	32	320000	0	0	24	35	0	0	0	5019	0	0	5	16	0	6	6	160040	80000	10	0	320000	640000	80010	160060	160060	160044	160060	160057
960024	160056	1198	0	0	0	0	0	0	38	0	0	0	0	1	160028	0	12	12	45	1040066	80010	640000	320000	80010	640000	320000	472041	1680408	8160000	0	0	160037	160056	160043	0	0	3	42	1040010	20	320000	640000	20	400000	1600000	160059	160043	1	1	80021	10	9	10	10	80000	80000	0	10	320000	27	320000	0	32	320000	5	0	0	35	0	0	0	5019	0	4	6	16	0	4	6	160042	80000	0	6	320000	640000	80010	160044	160057	160044	160060	160059
960024	160059	1198	0	0	1	0	0	0	38	0	0	0	0	0	160044	3	0	12	25	1040054	80010	640304	320130	80010	640000	320000	472041	1680308	8478696	0	0	160037	160043	160059	0	0	3	26	1040010	20	320000	640000	20	400000	1600000	160059	160043	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	320024	146	0	320024	6	0	24	0	0	0	0	5019	0	0	6	16	0	6	6	160053	80000	10	0	320000	640000	80010	160060	160060	160057	160060	160057
960024	160056	1198	0	0	1	0	0	0	48	0	0	0	0	1	160044	3	12	12	25	1040054	80010	640044	320000	80010	640000	320000	472041	1680001	16639980	0	0	160024	160059	160059	0	0	3	42	1040010	20	320000	640000	20	400000	1600000	160059	160056	1	1	80021	10	9	10	10	80000	80000	0	10	320000	27	320000	0	0	320024	6	1	24	27	0	0	0	5019	0	0	4	16	0	5	7	160040	80000	10	0	320000	640000	80010	160044	160044	160044	160060	160057
960024	160059	1199	0	0	1	0	0	0	38	0	1	0	0	1	160041	3	12	0	25	1040054	80010	640000	320000	80010	640000	320000	472041	1680001	8160000	0	0	160041	160059	160043	0	0	3	39	1040010	20	320676	640528	20	400190	1600000	160056	160056	1	1	80021	10	9	10	10	80000	80000	1	10	320000	27	320000	0	105	320080	0	0	24	27	0	0	0	5019	0	0	7	16	0	7	6	160053	80000	10	10	320000	640000	80010	160060	160060	160044	160044	160057

LD4 (multiple, post-index, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations