Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8 nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 1 mov x1, 2 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 6.000
Issues: 7.008
Integer unit issues: 1.000
Load/store unit issues: 2.000
SIMD/FP unit issues: 4.008
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | 09 | l2 tlb miss instruction (0a) | 0e | 0f | 1e | 22 | 24 | 3a | 3f | 43 | 46 | 49 | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd load (98) | inst ldst (9b) | 9d | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
66005 | 29359 | 220 | 23 | 0 | 22 | 0 | 1 | 5 | 1 | 0 | 4583 | 28865 | 0 | 1 | 0 | 16951 | 7012 | 1000 | 4008 | 2000 | 1000 | 4000 | 2000 | 5000 | 10000 | 47536 | 9 | 22989 | 29148 | 29297 | 3 | 10 | 7000 | 2000 | 4000 | 3000 | 8000 | 29092 | 29187 | 1 | 1 | 61001 | 1000 | 1000 | 1 | 2000 | 0 | 2000 | 1 | 0 | 2 | 2000 | 4 | 0 | 0 | 0 | 12812 | 9247 | 6908 | 3087 | 9 | 72 | 20194 | 3041 | 3831 | 12 | 56 | 51 | 28422 | 1000 | 16428 | 13357 | 14311 | 2000 | 4000 | 1000 | 29240 | 29363 | 29342 | 29286 | 29253 |
66004 | 29178 | 220 | 16 | 0 | 24 | 1 | 0 | 7 | 0 | 0 | 4527 | 28807 | 0 | 0 | 0 | 16956 | 7004 | 1000 | 4000 | 2000 | 1000 | 4000 | 2000 | 5000 | 10000 | 47488 | 6 | 22962 | 29008 | 29298 | 3 | 10 | 7000 | 2000 | 4000 | 3000 | 8000 | 29149 | 29117 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 2000 | 0 | 2002 | 0 | 0 | 0 | 2002 | 0 | 0 | 0 | 4 | 12841 | 9328 | 6839 | 3057 | 7 | 56 | 20039 | 3134 | 3829 | 14 | 49 | 50 | 28413 | 1000 | 16454 | 13257 | 14350 | 2000 | 4000 | 1000 | 29232 | 29304 | 29165 | 29266 | 29381 |
66004 | 29249 | 221 | 18 | 0 | 24 | 0 | 0 | 6 | 0 | 0 | 4586 | 28709 | 0 | 0 | 0 | 16833 | 7000 | 1000 | 4000 | 2000 | 1000 | 4000 | 2000 | 5000 | 10000 | 47520 | 9 | 22972 | 28955 | 29297 | 3 | 10 | 7000 | 2000 | 4000 | 3000 | 8000 | 29150 | 29208 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 2000 | 0 | 2002 | 0 | 0 | 0 | 2000 | 4 | 0 | 2 | 0 | 13003 | 9204 | 6802 | 2971 | 7 | 51 | 20057 | 3105 | 3824 | 16 | 57 | 54 | 28471 | 1000 | 16271 | 13240 | 14332 | 2000 | 4000 | 1000 | 29252 | 29191 | 29351 | 29398 | 29261 |
66004 | 29312 | 219 | 22 | 0 | 20 | 0 | 0 | 6 | 0 | 0 | 4515 | 28843 | 0 | 0 | 0 | 16894 | 7000 | 1000 | 4000 | 2000 | 1000 | 4000 | 2000 | 5000 | 10000 | 47506 | 1 | 23000 | 29106 | 29170 | 3 | 10 | 7000 | 2000 | 4000 | 3000 | 8000 | 29077 | 29175 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 2000 | 4 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 2 | 4 | 12749 | 9457 | 6837 | 3158 | 10 | 49 | 20192 | 3086 | 3829 | 14 | 47 | 52 | 28425 | 1000 | 16473 | 13428 | 14436 | 2000 | 4000 | 1000 | 29232 | 29254 | 29249 | 29346 | 29234 |
66004 | 29266 | 219 | 22 | 0 | 21 | 0 | 0 | 0 | 0 | 0 | 4589 | 28933 | 0 | 0 | 0 | 16897 | 7000 | 1000 | 4000 | 2000 | 1000 | 4000 | 2000 | 5000 | 10002 | 47520 | 2 | 23018 | 29138 | 29313 | 3 | 10 | 7000 | 2000 | 4000 | 3000 | 8000 | 29214 | 29138 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 2000 | 4 | 2000 | 1 | 0 | 0 | 2000 | 0 | 0 | 2 | 4 | 12712 | 9274 | 6794 | 3182 | 7 | 58 | 20106 | 3124 | 3831 | 11 | 48 | 51 | 28426 | 1000 | 16288 | 13162 | 14221 | 2000 | 4000 | 1000 | 29264 | 29296 | 29321 | 29332 | 28921 |
66004 | 29238 | 220 | 16 | 0 | 20 | 0 | 0 | 0 | 1 | 0 | 4758 | 28772 | 0 | 0 | 0 | 16907 | 7008 | 1000 | 4008 | 2000 | 1000 | 4000 | 2000 | 5000 | 10000 | 47508 | 2 | 22992 | 29142 | 29250 | 3 | 28 | 7000 | 2000 | 4000 | 3000 | 8000 | 29224 | 29165 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 2000 | 4 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 0 | 6 | 12884 | 9240 | 6861 | 3056 | 9 | 58 | 20193 | 3157 | 3822 | 17 | 55 | 47 | 28376 | 1000 | 16176 | 13467 | 14356 | 2000 | 4000 | 1000 | 29339 | 29196 | 29281 | 29309 | 29298 |
66004 | 29246 | 219 | 17 | 0 | 20 | 0 | 0 | 4 | 1 | 0 | 4551 | 28821 | 0 | 0 | 0 | 16857 | 7008 | 1000 | 4000 | 2000 | 1000 | 4000 | 2000 | 5000 | 10000 | 47548 | 2 | 23037 | 29261 | 29217 | 3 | 10 | 7000 | 2000 | 4000 | 3000 | 8000 | 29233 | 29109 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 2000 | 4 | 2000 | 0 | 0 | 0 | 2000 | 2 | 0 | 0 | 4 | 13026 | 9191 | 6818 | 3030 | 11 | 54 | 20126 | 3119 | 3829 | 11 | 50 | 59 | 28603 | 1000 | 16041 | 13037 | 14068 | 2000 | 4000 | 1000 | 29387 | 29348 | 29258 | 29204 | 29277 |
66004 | 29268 | 220 | 18 | 0 | 18 | 1 | 0 | 5 | 0 | 0 | 4529 | 28797 | 0 | 1 | 1 | 16971 | 7000 | 1000 | 4008 | 2000 | 1000 | 4000 | 2000 | 5000 | 10000 | 47392 | 3 | 22978 | 29152 | 29215 | 3 | 10 | 7000 | 2000 | 4000 | 3000 | 8000 | 29188 | 29145 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 2000 | 4 | 2000 | 0 | 0 | 0 | 2000 | 4 | 0 | 0 | 4 | 12743 | 9117 | 6893 | 3024 | 4 | 54 | 20094 | 2988 | 3834 | 17 | 54 | 56 | 28398 | 1000 | 16496 | 13438 | 14444 | 2000 | 4000 | 1000 | 29261 | 29372 | 29402 | 29228 | 29267 |
66004 | 29322 | 216 | 28 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 4570 | 28806 | 0 | 0 | 0 | 16916 | 7012 | 1000 | 4008 | 2000 | 1000 | 4000 | 2000 | 5000 | 10000 | 47570 | 1 | 23103 | 29209 | 29238 | 3 | 10 | 7000 | 2000 | 4000 | 3000 | 8000 | 29097 | 29167 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 2000 | 4 | 2000 | 0 | 0 | 0 | 2000 | 0 | 0 | 0 | 0 | 12933 | 9265 | 6895 | 2970 | 12 | 63 | 20066 | 3191 | 3823 | 15 | 59 | 50 | 28473 | 1000 | 16100 | 13344 | 14235 | 2000 | 4000 | 1000 | 29311 | 29166 | 29259 | 29324 | 29186 |
66004 | 29251 | 220 | 25 | 0 | 19 | 1 | 0 | 6 | 0 | 0 | 4620 | 28743 | 0 | 0 | 0 | 16865 | 7008 | 1000 | 4008 | 2000 | 1000 | 4000 | 2000 | 5000 | 10000 | 47424 | 6 | 22961 | 29135 | 29186 | 3 | 10 | 7000 | 2000 | 4000 | 3000 | 8000 | 29201 | 29135 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 2000 | 4 | 2000 | 0 | 0 | 0 | 2000 | 2 | 0 | 0 | 4 | 12849 | 9416 | 6851 | 3021 | 8 | 52 | 19983 | 3133 | 3827 | 12 | 54 | 53 | 28430 | 1000 | 16233 | 13288 | 14305 | 2000 | 4000 | 1000 | 29320 | 29253 | 29247 | 29280 | 29291 |
Count: 8
Code:
ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8 ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8 ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8 ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8 ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8 ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8 ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8 ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0008
retire uop (01) | cycle (02) | 03 | 09 | 0e | 0f | 1e | 1f | 22 | 3a | 3f | 43 | 46 | 49 | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | simd prf full (72) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
480205 | 80070 | 600 | 1 | 0 | 0 | 52 | 0 | 0 | 0 | 80034 | 13 | 15 | 28 | 0 | 25 | 560128 | 80100 | 320072 | 160000 | 80100 | 320000 | 160000 | 480499 | 960679 | 10880000 | 1 | 80045 | 80064 | 80064 | 0 | 3 | 31 | 560100 | 200 | 160000 | 320000 | 200 | 240000 | 640000 | 80064 | 80049 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 160000 | 2 | 49 | 160045 | 0 | 48 | 160045 | 6 | 1 | 13 | 0 | 5109 | 1 | 17 | 1 | 1 | 80062 | 80000 | 6 | 0 | 160000 | 320000 | 80100 | 80050 | 80065 | 80050 | 80065 | 80050 |
480204 | 80064 | 599 | 0 | 0 | 0 | 52 | 0 | 1 | 1 | 80049 | 10 | 15 | 29 | 0 | 25 | 560172 | 80100 | 320072 | 160000 | 80100 | 320000 | 160000 | 480499 | 960032 | 6080020 | 1 | 80033 | 80064 | 80049 | 0 | 3 | 31 | 560100 | 200 | 160000 | 320000 | 200 | 240000 | 640000 | 80064 | 80064 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 160000 | 0 | 49 | 160046 | 0 | 45 | 160045 | 6 | 0 | 45 | 0 | 5109 | 1 | 17 | 1 | 1 | 80061 | 80000 | 6 | 6 | 160000 | 320000 | 80100 | 80065 | 80065 | 80065 | 80065 | 80065 |
480204 | 80064 | 600 | 0 | 0 | 0 | 51 | 0 | 1 | 1 | 80049 | 13 | 0 | 28 | 0 | 25 | 560172 | 80100 | 320028 | 160000 | 80100 | 320000 | 160000 | 480499 | 960673 | 6080020 | 1 | 80045 | 80064 | 80049 | 0 | 3 | 46 | 560100 | 200 | 160000 | 320000 | 200 | 240000 | 640000 | 80064 | 80064 | 1 | 1 | 80202 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 160000 | 0 | 49 | 160045 | 0 | 13 | 160046 | 6 | 1 | 13 | 0 | 5109 | 1 | 17 | 1 | 1 | 80046 | 80000 | 6 | 6 | 160000 | 320000 | 80100 | 80065 | 80065 | 80065 | 80050 | 80050 |
480204 | 80049 | 600 | 0 | 0 | 0 | 55 | 0 | 1 | 1 | 80034 | 10 | 0 | 28 | 0 | 25 | 560172 | 80100 | 320072 | 160000 | 80100 | 320000 | 160000 | 480499 | 960666 | 6080020 | 0 | 80045 | 80064 | 80064 | 0 | 3 | 46 | 560100 | 200 | 160000 | 320000 | 200 | 240000 | 640000 | 80064 | 80049 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 160000 | 0 | 49 | 160045 | 0 | 46 | 160013 | 6 | 1 | 46 | 41 | 5109 | 1 | 17 | 1 | 1 | 80061 | 80000 | 6 | 6 | 160000 | 320000 | 80100 | 80069 | 80065 | 80065 | 80065 | 80065 |
480204 | 80049 | 599 | 0 | 0 | 0 | 51 | 0 | 1 | 1 | 80034 | 10 | 15 | 29 | 0 | 25 | 560128 | 80100 | 320068 | 160000 | 80100 | 320000 | 160000 | 480499 | 960679 | 10880000 | 1 | 80045 | 80049 | 80049 | 0 | 3 | 46 | 560100 | 200 | 160000 | 320000 | 200 | 240000 | 640000 | 80064 | 80049 | 2 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 160000 | 0 | 49 | 160014 | 0 | 13 | 160046 | 6 | 0 | 45 | 0 | 5109 | 1 | 17 | 1 | 1 | 80061 | 80000 | 6 | 6 | 160000 | 320000 | 80100 | 80065 | 80065 | 80065 | 80065 | 80065 |
480204 | 80064 | 599 | 0 | 0 | 0 | 51 | 0 | 0 | 1 | 80049 | 14 | 14 | 29 | 0 | 25 | 560168 | 80100 | 320072 | 160000 | 80100 | 320000 | 160000 | 480499 | 960679 | 6080020 | 1 | 80045 | 80064 | 80064 | 0 | 3 | 46 | 560100 | 200 | 160000 | 320000 | 200 | 240000 | 640000 | 80064 | 80049 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 160000 | 4 | 49 | 160014 | 0 | 60 | 160045 | 0 | 0 | 45 | 0 | 5109 | 1 | 17 | 1 | 1 | 80061 | 80000 | 0 | 0 | 160000 | 320000 | 80100 | 80065 | 80065 | 80065 | 80050 | 80065 |
480204 | 80064 | 599 | 0 | 0 | 1 | 52 | 0 | 1 | 1 | 80049 | 10 | 0 | 29 | 0 | 47 | 560172 | 80100 | 320028 | 160000 | 80100 | 320000 | 160000 | 480499 | 960701 | 6080020 | 1 | 80030 | 80049 | 80049 | 0 | 3 | 31 | 560100 | 200 | 160000 | 320000 | 200 | 240000 | 640000 | 80049 | 80064 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 160000 | 0 | 0 | 160045 | 0 | 13 | 160045 | 6 | 0 | 45 | 41 | 5109 | 1 | 17 | 1 | 1 | 80061 | 80000 | 6 | 6 | 160000 | 320000 | 80100 | 80065 | 80065 | 80065 | 80065 | 80050 |
480204 | 80049 | 600 | 0 | 0 | 0 | 51 | 0 | 0 | 0 | 80049 | 11 | 15 | 28 | 0 | 25 | 560128 | 80100 | 320068 | 160000 | 80100 | 320000 | 160000 | 480499 | 960674 | 6080020 | 1 | 80045 | 80064 | 80049 | 0 | 3 | 46 | 560100 | 200 | 160000 | 320000 | 200 | 240000 | 640000 | 80064 | 80064 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 160000 | 0 | 49 | 160045 | 1 | 13 | 160013 | 6 | 1 | 13 | 41 | 5109 | 1 | 17 | 1 | 1 | 80046 | 80000 | 0 | 6 | 160000 | 320000 | 80100 | 80065 | 80050 | 80050 | 80050 | 80065 |
480204 | 80064 | 599 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | 80034 | 11 | 0 | 29 | 0 | 25 | 560172 | 80100 | 320072 | 160000 | 80100 | 320000 | 160000 | 480499 | 960668 | 10880000 | 1 | 80030 | 80064 | 80049 | 0 | 3 | 46 | 560100 | 200 | 160000 | 320000 | 200 | 240000 | 640000 | 80049 | 80049 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 160000 | 0 | 49 | 160046 | 0 | 46 | 160046 | 0 | 1 | 13 | 0 | 5109 | 1 | 17 | 1 | 1 | 80061 | 80000 | 6 | 6 | 160000 | 320000 | 80100 | 80056 | 80065 | 80065 | 80050 | 80065 |
480204 | 80064 | 600 | 0 | 1 | 1 | 60 | 0 | 0 | 0 | 80034 | 10 | 0 | 0 | 0 | 25 | 560172 | 80100 | 320028 | 160000 | 80100 | 320000 | 160000 | 480499 | 960032 | 6080020 | 1 | 80030 | 80064 | 80064 | 0 | 3 | 31 | 560100 | 200 | 160000 | 320000 | 200 | 240000 | 640000 | 80064 | 80064 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 1 | 100 | 160000 | 0 | 49 | 160045 | 0 | 45 | 160045 | 0 | 1 | 45 | 41 | 5109 | 1 | 17 | 1 | 1 | 80061 | 80000 | 0 | 0 | 160000 | 320000 | 80100 | 80053 | 80065 | 80065 | 80065 | 80065 |
Result (median cycles for code divided by count): 1.0008
retire uop (01) | cycle (02) | 03 | 09 | 0e | 0f | 1e | 22 | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | simd prf full (72) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | branch mispred nonspec (cb) | cf | d0 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | e7 | ? int output thing (e9) | ea | eb | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
480025 | 80060 | 599 | 0 | 0 | 1 | 35 | 1 | 80045 | 2 | 12 | 12 | 0 | 25 | 560010 | 80010 | 320000 | 160000 | 80010 | 320000 | 160000 | 480049 | 960330 | 4159992 | 1 | 80023 | 80042 | 80060 | 0 | 0 | 3 | 24 | 560010 | 20 | 160000 | 320000 | 20 | 240000 | 640000 | 80060 | 80042 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 1 | 10 | 160000 | 33 | 160030 | 0 | 0 | 160029 | 6 | 1 | 0 | 33 | 0 | 5019 | 0 | 4 | 17 | 6 | 4 | 80057 | 1 | 80055 | 10 | 11 | 160000 | 320000 | 80010 | 80061 | 80061 | 80043 | 80061 | 80061 |
480024 | 80060 | 599 | 0 | 0 | 1 | 36 | 1 | 80045 | 2 | 12 | 0 | 0 | 25 | 560082 | 80010 | 320000 | 160000 | 80010 | 320000 | 160000 | 480049 | 959996 | 9600000 | 1 | 80023 | 80042 | 80060 | 0 | 0 | 3 | 42 | 560010 | 20 | 160000 | 320000 | 20 | 240000 | 640000 | 80060 | 80060 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 160000 | 33 | 160000 | 0 | 29 | 160000 | 0 | 1 | 29 | 0 | 0 | 5019 | 0 | 6 | 17 | 6 | 6 | 80039 | 0 | 80055 | 0 | 10 | 160000 | 320000 | 80010 | 80061 | 80061 | 80061 | 80061 | 80043 |
480024 | 80060 | 599 | 0 | 0 | 0 | 0 | 1 | 80027 | 2 | 12 | 12 | 0 | 25 | 560541 | 80010 | 320000 | 160000 | 80010 | 320000 | 160000 | 480049 | 975759 | 9600000 | 1 | 80590 | 80060 | 80060 | 0 | 0 | 3 | 42 | 560416 | 20 | 160000 | 320000 | 20 | 240381 | 640000 | 80060 | 80060 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 160000 | 0 | 160029 | 0 | 1060 | 160030 | 6 | 1 | 30 | 33 | 0 | 5019 | 0 | 3 | 17 | 7 | 6 | 80057 | 0 | 80000 | 10 | 0 | 160000 | 320000 | 80010 | 80061 | 80061 | 80061 | 80061 | 80061 |
480024 | 80059 | 600 | 0 | 0 | 0 | 35 | 0 | 80045 | 2 | 0 | 12 | 0 | 25 | 560082 | 80010 | 320072 | 160000 | 80010 | 320000 | 160000 | 480049 | 960338 | 9600000 | 1 | 80041 | 80060 | 80060 | 0 | 0 | 3 | 42 | 560010 | 20 | 160000 | 320000 | 20 | 240000 | 640000 | 80042 | 80060 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 160000 | 33 | 160000 | 0 | 0 | 160029 | 6 | 0 | 30 | 33 | 0 | 5019 | 0 | 6 | 17 | 7 | 6 | 80057 | 0 | 80000 | 10 | 10 | 160000 | 320000 | 80010 | 80061 | 80061 | 80061 | 80043 | 80061 |
480024 | 80060 | 599 | 0 | 0 | 0 | 35 | 1 | 80045 | 2 | 0 | 12 | 0 | 25 | 560010 | 80010 | 320072 | 160000 | 80010 | 320000 | 160152 | 480049 | 960594 | 4439852 | 1 | 80041 | 80060 | 80060 | 0 | 0 | 3 | 42 | 560010 | 20 | 160000 | 320000 | 20 | 240000 | 640000 | 80060 | 80060 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 1 | 10 | 160000 | 33 | 160029 | 0 | 29 | 160029 | 6 | 1 | 29 | 33 | 0 | 5019 | 0 | 4 | 17 | 6 | 6 | 80057 | 1 | 80000 | 10 | 10 | 160000 | 320000 | 80010 | 80061 | 80048 | 80061 | 80060 | 80061 |
480024 | 80060 | 600 | 0 | 0 | 0 | 35 | 1 | 80045 | 0 | 12 | 12 | 0 | 25 | 560010 | 80010 | 320072 | 160000 | 80010 | 320000 | 160000 | 480049 | 960331 | 4159992 | 1 | 80041 | 80060 | 80042 | 0 | 0 | 3 | 42 | 560010 | 20 | 160000 | 320000 | 20 | 240000 | 640000 | 80042 | 80060 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 160000 | 0 | 160030 | 0 | 30 | 160030 | 6 | 1 | 29 | 0 | 0 | 5019 | 0 | 6 | 17 | 7 | 6 | 80039 | 0 | 80000 | 10 | 10 | 160000 | 320000 | 80010 | 80043 | 80061 | 80061 | 80061 | 80061 |
480024 | 80060 | 600 | 0 | 0 | 0 | 35 | 0 | 80027 | 2 | 12 | 12 | 0 | 25 | 560082 | 80010 | 320072 | 160000 | 80010 | 320000 | 160000 | 480049 | 960331 | 9600000 | 1 | 80041 | 80060 | 80060 | 0 | 0 | 3 | 42 | 560010 | 20 | 160000 | 320000 | 20 | 240000 | 640000 | 80042 | 80060 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 160000 | 33 | 160030 | 0 | 33 | 160000 | 0 | 1 | 0 | 0 | 0 | 5019 | 0 | 5 | 17 | 3 | 4 | 80042 | 1 | 80000 | 10 | 10 | 160000 | 320000 | 80010 | 80061 | 80061 | 80061 | 80061 | 80061 |
480024 | 80042 | 600 | 0 | 0 | 0 | 36 | 1 | 80027 | 2 | 12 | 12 | 0 | 25 | 560082 | 80010 | 320072 | 160000 | 80010 | 320000 | 160000 | 480049 | 960338 | 9600008 | 1 | 80041 | 80060 | 80060 | 0 | 0 | 3 | 24 | 560010 | 20 | 160000 | 320000 | 20 | 240000 | 640000 | 80060 | 80060 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 1 | 10 | 160000 | 33 | 160030 | 0 | 30 | 160030 | 0 | 1 | 30 | 33 | 0 | 5019 | 0 | 6 | 17 | 4 | 3 | 80057 | 1 | 80000 | 10 | 10 | 160000 | 320000 | 80010 | 80061 | 80043 | 80061 | 80043 | 80061 |
480024 | 80060 | 600 | 0 | 0 | 0 | 35 | 1 | 80045 | 2 | 12 | 12 | 0 | 25 | 560010 | 80010 | 320000 | 160000 | 80010 | 320000 | 160000 | 480049 | 959996 | 9600000 | 1 | 80041 | 80045 | 80060 | 0 | 0 | 3 | 42 | 560010 | 20 | 160000 | 320000 | 20 | 240000 | 640000 | 80060 | 80060 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 160000 | 33 | 160030 | 1 | 30 | 160000 | 0 | 1 | 0 | 0 | 0 | 5019 | 0 | 3 | 17 | 4 | 3 | 80057 | 1 | 80000 | 10 | 10 | 160000 | 320000 | 80010 | 80061 | 80043 | 80061 | 80061 | 80061 |
480024 | 80060 | 600 | 0 | 0 | 0 | 35 | 1 | 80045 | 2 | 12 | 12 | 0 | 25 | 560082 | 80010 | 320072 | 160000 | 80010 | 320000 | 160000 | 480049 | 960330 | 9600000 | 1 | 80041 | 80060 | 80060 | 0 | 0 | 3 | 42 | 560010 | 20 | 160000 | 320000 | 20 | 240000 | 640432 | 80052 | 80060 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 160000 | 33 | 160030 | 0 | 30 | 160030 | 6 | 1 | 0 | 33 | 0 | 5019 | 0 | 4 | 17 | 4 | 4 | 80057 | 1 | 80000 | 10 | 10 | 160000 | 320000 | 80010 | 80043 | 80061 | 80061 | 80061 | 80061 |