Firestorm: LD4 (multiple, post-index, 4S) measurements

Code:

  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 13.018

Integer unit issues: 1.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.018

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	1f	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
72005	29282	220	3	0	0	0	0	0	0	0	0	0	0	4552	29048	0	4	0	15290	13000	1000	8000	4000	1000	8000	4000	5000	20330	98441	7	0	0	24736	29166	29209	3	10	13000	4000	8000	5000	20000	29315	29202	1	1	61001	1000	1000	0	4000	8	4006	0	0	6	4006	5	1	0	0	12785	9116	6872	3119	0	52	19292	3130	3818	9	59	40	28504	1000	16557	13127	13332	4000	8000	1000	29283	29290	29257	29263	29299
72004	29235	219	0	0	0	0	0	0	0	12	0	0	0	4522	29060	2	0	4	15238	13020	1000	8018	4000	1000	8000	4000	5000	20350	98444	0	0	0	24804	29192	29271	3	10	13000	4000	8000	5000	20000	29169	29197	1	1	61001	1000	1000	1	4000	8	4006	0	0	6	4006	5	1	0	12	12744	9097	6876	3082	0	43	19172	3076	3815	19	52	50	28549	1000	16397	12985	13398	4000	8000	1000	29288	29289	29272	29326	29211
72004	29279	219	0	0	0	0	0	0	0	0	0	0	0	4500	29135	0	0	0	15260	13014	1000	8020	4000	1000	8000	4000	5000	20329	98249	2	0	0	24722	29170	29184	3	10	13000	4000	8000	5000	20000	29132	29202	1	1	61001	1000	1000	0	4000	12	4006	0	0	6	4006	5	1	0	12	12884	9101	6870	3129	0	38	19315	3074	3814	10	57	47	28475	1000	16347	13034	13268	4000	8000	1000	29388	29237	29295	29244	29174
72004	29338	219	1	0	0	0	0	0	0	12	0	1	0	4663	29059	0	0	0	15263	13020	1000	8018	4000	1000	8000	4000	5000	20330	98289	5	0	0	24698	29119	29281	3	10	13000	4000	8000	5000	20000	29170	29278	1	1	61001	1000	1000	0	4000	11	4006	0	0	6	4004	0	1	5	0	12940	9069	6852	3068	0	39	19276	3037	3825	13	54	44	28498	1000	16431	12937	13287	4000	8000	1000	29305	29334	29275	29352	29254
72004	29236	220	0	0	0	0	0	0	0	10	0	0	0	4479	29015	0	0	0	15279	13020	1000	8020	4000	1000	8000	4000	5000	20319	98004	5	0	0	24770	29147	29275	3	10	13000	4000	8000	5000	20000	29243	29164	1	1	61001	1000	1000	0	4000	0	4006	0	0	6	4006	6	0	0	11	12927	9022	6873	3073	0	42	19311	3002	3819	12	57	49	28618	1000	16521	13061	13280	4000	8000	1000	29328	29302	29251	29259	29265
72004	29276	220	0	0	0	0	0	0	0	12	0	0	0	4537	29054	0	4	0	15332	13018	1000	8014	4000	1000	8000	4000	5000	20305	98295	6	0	0	24745	29191	29323	3	10	13000	4000	8000	5000	20000	29279	29218	1	1	61001	1000	1000	0	4000	8	4006	0	0	6	4005	5	1	3	0	12820	9104	6953	3052	0	46	19227	3045	3822	12	56	53	28475	1000	16525	12949	13148	4000	8000	1000	29307	29258	29333	29292	29210
72004	29198	219	0	0	0	0	0	0	0	8	0	0	0	4541	29099	2	0	0	15312	13018	1000	8014	4000	1000	8000	4000	5000	20334	98411	5	0	0	24769	29093	29206	3	10	13000	4000	8000	5000	20000	29231	29161	1	1	61001	1000	1000	0	4000	12	4000	0	0	0	4000	5	1	6	8	12795	9209	6863	3056	0	47	19297	3059	3821	14	57	48	28455	1000	16442	12988	13193	4000	8000	1000	29243	29322	29266	29299	29251
72004	29238	219	0	0	0	0	0	0	0	18	0	1	0	4576	29056	0	0	4	15321	13014	1000	8014	4000	1000	8000	4000	5000	20318	98072	3	0	0	24757	29188	29267	3	10	13000	4000	8000	5000	20000	29216	29178	1	1	61001	1000	1000	0	4000	12	4006	0	0	9	4006	5	1	3	11	12786	9083	6862	3054	0	42	19222	3075	3816	12	61	54	28468	1000	16423	13024	13290	4000	8000	1000	29259	29310	29308	29208	29268
72004	29320	219	0	0	1	0	0	0	0	12	0	0	0	4537	29033	0	0	0	15302	13014	1000	8018	4000	1000	8000	4000	5000	20308	98296	3	0	0	24708	29204	29252	3	10	13000	4000	8000	5000	20000	29178	29178	1	1	61001	1000	1000	0	4000	11	4006	0	0	6	4000	0	0	0	0	12954	9006	6842	3079	0	45	19327	3067	3819	14	57	51	28487	1000	16471	12949	13338	4000	8000	1000	29287	29326	29177	29300	29272
72004	29316	219	0	0	1	0	0	1	0	10	0	1	0	4545	29070	0	0	0	15212	13000	1000	8020	4000	1000	8000	4000	5000	20311	98107	0	0	0	24762	29215	29298	3	10	13000	4000	8000	5000	20000	29158	29197	1	1	61001	1000	1000	0	4000	8	4006	0	0	3	4003	6	1	6	8	12877	9085	6837	3088	0	40	19299	3090	3816	14	67	54	28442	1000	16488	12723	13179	4000	8000	1000	29315	29227	29237	29246	29268

Count: 8

Code:

  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960205	160069	1199	1	1	0	0	0	0	0	0	58	0	0	0	0	3	160034	2	17	17	1	0	25	1040116	80100	640056	320000	80100	640000	320000	479601	1680982	21760156	1	0	160046	0	160065	160065	0	164	3	48	1040100	200	320000	640000	200	400000	1600000	160065	160065	1	1	80201	100	99	100	100	80000	80000	0	100	320014	13	43	0	320052	0	0	0	52	320039	6	1	52	43	13	1	0	0	5109	1	16	1	1	160046	80000	0	9	1	320000	640000	80100	160066	160066	160066	160066	160050
960204	160065	1199	1	2	0	0	0	1	4	0	478	0	0	0	0	1	160050	2	17	17	1	0	271	1041392	80100	640056	320000	80302	641600	321084	479601	1680979	21760152	1	1	160397	0	160049	160065	0	0	3	48	1040100	200	320000	640000	200	400000	1600000	160065	160065	1	1	80201	100	99	100	100	80000	80000	0	100	320013	13	43	0	320121	1	0	0	13	320039	6	1	52	43	13	0	0	0	5109	1	16	1	3	160046	80000	9	9	1	320000	640000	80100	160050	160050	160066	160050	160050
960204	160065	1199	1	2	0	0	0	0	0	0	13	0	1	0	0	2	160181	2	17	0	1	0	25	1040116	80100	640052	320000	80100	640000	320000	479601	1680978	21760152	1	0	160046	0	160049	160067	0	0	3	32	1040100	200	320000	640000	200	400000	1600000	160065	160065	1	1	80201	100	99	100	100	80000	80000	0	100	320013	14	0	0	320052	3	0	0	52	320039	0	1	52	0	13	1	0	0	5109	1	16	1	1	160062	80000	9	9	1	320000	640000	80100	160066	160050	160066	160066	160050
960204	160065	1199	1	0	0	1	0	0	0	0	58	0	0	0	0	3	160050	2	17	17	1	0	25	1040168	80100	640328	320000	80100	640000	320000	479601	1680098	21760156	1	0	160164	0	160049	160049	0	0	3	32	1040100	200	320000	640000	200	400000	1600000	160065	160049	1	1	80201	100	99	100	100	80000	80000	0	100	320013	13	43	0	320051	1	0	0	52	320039	6	0	52	43	13	1	0	0	5109	1	16	1	1	160062	80000	0	0	0	320000	640000	80100	160066	160066	160066	160066	160066
960204	160065	1198	1	0	0	2	0	0	0	0	13	0	0	0	0	3	160034	0	0	17	1	0	25	1040156	80100	640052	320000	80100	640000	320000	479601	1680982	21760156	1	0	160046	0	160049	160049	0	0	3	33	1040100	200	320000	640000	200	400000	1600000	160066	160065	1	1	80201	100	99	100	100	80000	80000	0	100	320014	14	43	8	320052	1	2	2	52	320039	6	1	13	43	13	1	0	0	5109	1	16	1	1	160062	80000	0	9	0	320000	640000	80100	160066	160050	160066	160052	160066
960204	160065	1199	1	0	0	1	0	0	0	0	13	0	0	0	0	3	160050	2	17	0	1	0	25	1040156	80100	640068	320000	80100	640000	320000	479601	1680982	21760156	1	0	160046	0	160065	160049	0	0	3	48	1040100	200	320000	640000	200	400000	1600000	160065	160049	1	1	80201	100	99	100	100	80000	80000	0	100	320014	13	0	0	320052	1	0	1	52	320000	0	1	52	43	13	0	0	0	5109	1	16	1	1	160062	80000	0	9	1	320000	640000	80100	160066	160066	160051	160066	160066
960204	160065	1198	1	1	0	1	0	0	0	0	70	0	0	0	0	3	160050	0	17	17	1	0	25	1040148	80100	640016	320000	80100	640000	320000	479601	1680978	11520024	1	0	160030	0	160065	160065	0	0	3	48	1040100	200	320000	640000	200	400000	1600000	160065	160081	1	1	80201	100	99	100	100	80000	80000	0	100	320013	14	43	0	320052	1	1	2	52	320000	6	1	52	43	13	1	0	0	5109	1	16	1	1	160062	80000	9	9	1	320000	640000	80100	160050	160066	160066	160066	160050
960204	160065	1199	1	1	0	1	0	0	0	0	57	0	0	0	0	3	160034	2	17	17	1	0	25	1040152	80100	640052	320000	80100	640000	320000	479601	1680979	21760152	1	0	160046	0	160065	160065	0	0	3	48	1040100	200	320000	640000	200	400000	1600000	160065	160065	1	1	80201	100	99	100	100	80000	80000	0	100	320013	13	0	8	320013	1	0	1	52	320039	6	1	52	43	13	0	0	0	5109	1	16	1	1	160062	80000	9	0	1	320000	640000	80100	160066	160066	160066	160066	160066
960204	160049	1199	1	0	0	0	0	0	0	0	58	0	0	0	0	2	160050	3	0	17	0	0	25	1040156	80100	640016	320000	80100	640000	320000	479601	1680046	21760152	1	0	160030	0	160065	160049	0	0	3	120	1040100	200	320000	640000	200	400000	1600000	160065	160065	1	1	80201	100	99	100	100	80000	80000	0	100	320014	14	43	0	320052	1	0	1	1906	320039	0	1	51	43	13	1	0	0	5109	1	16	1	1	160062	80000	0	9	0	320000	640000	80100	160066	160050	160050	160066	160066
960204	160065	1198	1	0	0	0	0	0	0	0	13	0	0	0	0	2	160034	0	17	17	0	0	25	1040148	80100	640056	320000	80100	640000	320000	479601	1680979	21760152	1	0	160046	0	160050	160065	0	0	3	32	1040100	200	320000	640000	200	400000	1600000	160065	160065	1	1	80201	100	99	100	100	80000	80000	1	100	320014	14	43	0	320052	1	0	0	52	320000	0	1	13	43	13	1	0	0	5109	1	16	1	1	160062	80000	9	9	0	320000	640000	80100	160066	160066	160066	160066	160050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960025	160069	1199	1	0	2	0	0	0	59	0	1	0	3	160033	2	6	6	0	0	25	1040070	80010	640016	320000	80010	640000	320000	472041	1681191	21760752	1	0	160050	0	160049	160069	0	0	3	32	1040010	20	320000	640000	20	400000	1600000	160069	160069	1	1	80021	10	9	10	10	80000	80000	1	10	320014	14	44	0	320013	1	0	0	53	320039	6	0	13	44	13	0	0	0	5019	15	3	16	0	3	6	160066	80000	13	13	0	320000	640000	80010	160070	160070	160050	160050	160070
960024	160069	1199	1	1	0	1	0	0	59	0	1	0	2	160054	2	6	6	5	0	25	1040078	80010	640068	320000	80010	640000	320000	472041	1681188	21760752	1	0	160052	0	160049	160049	0	0	3	32	1040010	20	320000	640000	20	400000	1600000	160049	160069	1	1	80021	10	9	10	10	80000	80000	0	10	320013	13	44	0	320053	0	0	1	13	320000	6	1	53	44	13	0	0	0	5019	15	3	16	0	6	5	160066	80000	13	13	1	320000	640000	80010	160070	160070	160050	160049	160050
960024	160051	1199	1	1	0	0	0	0	59	0	0	0	1	160054	2	0	6	5	0	25	1040070	80010	640060	320000	80010	640000	320000	472041	1680046	21760752	1	0	160050	0	160069	160069	3	0	3	32	1040010	20	320000	640000	20	400000	1600000	160069	160069	1	1	80021	10	9	10	10	80000	80000	0	10	320014	14	44	0	320053	0	2	1	52	320040	0	1	53	44	13	0	0	0	5019	15	6	16	0	3	3	160046	80000	0	13	2	320000	640000	80010	160070	160070	160070	160181	160070
960024	160069	1199	1	1	0	1	0	0	59	0	0	0	3	160034	2	0	0	5	1	25	1040066	80010	640056	320000	80010	640000	320000	472041	1681217	21760752	1	0	160050	0	160049	160069	3	0	3	53	1040010	20	320000	640000	20	400000	1600000	160069	160069	1	1	80021	10	9	10	10	80000	80000	0	10	320013	13	44	0	320053	1	1	1	53	320000	6	1	53	44	13	1	0	0	5019	15	3	16	0	5	3	160066	80000	13	13	2	320000	640000	80010	160070	160070	160070	160050	160070
960024	160069	1199	1	1	0	1	0	0	13	0	0	0	2	160034	2	6	0	5	1	25	1040066	80010	640016	320000	80010	640000	320000	472041	1680048	21760752	1	0	160050	0	160069	160069	3	0	3	32	1040474	20	320136	640000	20	400000	1600000	160069	160069	1	1	80021	10	9	10	10	80000	80000	0	10	320015	14	0	0	320052	1	0	1	53	320040	6	0	53	44	13	1	0	0	5019	12	6	16	0	6	5	160066	80000	13	0	0	320000	640000	80010	160070	160050	160183	160070	160070
960024	160069	1199	1	0	0	0	0	0	59	0	0	0	3	160034	2	6	0	0	0	25	1040026	80010	640016	320141	80010	640000	320000	472041	1681342	21760752	1	0	160050	0	160049	160069	3	0	3	52	1040010	20	320000	640000	20	400000	1600000	160069	160069	1	1	80021	10	9	10	10	80000	80000	0	10	320014	13	44	0	320013	0	0	0	62	320040	0	1	13	44	13	1	0	0	5027	0	3	16	0	6	5	160066	80000	13	13	0	320000	640000	80010	160150	160071	160070	160070	160070
960024	160069	1199	1	0	0	0	0	0	59	0	1	0	1	160054	2	6	6	5	0	25	1040070	80010	640060	320000	80010	640000	320000	472041	1681191	11520028	1	0	160050	0	160069	160049	3	0	3	52	1040010	20	320000	640000	20	400000	1600000	160069	160069	1	1	80021	10	9	10	10	80000	80000	0	10	320013	15	44	0	320053	0	0	1	53	320039	6	0	32	35	0	0	0	0	5027	0	2	16	0	5	3	160056	80000	10	10	0	320000	640000	80010	160065	160044	160044	160044	160060
960024	160059	1199	0	0	0	0	0	0	0	0	1	0	0	160044	3	12	12	0	0	25	1040066	80010	640000	320000	80010	640000	320000	472041	1680001	18560012	1	0	160045	0	160059	160059	0	0	3	32	1040010	20	320000	640000	20	400000	1600000	160069	160049	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	35	0	320032	0	0	0	3	320000	6	1	0	35	0	0	0	0	5027	0	3	16	0	6	5	160056	80000	10	10	0	320000	640000	80010	160060	160044	160044	160060	160065
960024	160043	1198	0	0	0	0	0	0	38	0	1	0	3	160054	2	6	0	5	0	25	1040066	80010	640056	320000	80010	640000	320000	472041	1680046	21760752	1	0	160050	0	160069	160049	3	0	3	52	1040010	20	320000	640000	20	400000	1600000	160049	160070	1	1	80021	10	9	10	10	80000	80000	0	10	320014	14	44	0	320053	1	0	1	53	320040	6	1	52	44	13	1	0	0	5027	0	5	16	0	3	2	160066	80000	0	13	2	320000	640000	80010	160070	160070	160070	160070	160070
960024	160069	1199	1	1	0	1	0	0	59	0	0	0	1	160034	2	6	0	0	0	25	1040070	80010	640060	320000	80010	640000	320000	472041	1681191	21760752	1	0	160050	0	160069	160069	3	0	3	32	1040010	20	320000	640000	20	400000	1600000	160069	160049	5	1	80021	10	9	10	10	80000	80000	0	10	320014	14	44	0	320013	0	0	1	53	320040	0	0	53	44	13	1	0	0	5027	0	3	16	0	6	3	160066	80000	13	13	2	320000	640000	80010	160052	160070	160070	160050	160070

LD4 (multiple, post-index, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations