Firestorm: LD4 (multiple, post-index, 8H) measurements

Code:

  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 13.014

Integer unit issues: 1.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.014

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0f	18	1e	22	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
72005	29348	220	0	21	0	1	26	0	0	0	8	1	4611	29022	0	0	0	15295	13030	1000	8026	4000	1000	8000	4000	5000	20309	98292	9	0	24780	29185	29236	3	10	13000	4000	8000	5000	20000	29293	29277	1	1	61001	1000	1000	0	4006	6	8	4004	0	0	2	10	4005	6	1	9	8	4	1	12779	9340	6787	2987	9	59	19228	3047	3809	12	47	47	28497	1000	16335	12953	13399	4000	8000	1000	29215	29302	29253	29208	29204
72004	29311	219	1	15	1	0	20	0	0	0	12	0	4477	29073	0	0	0	15265	13008	1000	8008	4000	1000	8000	4000	5000	20355	98154	5	0	24765	29256	29367	3	10	13000	4000	8000	5000	20000	29260	29211	1	1	61001	1000	1000	0	4004	5	8	4010	0	0	2	4	4006	0	1	6	12	4	2	13110	9104	6797	3054	13	47	19223	3104	3810	8	54	45	28498	1000	16293	13066	13201	4000	8000	1000	29171	29329	29262	29320	29276
72004	29309	219	0	22	0	0	21	0	0	0	14	1	4495	29046	0	0	0	15311	13014	1000	8014	4000	1000	8000	4000	5000	20322	98432	7	0	24761	29201	29316	3	10	13000	4000	8000	5000	20000	29201	29267	1	1	61001	1000	1000	0	4000	0	8	4003	0	0	0	6	4005	6	1	5	8	0	0	12853	9208	6845	3091	7	52	19284	3154	3811	8	48	52	28560	1000	16394	12929	13276	4000	8000	1000	29241	29293	29216	29366	29287
72004	29304	220	0	16	0	0	20	0	0	0	0	1	4573	28997	2	0	0	15268	13000	1000	8014	4000	1000	8000	4000	5000	20337	98430	8	0	24815	29111	29232	3	10	13000	4000	8000	5000	20000	29178	29125	1	1	61001	1000	1000	0	4000	0	0	4002	0	1	0	2	4000	6	0	5	8	0	0	12775	9165	6811	3078	8	40	19251	3100	3806	16	47	46	28480	1000	16109	13038	13018	4000	8000	1000	29205	29208	29229	29254	29215
72004	29286	219	0	17	0	0	17	0	0	0	8	1	4545	29078	2	0	0	15185	13000	1000	8014	4000	1000	8000	4000	5000	20335	98250	3	0	24814	29234	29269	3	10	13000	4000	8000	5000	20000	29268	29186	1	1	61001	1000	1000	0	4000	0	8	4003	0	0	0	0	4006	6	1	0	8	0	0	12809	9020	6932	3047	11	49	19166	3140	3817	11	45	46	28505	1000	16218	12932	13136	4000	8000	1000	29288	29305	29299	29211	29246
72004	29215	218	0	20	0	0	21	0	0	0	0	0	4658	29076	0	0	0	15232	13000	1000	8014	4000	1000	8000	4000	5000	20316	98352	15	0	24768	29257	29208	3	10	13013	4000	8000	5000	20000	29113	29144	1	1	61001	1000	1000	0	4000	0	0	4002	0	0	0	2	4002	6	0	5	0	0	0	12888	9122	6826	3076	11	45	19253	3002	3809	17	45	46	28515	1000	16234	12940	13323	4000	8000	1000	29262	29268	29257	29247	29210
72004	29222	219	0	17	0	0	22	0	0	0	8	0	4503	29087	0	0	0	15332	13014	1000	8014	4000	1000	8000	4000	5000	20303	98238	2	0	24736	29235	29268	3	10	13000	4000	8000	5000	20000	29128	29205	1	1	61001	1000	1000	1	4000	0	8	4005	0	0	0	0	4005	6	1	5	0	0	0	12708	9445	6859	3068	14	47	19231	3060	3809	9	48	48	28488	1000	16322	12903	13392	4000	8000	1000	29278	29237	29195	29211	29271
72004	29262	219	0	21	0	0	23	0	0	0	8	0	4615	29041	0	0	0	15271	13022	1000	8030	4000	1000	8000	4000	5000	20332	98139	9	0	24832	29174	29333	3	10	13000	4000	8000	5000	20000	29189	29272	1	1	61001	1000	1000	0	4006	6	8	4010	0	0	2	4	4002	6	0	10	11	4	1	12897	9156	6875	3088	6	51	19257	3008	3816	12	44	43	28593	1000	16387	13010	13344	4000	8000	1000	29296	29205	29235	29292	29207
72004	29304	219	1	15	1	0	15	1	0	0	12	0	4501	29129	0	0	0	15253	13020	1000	8014	4000	1000	8000	4000	5000	20318	98338	5	0	24736	29179	29302	3	10	13000	4000	8000	5000	20000	29220	29195	1	1	61001	1000	1000	0	4000	0	8	4002	0	0	0	0	4000	0	1	5	0	0	0	12885	9103	6835	3062	11	45	19300	3067	3815	11	48	48	28486	1000	16326	13031	13443	4000	8000	1000	29208	29203	29303	29291	29147
72004	29242	219	0	14	0	0	23	0	0	0	9	1	4652	29070	0	0	0	15344	13014	1000	8020	4000	1000	8000	4000	5000	20305	98293	0	0	24857	29133	29284	3	10	13000	4000	8000	5000	20000	29304	29205	1	1	61001	1000	1000	0	4000	0	8	4002	0	0	0	2	4000	6	1	3	0	0	0	12946	9258	6831	3039	8	48	19253	3124	3814	20	43	47	28640	1000	16362	13088	13408	4000	8000	1000	29214	29326	29282	29291	29273

Count: 8

Code:

  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	67	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960205	160056	1199	0	0	0	0	1	1	0	0	30	0	1	0	0	160041	0	12	12	0	25	1040144	80100	640044	320000	80100	640000	320000	479601	1680242	16639980	0	0	160037	0	160043	160056	0	0	3	26	1040100	200	320000	640000	200	400000	1600000	160056	160056	1	1	80201	100	99	100	100	80000	80000	0	100	320000	27	0	320155	0	0	24	320024	6	1	24	27	0	0	0	5109	0	4	16	1	1	160053	80000	6	6	320000	640000	80100	160057	160057	160044	160057	160057
960204	160043	1199	0	0	0	0	1	1	0	0	30	0	1	0	0	160041	3	12	12	0	25	1040144	80100	640044	320000	80128	640000	320000	479601	1680274	8160000	1	0	160037	0	160056	160056	0	0	3	39	1040100	200	320000	640000	200	400000	1600000	160056	160056	1	1	80201	100	99	100	100	80000	80000	1	100	320000	27	0	320024	0	0	24	320024	6	1	24	27	0	0	0	5109	0	1	16	1	1	160053	80000	6	6	320000	640000	80100	160057	160057	160161	160057	160057
960204	160056	1199	0	0	0	0	0	0	0	0	30	0	1	0	0	160041	3	12	12	0	25	1040144	80100	640044	320000	80100	640000	320000	479601	1680242	16639980	1	0	160037	0	160056	160056	0	0	3	39	1040100	200	320000	640000	200	400000	1600000	160056	160056	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	0	320024	0	0	27	320000	6	1	24	0	0	0	0	5121	0	1	16	1	1	160053	80000	6	0	320000	640000	80100	160057	160057	160057	160057	160057
960204	160056	1199	0	0	0	0	1	1	0	0	30	0	1	0	0	160041	3	12	12	0	25	1040144	80100	640044	320000	80100	640000	320000	479601	1680001	16639980	0	0	160037	0	160043	160056	0	0	3	39	1040100	200	320000	640000	200	400000	1600000	160056	160056	1	1	80201	100	99	100	100	80000	80000	0	100	320000	27	0	320024	0	0	24	320024	6	1	24	27	0	0	0	5109	0	1	16	1	1	160053	80000	6	6	320000	640000	80100	160057	160057	160057	160057	160057
960204	160056	1199	0	0	0	0	1	1	0	0	30	0	1	0	0	160041	3	12	12	0	25	1040144	80100	640000	320000	80100	640000	320000	479601	1680242	8160000	0	0	160037	0	160056	160056	0	0	3	26	1040100	200	320000	640000	200	400000	1600000	160056	160056	1	1	80201	100	99	100	100	80000	80000	0	100	320000	27	0	320000	0	0	0	320024	6	1	24	27	0	0	0	5109	0	1	16	1	1	160053	80000	6	6	320000	640000	80100	160057	160057	160057	160057	160057
960204	160056	1203	0	0	1	0	0	1	2	0	30	0	1	0	0	160041	3	12	12	487	269	1042677	80167	640000	320000	80100	640000	320000	479601	1680342	16639980	1	0	160037	0	160044	160056	0	0	3	26	1040100	200	320000	640000	200	400000	1600000	160056	160056	1	1	80201	100	99	100	100	80000	80000	0	100	320000	27	0	320024	1	0	24	320024	6	1	24	27	0	0	0	5109	0	1	16	1	1	160053	80000	0	6	320000	640000	80100	160057	160057	160057	160057	160044
960204	160056	1198	0	0	0	0	0	0	0	0	30	0	1	0	0	160041	3	12	12	0	25	1040144	80100	640288	320000	80100	640000	320000	479601	1680242	16639980	0	0	160024	0	160056	160056	0	0	3	40	1040100	200	320000	640000	200	400000	1600000	160043	160056	1	1	80201	100	99	100	100	80000	80000	0	100	320000	27	0	320024	0	0	24	320024	6	1	24	27	0	0	0	5109	0	1	16	1	1	160053	80000	6	6	320000	640000	80100	160044	160057	160057	160057	160045
960204	160056	1198	0	0	0	0	0	0	0	0	30	0	1	0	0	160041	3	0	12	0	25	1040144	80100	640044	320000	80100	640000	320000	479601	1680298	16639980	0	0	160037	0	160056	160056	0	0	3	43	1040100	200	320000	640000	200	400000	1600000	160056	160056	1	1	80201	100	99	100	100	80000	80000	0	100	320000	27	0	320024	0	0	24	320024	6	1	24	27	0	0	0	5120	0	1	16	1	1	160053	80000	0	6	320000	640000	80100	160044	160057	160057	160057	160044
960204	160056	1199	0	0	0	0	0	0	0	0	30	0	1	0	0	160041	3	12	12	0	25	1040144	80100	640044	320000	80100	640000	320000	479601	1680242	16639980	0	0	160037	0	160043	160056	0	0	3	39	1040100	200	320000	640000	200	400000	1600000	160057	160043	1	1	80202	100	99	100	100	80000	80000	0	100	320000	27	0	320024	0	0	0	320024	6	0	24	27	0	0	0	5109	0	1	16	1	1	160153	80000	6	6	320000	640000	80100	160057	160057	160057	160057	160057
960204	160056	1199	0	0	0	0	0	0	0	0	0	0	0	0	0	160041	3	12	12	0	25	1040100	80100	640044	320000	80100	640000	320000	479601	1680242	16639980	0	0	160037	0	160056	160056	0	0	3	39	1040100	200	320000	640000	200	400000	1600000	160056	160056	1	1	80201	100	99	100	100	80000	80000	0	100	320000	27	0	320000	10	0	26	320024	6	0	24	27	0	0	0	5109	0	1	16	1	1	160053	80000	6	6	320000	640000	80100	160057	160057	160057	160057	160044

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d2	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
960025	160065	1199	1	1	0	0	0	58	0	0	2	160050	2	0	15	1	25	1040066	80010	640056	320000	80010	640000	320000	466408	1681115	11520028	0	160046	160065	160049	0	3	48	1040010	20	320000	640000	20	400000	1600000	160065	160066	1	1	80021	10	9	10	10	80000	80000	10	320014	14	0	0	320052	0	0	0	13	320039	6	0	13	43	13	0	0	5019	0	1	16	0	1	1	160062	80000	0	9	0	320000	640000	80010	160066	160066	160050	160050	160066
960024	160049	1199	1	1	1	0	0	58	1	0	2	160050	2	17	0	1	25	1040062	80010	640052	320000	80010	640000	320000	472041	1680978	11520028	0	160030	160069	160049	0	3	48	1043514	20	320148	640000	20	400000	1600000	160065	160049	1	1	80021	10	9	10	10	80000	80000	10	320013	13	43	0	320052	1	0	0	52	320038	6	1	13	43	13	1	0	5019	0	1	16	0	1	1	160062	80000	0	9	1	320000	640000	80010	160050	160050	160051	160050	160066
960024	160065	1199	1	1	0	0	1	58	0	0	3	160034	0	17	17	1	25	1040026	80010	640056	320000	80010	640000	320000	469392	1681087	21760152	0	160030	160065	160065	0	3	32	1040010	20	320000	640000	20	400000	1600000	160049	160049	1	1	80021	10	9	10	10	80000	80000	10	320013	14	43	0	320013	1	0	0	5610	320039	0	1	53	0	13	1	0	5019	0	1	16	0	1	1	160046	80000	9	9	1	320000	640000	80010	160050	160066	160066	160066	160066
960024	160049	1199	1	1	1	0	0	59	1	0	0	160052	0	17	0	0	25	1040066	80010	640056	320000	80010	640000	320000	464156	1680254	21760152	0	160046	160049	160065	0	3	32	1040010	20	320000	640000	20	400000	1600000	160065	160049	1	1	80021	10	9	10	10	80000	80000	10	320014	13	0	0	320052	0	0	2	52	320000	6	0	13	43	13	1	0	5019	0	1	16	0	1	1	160062	80000	0	0	1	320000	640000	80010	160066	160050	160066	160050	160066
960024	160065	1198	1	1	1	0	1	38	0	0	0	160044	0	12	12	0	25	1040054	80010	640056	320000	80010	640000	320000	472041	1680242	9823384	0	160037	160059	160056	7	3	26	1040010	20	320000	640000	20	400000	1600000	160056	160043	1	1	80021	10	9	10	10	80000	80000	10	320000	0	27	0	320024	0	0	0	0	320024	0	0	24	35	0	0	0	5019	0	1	16	0	1	1	160053	80000	10	0	0	320000	640000	80010	160044	160062	160060	160057	160057
960024	160056	1199	0	0	0	1	1	38	0	0	1	160044	0	0	12	0	25	1040054	80010	640000	320000	80010	640000	320000	472041	1680321	18560012	0	160040	160043	160059	0	3	42	1040010	20	320000	640000	20	400000	1600000	160062	160056	1	1	80021	10	9	10	10	80000	80000	10	320000	0	27	0	320000	0	0	0	0	320024	6	1	24	35	0	0	0	5019	0	1	16	0	1	1	160053	80000	6	0	0	320000	640000	80010	160060	160057	160060	160060	160060
960024	160059	1198	0	0	0	1	1	38	1	0	0	160028	0	0	12	0	25	1040054	80010	640044	320000	80010	640000	320000	469693	1680484	16639980	0	160040	160043	160059	0	3	26	1040010	20	320000	640000	20	400000	1600000	160059	160056	1	1	80021	10	9	10	10	80000	80000	10	320000	0	27	0	320000	0	1	0	24	320032	6	1	32	35	0	0	0	5019	0	1	16	0	1	1	160056	80000	10	0	0	320000	640000	80010	160044	160060	160057	160060	160046
960024	160056	1199	0	0	0	0	0	38	0	0	0	160028	3	12	12	0	25	1040066	80010	640060	320000	80010	640000	320000	465900	1680478	16639980	0	160040	160062	160043	0	3	26	1040010	20	320000	640000	20	400000	1600000	160043	160056	1	1	80021	10	9	10	10	80000	80000	10	320000	0	27	0	320032	1	0	0	35	320024	6	1	24	35	0	0	0	5019	0	1	16	0	1	1	160053	80000	0	0	0	320000	640000	80010	160060	160044	160060	160044	160057
960024	160056	1199	0	0	0	0	0	38	1	0	1	160044	3	0	0	0	25	1040054	80010	640056	320000	80010	640000	320000	472041	1680417	8160000	0	160040	160056	160045	0	3	39	1040010	20	320000	640000	20	400000	1600000	160056	160043	1	1	80021	10	9	10	10	80000	80000	10	320000	0	27	0	320032	0	0	0	24	320024	6	0	24	35	0	0	0	5019	0	1	16	0	1	1	160056	80000	0	0	0	320000	640000	80010	160057	160044	160057	160156	160060
960024	160056	1198	0	0	0	1	1	38	0	0	0	160044	0	12	0	0	25	1040066	80010	640000	320000	80010	640000	320000	472041	1680295	16639980	0	160040	160056	160056	0	3	39	1040010	20	320000	640000	20	400000	1600000	160043	160056	1	1	80021	10	9	10	10	80000	80000	10	320000	0	27	0	320000	0	0	0	24	320032	0	0	24	35	0	0	0	5019	0	1	16	0	1	1	160056	80000	0	6	0	320000	640000	80010	160060	160057	160044	160063	160060

LD4 (multiple, post-index, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations