Firestorm: LD4 (single, B) measurements

Code:

  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.004

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	df	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
65005	28520	212	1	1	0	1	2	0	0	0	0	0	6	0	1	0	4963	28160	0	1	0	16053	5004	4004	1000	4000	1000	5000	47522	0	1	0	22984	28300	28306	3	10	5000	1000	4000	1000	8000	28396	28420	1	1	61001	1000	1000	0	1000	2	1000	1	0	1001	0	1	2	0	13748	9759	7047	3437	0	48	19209	3324	3812	13	41	40	2	27957	14740	12943	13290	1000	4000	28339	28357	28404	28390	28309
65004	28388	212	0	1	0	0	1	0	0	0	0	0	4	0	0	0	5020	28110	0	0	0	16165	5004	4004	1000	4000	1000	5000	47599	5	0	0	22954	28400	28378	3	10	5000	1000	4000	1000	8000	28430	28340	1	1	61001	1000	1000	0	1000	0	1000	0	0	1000	0	0	2	0	13632	9866	7135	3360	0	42	19322	3213	3811	15	42	38	2	27926	14690	12806	13409	1000	4000	28252	28377	28307	28471	28422
65004	28464	213	1	1	0	0	1	0	0	0	0	0	2	0	0	0	5032	28299	0	0	0	16125	5004	4004	1000	4000	1000	5000	47432	0	0	0	22968	28393	28355	3	10	5000	1000	4000	1000	8000	28153	28278	1	1	61001	1000	1000	0	1000	2	1000	0	0	1001	2	0	3	0	13591	9982	7133	3310	1	44	19322	3323	3817	12	42	42	2	27973	14512	12618	13635	1000	4000	28415	28368	28311	28325	28340
65004	28410	212	0	0	0	0	1	0	0	0	0	0	0	0	0	0	5067	28150	0	0	0	16079	5004	4004	1000	4000	1000	5000	47548	0	0	0	22910	28285	28386	3	10	5000	1000	4000	1000	8000	28421	28261	1	1	61001	1000	1000	0	1000	2	1000	0	0	1001	2	1	0	0	13657	9894	7165	3296	1	42	19305	3257	3811	14	45	45	2	28006	14799	12758	13525	1000	4000	28440	28434	28352	28389	28473
65004	28456	213	0	1	0	0	1	0	1	0	0	0	4	0	0	0	5011	28110	1	0	0	16295	5004	4004	1000	4000	1000	5000	47587	4	0	0	22954	28182	28449	3	10	5000	1000	4000	1000	8000	28275	28335	1	1	61001	1000	1000	1	1000	2	1000	0	1	1001	0	1	0	0	13671	10017	7080	3296	0	46	19299	3207	3820	16	44	44	2	27930	14551	12712	13842	1000	4000	28311	28309	28294	28417	28462
65004	28488	213	0	1	0	0	1	0	0	0	0	0	4	0	0	0	4828	28024	1	0	0	16074	5004	4004	1000	4000	1000	5000	47575	3	0	0	22990	28223	28367	3	10	5000	1000	4000	1000	8000	28359	28371	1	1	61001	1000	1000	0	1000	2	1000	0	0	1000	2	1	3	0	13752	10024	7230	3349	0	44	19165	3239	3814	15	44	35	2	27832	15102	12683	13632	1000	4000	28353	28298	28510	28414	28317
65004	28349	212	0	1	0	0	1	0	0	0	0	0	4	0	0	0	5018	28136	0	0	0	16063	5004	4004	1000	4000	1000	5000	47558	0	0	0	22989	28231	28349	3	10	5000	1000	4000	1000	8000	28274	28425	1	1	61001	1000	1000	0	1000	2	1000	0	0	1000	2	1	3	0	13713	10020	7111	3335	0	47	19246	3260	3818	25	43	37	2	27928	14885	13016	13546	1000	4000	28278	28264	28330	28383	28402
65004	28479	213	0	1	0	0	1	0	0	0	0	0	7	0	1	0	4996	28204	1	0	0	16061	5004	4007	1000	4000	1000	5001	47556	4	0	0	22981	28331	28409	3	10	5000	1000	4000	1000	8000	28271	28325	1	1	61001	1000	1000	0	1000	3	1000	0	0	1001	1	1	3	0	13712	9974	7176	3316	0	39	19247	3227	3817	14	45	45	2	28064	14761	12617	13352	1000	4000	28377	28384	28446	28330	28285
65004	28320	213	0	1	0	0	1	0	0	0	0	0	4	0	0	0	4863	28050	0	0	1	16190	5000	4000	1000	4004	1000	5000	47430	0	0	0	22958	28292	28394	3	10	5000	1000	4000	1000	8000	28511	28294	1	1	61001	1000	1000	0	1000	0	1001	0	0	1000	2	1	0	0	13635	9889	7145	3322	0	42	19327	3314	3815	20	38	42	2	27994	14748	12756	13570	1000	4000	28441	28617	28275	28377	28235
65004	28403	214	2	1	0	0	1	0	0	0	0	0	4	0	0	0	4958	28026	0	0	0	15959	5000	4004	1000	4000	1000	5000	47442	0	0	0	22938	28448	28447	3	10	5000	1000	4000	1000	8000	28551	28368	1	1	61001	1000	1000	0	1000	2	1000	0	0	1000	1	0	2	0	13671	10067	7091	3368	1	46	19214	3260	3818	12	38	42	2	27848	14801	12763	13600	1000	4000	28355	28378	28377	28433	28399

Count: 8

Code:

  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]
  ld4 { v0.b, v1.b, v2.b, v3.b }[1], [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	160061	1199	1	1	1	0	0	0	0	31	0	0	0	1	160031	1	6	6	79961	25	400116	100	320016	80000	100	320000	80000	500	400003	22714068	0	160042	0	160046	160046	79955	3	80043	400100	200	80000	320000	200	80000	640000	160046	160061	1	1	80201	100	99	100	100	80000	80000	1	100	80008	8	23	80028	0	1	308	80000	6	1	26	24	7	2	0	0	5110	1	17	1	1	160043	0	0	9	9	2	80000	320000	100	160062	160062	160047	160062	160062
400204	160046	1198	1	1	0	0	0	0	0	32	0	0	0	1	160031	0	0	6	79946	25	400108	100	320008	80000	100	320000	80000	500	400033	22714068	0	160042	0	160061	160061	79955	3	80028	400100	200	80000	320000	200	80000	640000	160061	160046	1	1	80201	100	99	100	100	80000	80000	0	100	80008	8	24	80007	0	1	26	80018	0	1	25	24	6	1	0	0	5110	1	17	1	1	160043	1	0	0	9	2	80000	320000	100	160062	160062	160062	160062	160062
400204	160061	1199	1	0	1	0	0	0	0	31	0	0	0	0	160046	1	6	0	79961	25	400116	100	320016	80000	100	320000	80000	500	400003	22716884	0	160042	0	160061	160061	79955	3	80028	400100	200	80000	320000	200	80000	640000	160061	160061	1	1	80201	100	99	100	100	80000	80000	0	100	80007	7	24	80027	0	0	26	80041	0	0	26	0	7	0	0	0	5110	1	17	1	1	160058	1	0	9	9	2	80000	320000	100	160062	160062	160062	160062	160062
400204	160046	1199	1	0	0	0	0	0	0	6	0	0	0	0	160031	1	6	6	79946	25	400116	100	320016	80000	100	320000	80000	500	400041	22716884	0	160042	0	160061	160061	79955	3	80043	400100	200	80000	320000	200	80000	640000	160061	160061	1	1	80201	100	99	100	100	80000	80000	0	100	80007	7	24	80027	0	0	26	80020	6	1	7	24	6	0	0	0	5110	1	17	1	1	160058	0	0	9	9	0	80000	320000	100	160047	160062	160047	160062	160062
400204	160061	1199	1	1	0	0	0	0	0	7	0	1	0	0	160046	1	6	6	79961	25	400116	100	320016	80000	100	320000	80000	500	400003	22716884	0	160027	0	160061	160061	79955	3	80043	400100	200	80000	320000	200	80000	640000	160061	160061	1	1	80201	100	99	100	100	80000	80000	0	100	80009	6	24	80027	0	0	26	80020	6	1	7	24	7	2	0	0	5110	1	17	1	1	160058	0	0	9	9	2	80000	320000	100	160062	160047	160062	160062	160062
400204	160061	1199	1	0	1	1	0	0	0	32	0	0	0	1	160046	1	0	6	79961	25	400108	100	320016	80000	100	320000	80000	500	400033	22714068	0	160027	0	160061	160061	79955	3	80043	400100	200	80000	320000	200	80000	640000	160046	160061	1	1	80201	100	99	100	100	80000	80000	1	100	80009	8	0	80026	0	0	25	80018	6	1	25	24	6	0	0	0	5110	1	17	1	1	160043	0	0	9	9	2	80000	320000	100	160062	160062	160062	160047	160062
400204	160061	1199	1	0	0	0	0	0	0	31	0	0	0	0	160046	1	0	6	79946	25	400108	100	320016	80000	100	320000	80000	500	400039	22716884	0	160027	0	160061	160095	79955	3	80043	400100	200	80000	320000	200	80000	640000	160046	160061	1	1	80201	100	99	100	100	80000	80000	0	100	80006	7	24	80026	0	1	26	80000	6	1	26	24	7	0	0	0	5110	1	17	1	1	160058	0	0	9	9	2	80000	320000	100	160062	160062	160111	160062	160047
400204	160061	1199	1	1	0	0	0	0	0	32	0	1	0	0	160031	0	6	6	79946	25	400116	100	320016	80000	100	320000	80000	500	400033	22716884	1	160042	0	160061	160061	79940	3	80028	400100	200	80000	320000	200	80000	640000	160061	160046	1	1	80201	100	99	100	100	80000	80000	1	100	80008	7	24	80026	0	0	6	80000	6	1	26	24	7	0	0	0	5110	1	17	1	1	160058	0	0	0	9	2	80000	320000	100	160062	160047	160062	160062	160062
400204	160061	1199	1	1	0	0	0	0	0	6	0	1	0	1	160046	1	6	0	79961	25	400116	100	320016	80000	100	320000	80000	500	400027	22716884	1	160042	0	160061	160046	79955	3	80028	400100	200	80000	320000	200	80000	640000	160046	160061	1	1	80201	100	99	100	100	80000	80000	1	100	80006	6	24	80006	0	1	7	80000	0	0	7	24	7	0	0	0	5110	1	17	1	1	160058	0	0	9	9	2	80000	320000	100	160062	160047	160047	160062	160062
400204	160061	1199	1	0	1	1	1	0	0	67	0	0	0	1	160046	1	6	6	79961	25	400116	100	320016	80000	100	320000	80000	500	400038	22716884	1	160027	0	160061	160061	79955	3	80023	400100	200	80000	320000	200	80000	640000	160061	160061	1	1	80201	100	99	100	100	80000	80000	0	100	80007	7	24	80025	0	0	26	80018	6	1	26	24	7	0	0	0	5110	1	17	1	1	160058	0	0	9	9	2	80000	320000	100	160062	160047	160062	160062	160062

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	160056	1199	0	0	1	0	0	0	37	1	0	160025	1	6	0	79959	25	400018	10	320008	80000	10	320000	80000	50	400018	22716044	160037	160059	160059	79934	0	3	80041	400010	20	80000	320000	20	80000	640000	160040	160065	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	18	80031	0	0	29	80024	6	1	14	18	0	0	1	5020	4	17	5	5	160037	0	0	0	2	80000	320000	10	160041	160057	160060	160041	160057
400024	160040	1199	0	0	0	0	0	1	35	0	0	160044	1	0	0	79940	25	400018	10	320008	80000	10	320000	80000	50	400000	22716044	160040	160059	160056	79959	0	3	80038	400010	20	80000	320000	20	80000	640000	160059	160056	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80017	0	0	0	80000	0	1	14	0	0	0	0	5020	5	17	5	4	160056	0	0	10	2	80000	320000	10	160057	160057	160060	160060	160060
400024	160056	1199	0	0	0	0	0	0	24	0	0	160044	1	0	0	79959	25	400018	10	320000	80045	10	320000	80000	50	400042	22716044	160040	160059	160059	79934	0	3	80038	400010	20	80000	320000	20	80000	640000	160059	160056	1	1	80021	10	9	10	10	80000	80000	0	10	80007	6	28	80018	0	0	17	80018	0	1	14	22	0	0	0	5020	5	17	5	4	160053	0	10	10	2	80000	320000	10	160057	160041	160060	160041	160060
400024	160059	1199	0	0	0	0	0	0	6	1	0	160044	1	0	0	79959	25	400018	10	320008	80000	10	320000	80000	50	400000	22716044	160040	160040	160040	79953	0	3	80022	400010	20	80000	320000	20	80000	640000	160059	160056	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80030	0	1	34	80023	0	1	18	0	0	0	0	5020	5	17	5	6	160056	0	10	10	2	80000	320000	10	160041	160060	160041	160060	160060
400024	160059	1199	0	0	0	0	0	0	24	1	0	160044	0	0	6	79959	25	400018	10	320008	80000	10	320000	80000	50	400000	22712688	160040	160059	160040	79953	0	3	80038	400010	20	80000	320000	20	80000	640000	160056	160040	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80013	2	0	21	80018	6	1	13	22	0	0	0	5020	5	17	4	5	160037	1	0	13	2	80000	320000	10	160066	160066	160066	160047	160066
400024	160040	1199	0	0	0	0	0	0	0	0	0	160025	1	0	6	79959	25	400010	10	320008	80000	10	320000	80000	50	400009	22712688	160037	160059	160059	79934	0	3	80047	400010	20	80000	320000	20	80000	640000	160059	160056	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80014	0	0	13	80014	0	1	17	22	0	0	0	5020	5	17	5	4	160056	1	13	0	2	80000	320000	10	160066	160066	160066	160066	160047
400024	160046	1199	0	1	1	1	0	0	24	0	0	160025	1	6	0	79940	25	400018	10	320000	80000	10	320000	80000	50	400000	22716560	160040	160040	160059	79953	0	3	80022	400010	20	80000	320000	20	80000	640000	160059	160056	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80000	0	0	0	80000	0	0	0	22	0	0	0	5020	6	17	5	6	160056	1	13	10	0	80000	320000	10	160041	160060	160060	160057	160041
400024	160056	1198	0	0	0	0	0	0	75	1	0	160041	1	6	0	79959	25	400010	10	320008	80000	10	320000	80000	50	400024	22716044	160040	160059	160059	79953	0	3	80022	400010	20	80000	320000	20	80000	640000	160040	160056	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80017	0	0	0	80014	0	1	0	0	0	0	0	5020	5	17	5	5	160053	0	13	10	2	80000	320000	10	160060	160060	160041	160060	160060
400024	160059	1199	0	0	0	0	0	0	0	0	0	160044	1	0	6	79940	44	400010	10	320008	80000	10	320000	80000	50	400057	22717480	160021	160040	160059	79934	0	3	80028	400010	20	80000	320000	20	80000	640360	160059	160111	1	1	80021	10	9	10	10	80000	80000	0	10	80008	7	27	80009	0	1	0	80018	6	0	0	22	0	0	0	5020	5	17	5	5	160056	0	13	10	0	80000	320000	10	160060	160060	160060	160041	160060
400024	160040	1198	0	0	0	0	1	0	23	1	0	160044	1	0	6	79959	25	400010	10	320008	80000	10	320000	80000	50	400018	22716560	160037	160059	160040	79953	0	3	80041	400010	20	80000	320000	20	80000	640000	160059	160056	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80017	0	0	18	80000	6	1	0	22	0	0	0	5040	5	17	5	6	160053	1	13	13	2	80000	320000	10	160057	160060	160057	160041	160060

LD4 (single, B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations