Firestorm: LD4 (single, D) measurements

Code:

  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.010

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.010

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
66005	29317	219	0	1	1	1	2	1	0	0	0	5	1	0	0	4668	28836	0	0	0	16901	6010	4010	2000	4000	2000	10000	47672	5	22986	29152	29275	3	10	6000	2000	4000	2000	12000	29190	29066	1	1	61001	1000	1000	0	2003	3	4	2006	0	1	2	2000	4	0	2	0	2	0	13107	9292	6835	3042	1	51	20054	3110	3825	14	39	41	28549	16365	13438	14797	2000	4000	29289	29285	29242	29266	29313
66004	29242	220	0	1	0	1	1	1	1	0	0	8	0	0	0	4613	28891	2	0	0	16922	6012	4010	2000	4000	2000	10000	47680	0	22998	29073	29226	3	10	6000	2000	4000	2000	12000	29084	29196	1	1	61001	1000	1000	0	2002	3	4	2004	0	1	2	2000	0	0	2	4	2	0	12906	9174	6878	3128	0	39	20097	3135	3825	17	32	38	28424	16444	13244	14754	2000	4000	29253	29342	29331	29353	29353
66004	29220	219	0	1	0	0	1	1	0	1	0	8	1	0	0	4605	28865	2	0	0	16931	6010	4004	2000	4000	2000	10000	47620	0	23054	29094	29288	3	10	6000	2000	4000	2000	12000	29220	29155	1	1	61001	1000	1000	0	2002	3	0	2003	0	0	2	2002	4	0	2	6	2	0	12967	9087	6926	3032	0	41	20092	3067	3828	12	42	47	28412	16276	13351	14910	2000	4000	29272	29280	29239	29324	29224
66004	29249	219	0	0	0	0	0	1	0	0	0	4	0	0	0	4618	28817	0	0	0	16995	6000	4004	2000	4000	2000	10000	47538	0	22998	29225	29297	3	10	6000	2000	4000	2000	12000	29196	29201	1	1	61001	1000	1000	0	2000	0	6	2000	1	0	3	2000	4	0	0	4	0	0	12993	9134	6873	3044	0	39	20108	3073	3826	17	37	34	28429	16465	13185	14915	2000	4000	29289	29271	29313	29319	29333
66004	29291	220	0	1	0	0	1	0	0	1	0	14	0	0	0	4540	28867	0	0	0	16917	6010	4010	2000	4000	2000	10000	47606	0	23068	29189	29320	3	10	6000	2000	4000	2000	12000	29167	29200	1	1	61001	1000	1000	0	2003	4	6	2003	0	2	4	2000	6	0	2	0	2	1	13065	9136	6864	3143	0	40	20088	3100	3826	18	41	41	28537	16365	13407	15173	2000	4000	29382	29278	29275	29306	29251
66004	29293	219	0	1	1	0	1	1	0	0	0	4	1	0	0	4634	28855	0	0	2	16853	6010	4010	2000	4000	2000	10000	47618	1	22978	29141	29329	3	10	6000	2000	4000	2000	12000	29187	29199	1	1	61001	1000	1000	0	2004	4	4	2004	1	0	4	2002	4	0	2	6	2	1	12935	9327	6898	3018	0	40	20035	3039	3829	11	45	42	28465	16426	13312	14789	2000	4000	29357	29339	29300	29309	29378
66004	29329	219	0	1	0	0	0	1	1	0	0	6	0	0	0	4564	28865	0	0	0	16931	6004	4010	2000	4000	2000	10000	47582	5	23032	29187	29253	3	10	6000	2000	4000	2000	12000	29150	29155	1	1	61001	1000	1000	1	2003	3	6	2006	1	2	2	2000	4	0	2	4	2	0	12949	9374	6990	3048	0	42	20153	3114	3829	15	40	39	28520	16287	13347	14943	2000	4000	29301	29276	29300	29263	29315
66004	29257	219	0	1	0	0	0	1	1	0	0	5	1	0	0	4561	28825	0	0	0	16908	6010	4010	2000	4000	2000	10000	47654	0	22995	29071	29265	3	10	6000	2000	4000	2000	12000	29112	29210	1	1	61001	1000	1000	1	2004	3	0	2004	0	0	2	2000	0	0	2	4	2	1	12872	9085	6883	3067	0	42	20161	3055	3825	15	42	42	28372	16406	13321	15009	2000	4000	29360	29185	29336	29286	29284
66004	29274	219	2	1	0	1	1	1	1	1	0	8	0	0	0	4593	28794	0	0	0	16989	6010	4010	2000	4000	2000	10000	47612	5	23020	29140	29331	3	10	6000	2000	4000	2000	12000	29167	29195	1	1	61001	1000	1000	0	2004	2	4	2002	0	2	2	2000	4	0	2	6	2	2	12815	9107	6892	3136	0	49	20029	3125	3827	16	40	40	28520	16329	13319	14957	2000	4000	29326	29323	29193	29306	29276
66004	29239	219	0	1	1	1	1	0	1	1	1	5	0	0	0	4572	28856	0	0	0	16920	6004	4010	2000	4000	2000	10000	47596	0	23037	29117	29312	3	10	6000	2000	4000	2000	12000	29134	29159	1	1	61001	1000	1000	0	2003	3	6	2003	0	2	2	2004	4	0	2	6	2	1	13000	9326	6936	3088	0	40	20146	3100	3828	14	42	47	28541	16311	13307	14719	2000	4000	29227	29290	29277	29274	29343

Count: 8

Code:

  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]
  ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480205	160061	1199	1	1	1	1	1	0	0	13	1	0	0	160025	2	12	12	79956	25	480108	100	320008	160000	100	320000	160000	500	800222	22715484	1	160034	0	160040	160053	79947	0	3	80022	480100	200	160000	320000	200	160000	960000	160046	160061	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	0	160024	0	0	0	0	160024	6	1	0	27	0	0	0	0	0	5110	2	17	2	2	160050	1	6	6	2	160000	320000	100	160054	160041	160054	160054	160057
480204	160040	1198	0	0	0	0	1	1	0	30	1	0	0	160038	0	0	12	79953	25	480108	100	320008	160000	100	320000	160000	500	800000	22715484	1	160021	0	160040	160053	79950	0	3	80035	480100	200	160000	320000	200	160000	960000	160061	160046	1	1	80201	100	99	100	100	80000	80000	0	100	160012	12	42	0	160051	0	0	1	50	160038	6	0	13	42	13	1	0	0	0	5110	2	17	2	2	160059	0	9	9	2	160000	320000	100	160062	160113	160047	160062	160047
480204	160046	1199	1	0	1	0	0	0	0	57	1	0	0	160031	2	16	0	79961	25	480108	100	320016	160000	100	320000	160000	500	801217	22716936	0	160042	0	160061	160061	79955	0	3	80043	480372	200	160000	320000	200	160000	960000	160046	160061	1	1	80201	100	99	100	100	80000	80000	1	100	160014	14	42	0	160013	0	4	1	51	160038	6	1	50	42	13	0	0	0	0	5110	2	17	2	2	160060	0	9	0	2	160000	320000	100	160062	160062	160047	160062	160062
480204	160046	1198	1	1	1	1	0	0	0	57	0	0	2	160046	2	16	0	79961	25	480116	100	320016	160090	100	320000	160000	500	800753	22716888	1	160042	0	160061	160061	79955	0	3	80023	480100	200	160000	320000	200	160000	960000	160046	160061	1	1	80201	100	99	100	100	80000	80000	0	100	160014	14	42	0	160013	0	0	1	12	160000	6	1	51	42	13	1	0	0	0	5110	2	17	2	2	160058	0	9	9	2	160000	320000	100	160062	160047	160099	160062	160062
480204	160061	1199	1	0	1	0	0	0	0	0	0	0	1	160038	0	0	0	79953	25	480100	100	320000	160000	100	320000	160000	500	800979	22712688	0	160037	0	160056	160056	79934	0	3	80040	480100	200	160000	320000	200	160000	960000	160056	160040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	27	0	160210	0	1	0	35	160032	0	1	32	35	0	0	0	0	0	5110	2	17	2	2	160050	0	10	0	2	160000	320000	100	160078	160057	160057	160055	160057
480204	160056	1199	0	0	0	0	0	0	0	0	1	0	0	160038	2	0	12	79940	25	480108	100	320008	160000	100	320000	160000	500	800371	22715484	0	160021	0	160056	160040	79950	0	3	80038	480100	200	160000	320000	200	160000	960600	160053	160053	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	27	0	160024	0	0	0	24	160024	6	1	32	0	0	0	0	0	0	5110	2	17	2	2	160058	0	0	0	2	160000	320000	100	160062	160047	160062	160062	160062
480204	160046	1199	1	1	1	0	0	0	0	13	0	0	2	160046	2	0	16	79961	25	480116	100	320016	160000	100	320000	160000	500	800753	22716888	0	160042	0	160061	160061	79955	0	3	80028	480100	200	160000	320000	200	160000	960000	160061	160061	1	1	80201	100	99	100	100	80000	80000	0	100	160012	15	0	0	160052	0	0	0	50	160000	6	1	50	42	13	0	0	0	0	5110	2	17	2	2	160058	0	9	0	0	160000	320000	100	160062	160047	160062	160047	160062
480204	160061	1199	1	1	1	1	0	0	0	57	0	1	2	160046	0	16	16	79961	25	480116	100	320016	160000	100	320000	160000	500	800753	22716888	0	160027	0	160061	160061	79940	0	3	80043	480100	200	160000	320000	200	160000	960000	160061	160061	1	1	80201	100	99	100	100	80000	80000	0	100	160014	13	42	0	160052	0	0	0	57	160038	6	1	50	0	12	2	0	0	0	5110	2	17	2	2	160058	0	9	0	2	160000	320000	100	160062	160062	160062	160062	160062
480204	160061	1199	1	0	0	0	0	0	0	57	0	1	2	160068	2	16	16	79961	25	480116	100	320016	160000	100	320000	160000	500	800042	22716888	1	160042	0	160046	160061	79955	0	3	80043	480100	200	160000	320000	200	160000	960000	160061	160061	1	1	80201	100	99	100	100	80000	80000	1	100	160013	13	0	0	160013	0	0	0	51	160038	6	1	50	42	12	1	0	0	0	5110	2	17	2	2	160043	0	0	9	2	160000	320000	100	160047	160047	160047	160062	160062
480204	160061	1198	1	0	0	0	0	0	0	12	0	1	0	160025	2	0	0	79958	25	480222	100	320008	160000	100	320000	160000	500	800371	22715484	1	160021	0	160053	160056	79934	0	3	80038	480100	200	160000	320000	200	160000	960000	160056	160053	1	1	80201	100	99	100	100	80000	80000	1	100	160000	0	27	0	160031	0	0	0	32	160032	6	0	24	0	0	0	0	0	0	5110	2	17	2	1	160058	0	9	0	2	160000	320000	100	160062	160062	160064	160062	160062

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
480025	160061	1199	1	1	0	0	1	0	0	57	0	1	0	2	160046	2	16	0	79963	0	25	480026	10	320016	160000	10	320000	160000	50	800747	22716888	0	160042	160061	160061	79955	3	80043	480010	20	160000	320000	20	160000	960000	160046	160061	1	1	80021	10	9	10	10	80000	80000	0	10	160013	12	42	8	160013	0	0	0	51	160000	6	1	51	42	13	0	0	0	5020	0	0	2	17	0	1	1	160058	9	9	2	160000	320000	10	160062	160047	160062	160062	160062
480024	160061	1199	1	1	1	0	0	0	0	56	0	1	0	2	160046	0	16	16	79961	0	25	480026	10	320008	160000	10	320000	160000	50	800747	22716888	0	160042	160061	160061	79955	3	80028	480010	20	160000	320000	20	160000	960000	160063	160046	1	1	80021	10	9	10	10	80000	80000	0	10	160012	14	0	0	160050	0	0	1	53	160000	0	0	13	42	12	1	0	1	5020	0	0	1	17	0	1	1	160058	9	0	2	160000	320000	10	160047	160062	160062	160063	160062
480024	160061	1199	1	0	1	0	0	0	0	57	0	1	0	0	160046	2	16	0	79961	0	25	480026	10	320016	160000	10	320000	160000	50	800753	22716888	0	160027	160061	160061	79940	3	80043	480010	20	160000	320000	20	160000	960000	160061	160061	1	1	80021	10	9	10	10	80000	80000	0	10	160013	14	0	0	160052	0	1	1	50	160038	6	1	50	42	12	2	0	0	5020	0	0	1	17	0	1	1	160058	9	9	2	160000	320000	10	160047	160062	160062	160062	160062
480024	160061	1199	1	1	1	0	0	0	0	13	0	0	0	2	160031	2	16	16	79961	0	25	480018	10	320016	160000	10	320000	160000	50	800717	22716888	0	160027	160046	160063	79955	3	80043	480010	20	160000	320000	20	160000	960000	160061	160061	1	1	80021	10	9	10	10	80000	80000	0	10	160013	13	42	0	160052	0	0	1	51	160037	6	1	51	42	12	1	0	0	5020	0	0	1	17	0	1	1	160058	9	9	2	160000	320000	10	160062	160047	160062	160062	160047
480024	160061	1198	1	1	1	0	0	0	0	57	0	0	0	2	160046	2	16	16	79946	0	25	480026	10	320016	160000	10	320000	160000	50	800042	22716888	1	160042	160046	160061	79955	3	80045	480010	20	160000	320000	20	160000	960000	160061	160061	1	1	80021	10	9	10	10	80000	80000	1	10	160012	13	42	0	160052	0	0	0	50	160038	6	1	50	42	13	1	0	0	5020	0	0	1	17	0	1	1	160058	9	9	0	160000	320000	10	160047	160063	160062	160047	160047
480024	160061	1199	1	1	1	0	0	0	0	57	0	1	0	2	160046	2	16	16	79961	9	25	480018	10	320016	160000	10	320000	160000	50	800053	22716888	0	160027	160284	160046	79955	10	80043	480010	20	160000	320000	20	160000	960000	160061	160046	1	1	80021	10	9	10	10	80000	80000	1	10	160373	13	42	0	160142	0	3	0	63	160038	6	1	51	42	13	2	0	0	5020	0	0	1	17	0	1	5	160058	9	9	2	160000	320000	10	160047	160062	160047	160062	160062
480024	160061	1199	1	0	0	0	0	0	0	639	0	1	0	0	160046	2	16	16	79961	0	25	480026	10	320016	160000	10	320000	160000	50	800766	22716888	0	160042	160061	160063	79955	3	80043	480010	20	160000	320000	20	160000	960000	160061	160046	1	1	80021	10	9	10	10	80000	80000	0	10	160013	14	0	0	160014	0	0	2	54	160038	6	0	50	42	13	3	0	0	5020	0	0	3	17	0	1	1	160043	9	9	0	160000	320000	10	160062	160099	160062	160062	160062
480024	160063	1198	1	0	0	0	0	0	0	56	0	1	0	2	160031	2	16	16	79961	0	124	480018	10	320016	160000	10	320000	160000	50	800737	22716888	1	160042	160285	160061	79940	3	80043	480010	20	160000	320000	20	160000	960000	160061	160061	1	1	80021	10	9	10	10	80000	80000	0	10	160014	13	42	0	160014	0	1	1	54	160038	6	1	12	42	12	0	0	0	5020	0	0	1	17	0	1	1	160058	9	0	2	160000	320000	10	160047	160047	160062	160062	160062
480024	160046	1199	1	1	0	0	0	0	4	13	264	0	0	0	160046	2	16	16	79963	0	25	480156	10	320064	160540	10	320000	160270	50	815941	22724588	0	160354	160228	160061	79955	3	80028	480010	20	160000	320000	20	160000	960000	160061	160061	1	1	80021	10	9	10	10	80000	80000	0	10	160014	14	42	0	160051	0	0	0	13	160038	6	0	50	42	12	0	0	0	5020	0	0	1	17	0	3	1	160043	9	9	0	160000	320000	10	160062	160047	160062	160062	160062
480024	160061	1199	1	0	1	0	0	3	0	57	0	0	0	2	160046	0	0	16	79961	0	25	480026	10	320016	160000	10	320000	160000	50	800046	22716888	0	160027	160061	160061	79955	3	80028	480010	20	160000	320000	20	160000	962160	160061	160061	1	1	80021	10	9	10	10	80000	80000	0	10	160014	15	42	0	160052	0	4	3	54	160000	6	1	51	42	13	1	0	0	5020	0	0	1	17	0	1	1	160043	9	9	2	160000	320000	10	160047	160062	160290	160062	160047

LD4 (single, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations