Firestorm: LD4 (single, H) measurements

Code:

  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.004

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
65005	29423	220	3	4	1	3	0	0	0	126	0	1	0	4661	28852	0	0	0	17048	5004	4004	1000	4000	1000	5000	47529	0	1	0	22948	29075	29226	3	10	5000	1000	4000	1000	8000	29138	29150	1	1	61001	1000	1000	0	1000	2	1000	2	0	1000	2	0	2	0	13053	9219	6858	3123	5	71	20192	3063	3813	11	62	53	28351	15885	14076	15012	1000	4000	29346	29345	29325	29284	29312
65004	29238	219	4	3	0	2	0	0	0	15	0	0	0	4545	28812	0	0	0	17028	5005	4004	1000	4000	1000	5000	47515	0	1	5	22900	29123	29387	3	10	5000	1000	4000	1000	8000	29194	29202	1	1	61001	1000	1000	0	1000	2	1001	1	6	1000	2	0	2	0	12835	9156	6952	3112	4	53	20119	3125	3816	11	50	64	28335	16512	13841	15056	1000	4000	29377	29289	29319	29266	29348
65004	29326	219	4	2	0	6	0	0	0	42	0	1	0	4692	28844	0	0	0	16967	5004	4004	1000	4000	1000	5000	47560	0	1	5	22940	29204	29301	3	10	5000	1000	4000	1000	8000	29304	29165	1	1	61001	1000	1000	0	1000	2	1000	0	0	1000	2	0	2	0	12817	9072	6853	3030	5	52	20206	3091	3814	8	48	44	28374	16254	14086	15062	1000	4000	29384	29352	29324	29243	29371
65004	29241	219	3	3	0	5	0	0	0	31	0	1	0	4678	28830	0	0	0	16980	5004	4006	1000	4000	1000	5000	47573	3	0	5	22894	29065	29248	3	10	5000	1000	4000	1000	8000	29140	29238	1	1	61001	1000	1000	0	1000	2	1001	0	2	1002	2	0	2	0	12914	9176	6932	3147	2	49	20144	3261	3817	12	51	44	28505	16448	13922	14942	1000	4000	29217	29281	29274	29315	29230
65004	29278	219	3	6	0	5	0	0	0	350	0	1	0	4622	28836	0	0	0	17022	5004	4008	1000	4000	1000	5000	47610	3	1	5	22914	29210	29309	3	10	5000	1000	4004	1000	8000	29291	29265	1	1	61001	1000	1000	0	1000	3	1000	0	6	1000	2	0	3	0	13005	9115	6913	3133	3	56	20193	3037	3810	13	52	47	28351	16337	13879	14811	1000	4000	29334	29359	29218	29287	29245
65004	29275	220	2	6	0	5	0	0	0	336	0	1	0	4558	28901	0	0	0	16945	5004	4004	1000	4000	1000	5000	47515	2	1	5	22905	29121	29274	3	10	5000	1000	4000	1000	8000	29174	29074	1	1	61001	1000	1000	0	1000	2	1001	0	0	1001	2	0	2	0	12863	9202	6908	3192	5	53	20206	3076	3813	11	46	54	28356	16318	13995	14795	1000	4000	29272	29362	29242	29256	29361
65004	29287	219	2	4	0	2	0	0	0	27	0	1	0	4515	28731	0	0	1	17064	5004	4004	1000	4000	1000	5000	47546	3	0	5	22948	29117	29298	3	10	5000	1000	4000	1000	8000	29239	29181	1	1	61001	1000	1000	0	1000	2	1001	0	1	1000	2	0	3	0	12729	9151	6837	3053	2	52	20181	3101	3816	4	52	58	28500	16371	13892	15044	1000	4000	29303	29287	29283	29251	29199
65004	29413	219	3	3	0	4	0	0	0	379	0	1	0	4678	28798	0	0	1	17068	5004	4004	1000	4000	1000	5000	47656	2	1	0	22926	29067	29216	3	10	5000	1000	4000	1000	8000	29156	29140	1	1	61001	1000	1000	1	1000	2	1000	0	0	1000	2	0	2	0	12949	9022	6867	3087	5	52	20166	3120	3812	9	56	53	28476	16262	13465	14914	1000	4000	29250	29188	29304	29348	29289
65004	29308	220	0	5	0	6	0	0	0	27	0	1	0	4624	28972	0	1	0	16966	5004	4004	1000	4000	1000	5000	47533	7	1	0	22948	29118	29234	3	10	5000	1000	4000	1000	8000	29108	29097	1	1	61001	1000	1000	0	1000	2	1000	0	1	1000	2	0	3	0	12837	9181	6876	3109	3	52	20119	3059	3814	11	62	53	28468	16378	13820	14885	1000	4000	29219	29274	29318	29317	29398
65004	29258	220	4	3	0	6	0	0	0	312	0	1	0	4569	28786	0	1	0	16967	5004	4004	1000	4000	1000	5000	47560	3	1	5	22899	29171	29259	3	10	5000	1000	4000	1000	8000	29077	29310	1	1	61001	1000	1000	0	1000	2	1000	0	2	1000	2	1	3	0	12797	9247	6912	3079	4	54	20165	3128	3809	14	63	51	28379	16252	13962	14920	1000	4000	29270	29259	29227	29314	29378

Count: 8

Code:

  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4e	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	160053	1199	2	0	0	0	0	0	200	0	0	0	0	0	160025	1	6	0	79955	0	25	400108	100	320008	80000	100	320000	80000	500	400000	22715864	0	160036	0	160055	160040	79934	3	80037	400100	200	80050	320000	200	80000	640000	160053	160053	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80013	0	0	3	80052	6	0	0	15	0	0	0	0	5110	0	1	17	1	1	160052	0	0	6	6	0	80000	320000	100	160041	160056	160041	160054	160056
400204	160053	1198	0	0	0	0	0	0	98	0	0	0	0	0	160038	1	0	6	79955	0	25	400108	100	320008	80000	100	320000	80000	500	400009	22712688	0	160021	0	160055	160064	79949	3	80022	400100	200	80000	320000	200	80000	640000	160040	160053	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80011	0	0	0	80014	6	0	11	18	0	0	0	0	5110	0	1	17	1	1	160037	1	0	0	6	2	80000	320000	100	160054	160041	160054	160056	160041
400204	160053	1199	0	0	0	0	0	0	22	0	1	0	0	0	160038	0	6	6	79953	0	25	400108	100	320044	80000	100	320000	80000	500	400000	22712688	0	160034	0	160055	160040	79949	3	80037	400100	200	80000	320000	200	80000	640000	160040	160053	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	0	80011	0	0	14	80000	6	1	11	15	0	0	0	0	5110	0	1	17	1	1	160052	0	0	9	9	2	80000	320000	100	160041	160056	160054	160041	160041
400204	160055	1198	0	0	0	0	0	0	406	0	1	0	0	0	160025	0	6	0	79940	0	25	400108	100	320008	80000	100	320000	80000	500	400014	22712688	0	160021	0	160055	160055	79949	3	80037	400100	200	80000	320000	200	80000	640000	160055	160053	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	15	80011	0	0	14	80000	6	1	10	0	0	0	0	0	5110	0	1	17	1	1	160052	1	0	9	9	2	80000	320000	100	160056	160056	160056	160041	160056
400204	160055	1198	0	0	1	0	0	0	69	0	0	0	0	0	160025	1	0	6	79955	0	25	400108	100	320008	80000	100	320176	80000	500	400022	22715472	0	160036	0	160040	160055	79934	3	80022	400100	200	80000	320000	200	80000	640000	160055	160053	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	15	80014	0	0	0	80014	0	1	12	15	0	0	0	0	5110	0	1	17	1	1	160037	0	0	9	9	0	80000	320000	100	160056	160056	160056	160056	160056
400204	160055	1199	0	0	0	0	0	0	86	0	1	0	0	0	160040	1	0	0	79940	0	25	400108	100	320008	80000	100	320000	80000	500	400008	22715864	0	160036	0	160040	160055	79934	3	80022	400100	200	80000	320000	200	80000	640000	160055	160053	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	15	80014	0	0	0	80014	0	0	25	18	0	0	0	0	5110	0	1	17	1	1	160052	1	0	9	0	2	80000	320000	100	160041	160041	160041	160056	160054
400204	160055	1199	0	0	0	0	0	0	95	0	0	0	0	0	160025	1	6	6	79955	0	25	400108	100	320008	80000	100	320000	80000	500	400007	22715472	0	160021	0	160055	160055	79947	3	80035	400100	200	80000	320000	200	80000	640000	160053	160040	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	15	80000	0	0	14	80010	6	1	11	0	0	0	0	0	5110	0	1	17	1	1	160050	1	0	0	9	2	80000	320000	100	160054	160056	160054	160041	160054
400204	160040	1199	0	0	0	0	0	0	20	0	1	0	0	0	160040	0	6	6	79955	0	25	400108	100	320000	80000	100	320000	80000	500	400000	22715472	0	160021	0	160040	160055	79934	3	80037	400100	200	80000	320200	200	80000	640000	160053	160053	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80010	0	0	11	80010	6	0	11	18	0	0	0	0	5110	0	1	17	1	1	160050	1	0	9	0	2	80000	320000	100	160041	160054	160041	160054	160056
400204	160055	1199	0	0	0	0	0	0	86	0	1	0	0	0	160025	0	6	6	79940	0	25	400108	100	320000	80000	100	320000	80000	500	400000	22715472	0	160036	0	160055	160040	79949	3	80035	400100	200	80000	320000	200	80000	640000	160040	160053	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	15	80000	0	0	0	80000	0	0	0	0	0	0	0	0	5110	0	1	17	1	1	160052	0	0	0	6	2	80000	320000	100	160056	160056	160054	160056	160041
400204	160053	1199	0	0	0	0	0	0	113	0	1	0	0	0	160040	1	6	6	79940	0	25	400100	100	320040	80000	100	320000	80000	500	400011	22715472	0	160036	0	160053	160053	79947	3	80037	400100	200	80000	320000	200	80000	640000	160053	160055	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	15	80014	1	0	17	80000	6	0	11	18	0	0	0	0	5110	0	1	17	1	1	160052	1	0	9	6	2	80000	320000	100	160054	160041	160054	160054	160056

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	160053	1199	0	0	1	0	0	0	0	0	0	0	0	0	160038	1	0	6	79940	25	400018	10	320008	80000	10	320000	80000	50	400000	22715472	0	0	160083	160040	160053	79934	0	3	80035	400010	20	80000	320000	20	80000	640000	160053	160053	1	1	80021	10	9	10	10	80000	80000	0	10	80007	7	23	80007	0	0	1	7	80020	6	1	6	23	6	2	0	5020	5	0	1	17	1	1	160058	1	9	9	2	80000	320000	10	160062	160062	160062	160062	160062
400024	160061	1199	1	0	1	1	0	0	0	0	32	0	0	1	160046	1	0	6	79944	25	400026	10	320016	80000	10	320000	80000	50	400003	22716884	1	5	160042	160061	160046	79940	0	3	80028	400010	20	80000	320000	20	80000	640000	160061	160061	1	1	80021	10	9	10	10	80000	80000	0	10	80009	9	23	80027	0	0	0	25	80019	6	1	6	24	6	0	0	5020	0	0	1	17	1	1	160043	0	0	0	0	80000	320000	10	160062	160047	160062	160047	160047
400024	160061	1199	1	0	0	0	0	0	0	0	32	0	0	0	160031	0	6	6	79961	25	400018	10	320016	80000	10	320000	80000	50	400034	22714068	1	0	160027	160061	160046	79955	0	3	80043	400010	20	80000	320000	20	80000	640000	160061	160046	1	1	80021	10	9	10	10	80000	80000	0	10	80007	7	24	80027	0	8	0	30	80020	6	1	25	24	7	2	0	5045	5	0	1	17	1	1	160058	1	9	9	2	80000	320000	10	160047	160062	160062	160062	160047
400024	160046	1199	1	0	1	1	0	0	0	0	32	0	0	0	160031	1	6	0	79961	25	400026	10	320016	80000	10	320000	80000	50	400038	22716888	0	0	160027	160061	160061	79940	0	3	80043	400010	20	80000	320000	20	80000	640000	160046	160061	1	1	80021	10	9	10	10	80000	80000	0	10	80008	7	24	80026	0	0	1	6	80018	6	1	26	23	7	1	0	5020	5	4	1	17	1	1	160058	0	0	9	2	80000	320000	10	160062	160062	160047	160047	160062
400024	160110	1199	1	1	1	0	0	0	0	0	6	1	0	0	160046	0	6	6	79946	25	400026	10	320016	80000	10	320000	80000	50	400000	22716884	0	5	160044	160046	160046	79955	0	3	80043	400010	20	80000	320000	20	80000	640000	160061	160046	1	1	80021	10	9	10	10	80000	80000	0	10	80007	7	0	80006	0	0	1	7	80000	0	1	7	0	7	2	0	5020	0	0	1	17	1	1	160043	1	9	0	2	80000	320000	10	160047	160062	160062	160047	160062
400024	160061	1199	1	0	1	0	0	0	0	0	46	1	0	1	160046	1	0	6	79961	25	400026	10	320016	80000	10	320000	80000	50	400003	22716884	1	5	160042	160046	160061	79955	0	3	80043	400010	20	80000	320000	20	80000	640000	160061	160061	1	1	80021	10	9	10	10	80000	80000	0	10	80007	7	0	80025	0	0	1	26	80020	0	0	26	0	6	0	0	5020	0	4	1	17	1	1	160058	0	0	9	2	80000	320000	10	160047	160062	160047	160062	160062
400024	160046	1198	1	1	1	0	0	0	0	0	32	0	0	1	160046	1	6	6	79961	25	400018	10	320016	80000	10	320000	80000	50	400003	22716884	1	0	160042	160046	160061	79955	0	3	80028	400010	20	80000	320000	20	80050	640000	160061	160061	1	1	80021	10	9	10	10	80000	80000	0	10	80008	8	23	80008	0	0	1	25	80019	6	0	26	24	6	0	0	5020	5	4	1	17	1	1	160058	0	9	9	2	80000	320000	10	160062	160062	160047	160062	160062
400024	160061	1198	1	1	1	1	0	0	0	0	7	1	0	1	160046	1	6	6	79961	25	400018	10	320016	80000	10	320000	80000	50	400044	22714068	1	0	160027	160046	160061	79955	0	3	80043	400010	20	80000	320000	20	80000	640000	160046	160061	1	1	80021	10	9	10	10	80000	80000	0	10	80006	8	0	80007	0	1	0	53	80020	6	0	7	24	6	1	0	5020	5	0	1	17	1	1	160058	1	9	9	2	80000	320000	10	160062	160062	160047	160047	160062
400024	160061	1199	1	0	0	0	0	0	0	0	31	0	0	0	160031	1	6	6	79961	25	400018	10	320008	80000	10	320000	80000	50	400039	22716884	0	5	160042	160061	160061	79940	0	3	80043	400010	20	80000	320000	20	80000	640000	160061	160061	1	1	80021	10	9	10	10	80000	80000	0	10	80007	7	23	80025	0	0	0	26	80018	6	1	7	23	7	0	0	5020	0	4	1	17	1	1	160043	0	9	9	2	80000	320000	10	160047	160047	160047	160062	160062
400024	160061	1199	1	0	1	0	0	0	0	0	32	1	0	0	160046	1	6	0	79946	25	400111	10	320016	80000	10	320000	80000	50	400039	22716884	1	0	160042	160061	160061	79955	0	3	80043	400010	20	80000	320000	20	80000	640000	160046	160061	1	1	80021	10	9	10	10	80000	80000	1	10	80008	8	24	80008	0	1	0	26	80019	0	1	7	23	7	2	0	5020	5	0	1	17	1	1	160058	0	0	9	0	80000	320000	10	160062	160062	160062	160062	160062

LD4 (single, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations