Firestorm: LD4 (single, S) measurements

Code:

  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 5.004

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	0e	0f	19	1e	1f	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
65005	29356	220	21	0	1	21	1	1	0	2	0	0	0	0	4623	28883	0	0	0	17006	5004	4004	1000	4000	1000	5000	47513	0	0	0	23062	29113	29305	3	10	5000	1000	4000	1000	8000	29172	29354	1	1	61001	1000	1000	1000	4	1	1000	2	0	1000	2	0	2	0	12848	9178	6943	3023	6	50	20159	3190	3818	5	38	36	28342	16483	13972	15076	1000	4000	29333	29150	29537	29219	29339
65004	29255	219	11	1	0	10	0	0	0	26	352	0	0	0	4531	28786	0	0	0	17033	5004	4004	1000	4000	1000	5000	47558	3	0	0	22940	29111	29223	3	10	5000	1000	4000	1000	8000	29194	29118	1	1	61001	1000	1000	1000	0	3	1000	0	0	1000	2	0	2	0	13177	9184	6920	3069	7	42	20155	3118	3817	6	37	39	28297	16354	14015	14928	1000	4000	29318	29205	29225	29271	29262
65004	29291	219	19	0	0	18	0	0	0	14	0	1	0	0	4489	28836	0	0	0	16930	5004	4004	1000	4000	1000	5007	47548	1	0	0	22962	29090	29303	3	10	5000	1000	4000	1000	8000	29159	29209	1	1	61001	1000	1000	1000	0	2	1000	0	0	1000	2	1	2	0	12823	9196	6845	3060	4	36	20377	3135	3820	12	39	40	28391	16378	13956	15016	1000	4000	29229	29293	29285	29193	29315
65004	29237	218	14	0	0	21	0	0	0	0	0	0	0	0	4582	28811	0	1	0	16905	5004	4004	1000	4000	1000	5000	47548	0	0	0	22902	29062	29238	3	10	5000	1000	4000	1000	8000	29061	29105	1	1	61001	1000	1000	1000	0	2	1000	0	0	1000	2	0	3	0	12803	9497	6843	3198	4	40	20211	3125	3815	9	37	38	28353	16199	13878	14811	1000	4000	29259	29335	29312	29331	29319
65004	29301	219	13	0	1	15	0	0	0	2	0	0	0	0	4737	28717	0	0	1	16946	5004	4004	1000	4000	1000	5000	47538	1	1	0	22889	29038	29253	3	10	5000	1000	4000	1000	8000	29118	29150	1	1	61001	1000	1000	1000	0	3	1000	0	1	1000	2	0	2	0	13122	9157	6858	3045	9	45	20195	3083	3816	8	36	37	28304	15994	13943	14774	1000	4000	29243	29204	29185	29224	29254
65004	29248	220	22	0	0	10	0	0	0	3	0	0	0	0	4504	28788	0	1	1	16958	5008	4004	1000	4000	1000	5000	47585	2	0	0	22916	29084	29285	3	10	5000	1000	4000	1000	8000	29103	29017	1	1	61001	1000	1000	1000	0	2	1000	0	1	1002	2	0	2	0	12960	9074	6898	3051	8	33	20200	3089	3815	7	38	34	28467	16209	13873	14923	1000	4000	29266	29174	29219	29244	29275
65004	29252	219	11	0	1	18	0	0	0	2	0	0	0	0	4528	28837	0	1	0	17003	5004	4004	1000	4000	1000	5000	47638	0	0	0	22874	29023	29213	3	10	5000	1000	4000	1000	8000	29206	29062	1	1	61001	1000	1000	1000	0	2	1000	0	1	1000	1	0	3	0	12828	9100	6809	3029	10	35	20104	3183	3816	11	38	37	28368	16349	13890	15024	1000	4000	29238	29207	29263	29304	29232
65004	29265	220	17	0	1	10	0	1	0	3	0	0	0	0	4596	28873	0	0	1	16989	5008	4004	1000	4004	1000	5002	47524	1	0	5	22870	29037	29253	3	29	5000	1000	4000	1000	8000	29140	29137	1	1	61001	1000	1000	1000	0	3	1001	0	1	1000	2	2	3	0	12882	9200	6858	3099	6	42	20122	3087	3821	9	38	38	28289	16267	13817	15041	1000	4000	29307	29200	29258	29251	29253
65004	29207	220	17	0	1	16	0	0	2	0	0	0	0	0	4616	28763	0	1	0	16969	5008	4008	1000	4000	1000	5057	47526	1	0	0	22886	29044	29248	3	10	5000	1000	4000	1000	8000	29125	29137	1	1	61001	1000	1000	1000	0	2	1000	0	2	1000	2	0	2	2	13227	9256	6833	3064	6	36	20214	3124	3814	10	34	35	28323	16115	13947	15056	1000	4000	29234	29269	29404	29286	29266
65004	29333	219	13	0	0	13	1	1	0	62	0	1	0	0	4553	28813	0	1	0	16901	5004	4004	1000	4000	1000	5000	47596	0	0	0	22882	29041	29314	3	10	5000	1000	4000	1000	8000	29110	29209	1	1	61001	1000	1000	1000	0	2	1000	0	2	1001	2	0	3	0	12935	9419	6858	3072	7	40	20170	3192	3820	10	39	38	28377	16358	14055	14775	1000	4000	29256	29376	29247	29241	29239

Count: 8

Code:

  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  ld4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	160061	1198	1	1	1	0	0	0	0	0	32	0	0	0	0	1	160031	1	0	6	79961	25	400116	100	320016	80000	100	320000	80000	500	400008	22715472	0	160034	0	160053	160053	79947	0	3	80035	400100	200	80000	320000	200	80000	640000	160053	160040	1	1	80202	100	99	100	100	80000	80000	0	100	80000	0	15	80011	0	0	0	80011	6	1	0	15	0	0	0	0	5110	0	1	17	1	1	160050	0	0	6	6	2	80000	320000	100	160054	160054	160041	160041	160054
400204	160053	1199	0	0	0	0	0	0	0	0	0	0	1	0	0	0	160025	1	0	6	79953	25	400108	100	320008	80000	100	320000	80000	500	400007	22715472	0	160042	0	160061	160061	79955	0	3	80043	400100	200	80000	320000	200	80000	640000	160061	160046	1	1	80201	100	99	100	100	80000	80000	0	100	80009	8	0	80026	1	0	41	80018	6	1	26	24	7	2	0	0	5110	0	1	17	1	1	160043	0	0	0	9	2	80000	320000	100	160062	160062	160062	160062	160062
400204	160061	1199	1	0	1	0	0	0	0	0	90	0	1	0	0	1	160046	1	0	6	79946	25	400116	100	320016	80000	100	320000	80000	500	400039	22716884	0	160027	0	160061	160046	79955	0	3	80043	400100	200	80000	320000	200	80000	640000	160046	160061	1	1	80201	100	99	100	100	80000	80000	0	100	80007	8	24	80008	0	0	26	80020	6	1	26	24	7	0	0	0	5110	0	1	17	1	1	160058	1	0	9	0	2	80000	320000	100	160062	160062	160047	160062	160062
400204	160061	1198	1	0	0	0	0	0	0	0	6	0	0	0	0	1	160046	1	0	0	79946	25	400108	100	320016	80000	100	320000	80000	500	400033	22714068	0	160027	0	160061	160061	79955	0	3	80043	400100	200	80000	320000	200	80000	640000	160061	160061	1	1	80201	100	99	100	100	80000	80000	0	100	80008	8	0	80026	0	0	29	80018	0	1	7	24	6	1	0	0	5110	0	1	17	1	1	160058	0	0	9	9	0	80000	320000	100	160047	160062	160062	160062	160047
400204	160061	1199	1	1	1	1	0	0	0	0	7	0	0	0	0	0	160031	1	6	0	79946	25	400116	100	320016	80000	100	320000	80000	500	400030	22716884	0	160042	0	160115	160061	79955	0	3	80043	400100	200	80000	320000	200	80000	640000	160061	160061	1	1	80201	100	99	100	100	80000	80000	0	100	80007	8	23	80028	0	0	7	80020	0	1	7	0	6	0	0	0	5110	0	1	17	1	1	160058	0	0	9	9	2	80000	320000	100	160062	160062	160062	160062	160047
400204	160046	1199	1	0	1	0	0	0	0	0	32	0	0	0	0	1	160046	1	6	0	79961	25	400116	100	320008	80000	100	320000	80000	500	400000	22716884	0	160042	0	160061	160061	79955	0	3	80043	400100	200	80000	320000	200	80000	640000	160046	160061	1	1	80201	100	99	100	100	80000	80000	0	100	80008	7	0	80025	0	0	25	80019	6	1	6	23	7	1	0	0	5110	0	1	17	1	1	160058	0	0	9	0	2	80000	320000	100	160062	160062	160062	160062	160062
400204	160061	1199	1	0	1	0	0	0	0	0	7	0	1	0	0	1	160046	1	6	6	79961	25	400116	100	320008	80000	100	320000	80000	500	400000	22716884	0	160042	0	160061	160046	79955	0	3	80043	400100	200	80000	320000	200	80000	640000	160061	160046	1	1	80201	100	99	100	100	80000	80000	0	100	80008	7	0	80029	0	0	25	80019	6	1	26	24	7	0	0	0	5110	0	1	17	1	1	160058	0	0	0	9	2	80000	320000	100	160062	160062	160062	160062	160062
400204	160061	1199	1	1	0	1	0	0	0	0	32	0	0	0	0	1	160046	0	6	6	79946	25	400108	100	320016	80000	100	320000	80000	500	400033	22716884	0	160042	0	160061	160061	79940	0	3	80028	400100	200	80000	320000	200	80000	640000	160061	160061	1	1	80201	100	99	100	100	80000	80000	0	100	80007	8	23	80028	0	0	26	80019	6	0	25	23	6	0	0	0	5110	0	1	17	1	1	160058	1	0	9	9	2	80000	320000	100	160062	160062	160062	160047	160062
400204	160061	1199	1	1	1	0	1	0	0	0	32	0	1	0	0	1	160046	1	6	0	79961	25	400116	100	320016	80000	100	320000	80000	500	400039	22714068	0	160042	0	160046	160061	79955	0	3	80043	400100	200	80000	320000	200	80000	640000	160061	160046	1	1	80201	100	99	100	100	80000	80000	0	100	80007	7	24	80026	0	0	26	80018	6	1	7	24	7	1	1	0	5110	0	1	17	1	1	160058	1	0	0	9	0	80000	320000	100	160062	160047	160062	160062	160062
400204	160061	1199	1	1	1	1	1	0	0	0	6	0	1	0	0	0	160046	1	6	6	79961	25	400116	100	320016	80180	100	320000	80000	500	400027	22716884	1	160042	0	160046	160061	79955	0	3	80028	400100	200	80000	320000	200	80000	640000	160061	160046	1	1	80201	100	99	100	100	80000	80000	0	100	80008	7	24	80006	0	0	26	80000	0	1	7	0	6	1	0	0	5110	0	1	17	1	1	160058	0	0	9	9	2	80000	320000	100	160062	160062	160047	160062	160062

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	160056	1199	0	0	20	0	0	0	160044	0	0	6	79959	25	400018	10	320008	80000	10	320000	80000	50	400000	22716044	0	160040	0	160040	160059	79953	0	3	80022	400010	20	80000	320000	20	80000	640000	160040	160056	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80000	1	32	80013	6	1	0	22	0	0	1	0	5020	15	17	0	5	7	160056	1	7	10	2	80000	320000	10	160041	160060	160060	160041	160041
400024	160040	1199	1	1	33	0	0	0	160025	1	6	6	79940	25	400018	10	320008	80045	10	320000	80000	50	400029	22712688	1	160037	0	160059	160059	79953	0	3	80041	400010	20	80000	320000	20	80000	640000	160056	160056	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80014	0	0	80018	6	0	14	0	0	0	0	0	5020	5	17	0	7	5	160037	0	13	0	2	80000	320000	10	160060	160060	160041	160060	160057
400024	160040	1199	0	0	20	0	0	0	160025	1	6	6	79940	25	400010	10	320008	80000	10	320000	80000	50	400022	22716044	1	160040	0	160040	160059	79953	0	3	80041	400010	20	80000	320000	20	80000	640000	160040	160040	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	22	80018	0	17	80000	6	0	0	22	0	0	0	0	5020	5	17	0	5	7	160056	0	10	10	2	80000	320000	10	160057	160041	160060	160060	160060
400024	160040	1198	0	0	24	1	0	0	160044	1	6	6	79959	25	400010	10	320008	80000	10	320000	80000	50	400000	22716044	1	160021	0	160059	160059	79934	0	3	80022	400010	20	80000	320000	20	80000	640000	160059	160056	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80014	0	0	80000	6	1	17	0	0	0	0	0	5020	5	17	0	7	5	160056	0	0	10	2	80000	320000	10	160041	160060	160060	160060	160057
400024	160059	1199	0	0	24	0	0	0	160025	1	6	6	79959	25	400018	10	320008	80000	10	320000	80000	50	400037	22716044	1	160040	0	160040	160059	79953	0	3	80022	400010	20	80000	320000	20	80000	640000	160040	160056	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	18	80013	0	0	80013	0	1	14	22	0	0	0	0	5020	8	17	0	5	7	160056	1	13	13	2	80000	320000	10	160041	160041	160057	160060	160060
400024	160059	1199	0	0	20	0	0	0	160025	0	6	6	79959	25	400018	10	320008	80000	10	320000	80000	50	400029	22712688	1	160040	0	160056	160040	79953	0	3	80041	400010	20	80000	320000	20	80000	640000	160040	160056	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80014	0	17	80000	6	0	14	18	0	0	0	0	5020	7	17	0	6	7	160056	0	13	13	2	80000	320000	10	160060	160041	160041	160060	160041
400024	160059	1199	0	0	23	1	0	0	160025	1	6	0	79940	25	400018	10	320008	80000	10	320000	80000	50	400024	22716044	1	160021	0	160059	160040	79953	0	3	80041	400010	20	80000	320000	20	80000	640000	160056	160056	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80018	0	18	80014	6	1	14	22	0	0	0	0	5020	7	17	0	7	7	160037	0	10	0	2	80000	320000	10	160057	160060	160041	160060	160041
400024	160059	1198	0	0	0	1	0	0	160025	0	6	0	79940	25	400018	10	320008	80000	10	320000	80000	50	400032	22716044	1	160021	0	160059	160040	79934	0	3	80041	400010	20	80000	320000	20	80000	640000	160040	160056	1	1	80021	10	9	10	10	80000	80000	0	10	80048	2	18	80018	0	20	80018	0	1	13	22	0	0	0	0	5020	5	17	0	8	6	160056	0	13	13	0	80000	320000	10	160060	160057	160041	160057	160041
400024	160059	1198	0	0	31	1	0	0	160044	0	6	6	79908	47	400111	10	320104	80090	10	320352	80000	50	400026	22716044	0	160040	0	160059	160059	79953	0	3	80041	400010	20	80000	320000	20	80000	640000	160040	160056	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	80000	2	24	80000	6	1	0	22	0	0	0	0	5041	7	17	0	6	7	160056	1	0	10	2	80000	320000	10	160060	160060	160060	160060	160041
400024	160040	1199	0	0	32	0	0	0	160044	1	0	0	79940	25	400103	10	320008	80000	10	320000	80000	50	400029	22712688	0	160040	0	160040	160040	79953	0	3	80038	400010	20	80000	320000	20	80000	640000	160059	160056	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80018	0	17	80013	6	1	18	18	0	0	0	0	5020	5	17	0	7	5	160056	1	13	10	0	80000	320000	10	160060	160041	160041	160060	160057

LD4 (single, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations