Firestorm: LD4 (single, post-index, H) measurements

Code:

  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 5.000

Issues: 6.011

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 4.011

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
65005	28762	215	3	1	3	0	0	1	1	0	0	3	1	0	0	5103	27926	1	0	16247	6011	1000	4004	1000	1000	4000	1000	5000	5000	47606	6	1	0	22972	28451	28176	3	10	6000	1000	4000	2000	8000	28263	28358	1	1	61001	1000	1000	0	1001	3	3	1004	0	0	1	2	1001	2	2	2	1	0	14025	9543	7187	3486	0	54	19045	3459	3818	12	49	52	27766	1000	15227	12569	12633	1000	4000	1000	28206	28127	28487	28085	28135
65004	27979	211	0	1	1	1	0	1	1	0	0	1	1	0	0	5214	27917	1	1	16227	6011	1000	4011	1000	1000	4000	1000	5000	5000	47592	6	0	0	22943	28116	28080	3	10	6000	1000	4000	2000	8000	28136	28256	1	1	61001	1000	1000	0	1003	1	3	1003	0	0	0	1	1001	0	1	2	1	1	14029	10432	7337	3204	0	43	19185	3398	3812	16	45	46	28118	1000	14198	11776	12446	1000	4000	1000	28197	28526	28068	28062	28284
65004	28032	210	0	1	0	1	0	0	1	0	0	8	1	0	0	5239	27838	1	1	16251	6011	1000	4011	1000	1000	4000	1000	5000	5000	47596	5	1	0	22962	28187	27995	3	10	6000	1000	4000	2000	8000	28138	28313	1	1	61001	1000	1000	0	1003	3	3	1004	0	0	3	2	1001	2	2	3	1	1	13961	10455	7230	3489	0	42	19294	3207	3817	9	47	46	27855	1000	14935	11760	12313	1000	4000	1000	28096	28055	28126	28067	28091
65004	28326	211	0	1	1	1	0	0	1	0	0	4	0	0	0	5104	28276	1	1	15706	6011	1000	4011	1000	1000	4000	1000	5000	5000	47596	7	1	9	22944	28313	28115	3	10	6000	1000	4000	2000	8000	28289	28233	1	1	61001	1000	1000	0	1002	3	0	1003	0	0	1	1	1001	2	2	0	1	1	14245	10110	7324	3349	0	44	19197	3298	3812	15	54	48	27803	1000	14026	11802	12163	1000	4000	1000	28083	28522	28171	28179	28100
65004	28136	210	2	1	1	1	0	0	1	0	1	4	0	0	0	5200	27915	1	1	15894	6004	1000	4011	1000	1000	4000	1000	5000	5000	47600	6	0	0	22952	27991	28154	3	10	6000	1000	4000	2000	8000	28291	28156	1	1	61001	1000	1000	0	1002	2	3	1002	0	0	1	2	1001	2	2	3	1	2	13904	9655	7308	3220	0	44	19190	3241	3812	11	47	49	27730	1000	14030	11668	12643	1000	4000	1000	28084	28102	27994	28106	28112
65004	28026	211	1	1	0	1	0	1	0	0	0	3	1	0	0	5233	27923	1	1	16277	6011	1000	4011	1000	1000	4000	1000	5000	5000	47575	8	0	8	22985	28396	28011	3	10	6000	1000	4000	2000	8000	28427	28183	1	1	61001	1000	1000	0	1002	1	3	1001	0	0	1	1	1000	2	2	2	1	2	13979	10292	6994	3500	0	45	19424	3380	3814	16	45	41	27712	1000	13951	11784	12401	1000	4000	1000	28171	28200	28077	28599	28070
65004	28113	211	0	1	0	1	0	1	1	0	0	4	1	0	0	5047	27947	0	1	15691	6011	1000	4004	1000	1000	4000	1000	5000	5000	47452	7	0	8	23000	28121	28191	3	10	6000	1000	4000	2000	8008	28361	28100	1	1	61001	1000	1000	0	1003	2	3	1003	0	0	0	1	1000	2	2	3	1	1	14010	10301	7274	3475	0	46	19194	3432	3810	9	52	49	28179	1000	14150	11841	13609	1000	4000	1000	28247	28066	28116	28126	28079
65004	28179	213	0	1	0	0	0	0	1	0	0	3	0	0	0	5159	28277	1	0	15800	6011	1000	4011	1000	1000	4000	1000	5000	5000	47464	7	0	0	22972	28058	28079	3	10	6000	1000	4000	2000	8000	28383	28146	1	1	61001	1000	1000	0	1001	2	2	1003	0	0	0	5	1001	2	2	3	1	1	14107	10317	7179	3430	0	39	19333	3210	3813	13	45	37	27771	1000	13826	11861	12420	1000	4000	1000	28179	28782	28132	28135	28101
65004	28081	209	0	1	1	1	0	0	1	0	0	4	1	0	0	5150	28385	1	1	15868	6004	1000	4011	1000	1000	4000	1000	5000	5000	47452	4	1	8	22979	28130	28201	3	10	6000	1000	4000	2000	8000	28316	28407	1	1	61001	1000	1000	0	1002	2	3	1004	0	1	2	1	1001	2	2	0	1	1	13978	10570	7303	3381	0	47	19110	3373	3816	13	38	41	27754	1000	14876	12042	12534	1000	4000	1000	28050	28424	28466	28340	28075
65004	28155	210	2	1	1	1	0	0	1	1	0	4	1	0	0	5191	28294	0	1	15706	6004	1000	4011	1000	1000	4000	1000	5000	5000	47450	4	0	8	22969	28499	28180	3	10	6000	1000	4000	2000	8000	28256	28123	1	1	61001	1000	1000	0	1002	2	0	1002	0	0	1	2	1000	2	2	3	1	1	13416	10521	7317	3533	0	35	19016	3402	3813	12	45	42	27797	1000	14098	11871	12649	1000	4000	1000	28042	28120	28471	28088	28219

Count: 8

Code:

  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8
  ld4 { v0.h, v1.h, v2.h, v3.h }[1], [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400205	160065	1199	1	0	0	0	0	0	0	0	34	0	1	0	0	1	160050	1	6	6	79965	25	480116	80100	320016	80000	80100	320000	80000	480499	400081	22717480	1	160021	0	160056	160040	79950	0	3	80047	480100	200	80000	320000	200	160000	640000	160065	160065	1	1	80201	100	99	100	0	100	80000	80000	0	100	80000	0	18	80013	0	0	0	80000	6	0	29	27	6	0	0	5110	1	17	1	1	160062	1	80000	0	13	80000	320000	80100	160047	160066	160047	160066	160066
400204	160046	1199	1	0	1	1	0	0	0	0	6	0	1	0	0	0	160041	1	6	6	79956	25	480100	80100	320008	80000	80100	320000	80000	480499	400057	22716044	1	160037	0	160056	160056	79950	0	3	80038	480100	200	80000	320000	200	160000	640000	160056	160056	1	1	80201	100	99	100	0	100	80000	80000	0	100	80000	0	18	80014	0	0	14	80055	6	1	14	18	0	0	0	5110	1	17	1	1	160053	0	80000	10	10	80000	320000	80100	160041	160041	160041	160057	160041
400204	160056	1199	0	0	0	0	1	1	0	0	0	0	1	0	0	0	160025	0	6	6	79956	25	480108	80100	320008	80000	80100	320000	80000	480499	400064	22712692	1	160021	0	160040	160056	79934	0	3	80038	480100	200	80000	320000	200	160000	640000	160056	160040	2	1	80201	100	99	100	0	100	80000	80000	0	100	80000	0	18	80000	1	0	183	80057	0	1	0	18	0	0	0	5110	1	35	1	1	160133	1	80000	10	10	80000	320000	80100	160057	160041	160057	160057	160057
400204	160056	1198	0	0	0	0	0	1	0	0	20	0	1	0	0	0	160031	1	0	0	79946	25	480108	80100	320008	80000	80100	320000	80000	480499	400086	22714072	1	160027	0	160101	160065	79950	0	3	80028	480100	200	80000	320000	200	160000	640000	160065	160065	1	1	80201	100	99	100	0	100	80000	80000	0	100	80007	7	0	80028	0	0	6	80023	0	1	6	26	5	1	0	5110	1	17	1	1	160043	1	80000	13	0	80000	320000	80100	160047	160047	160066	160047	160057
400204	160056	1198	0	0	0	0	0	0	0	0	20	0	1	0	0	0	160025	0	0	6	79940	25	480108	80100	320000	80000	80100	320000	80000	480499	400061	22712692	0	160021	0	160056	160040	79934	0	3	80047	480100	200	80000	320000	200	160000	640000	160046	160065	1	1	80201	100	99	100	0	100	80000	80000	0	100	80005	5	26	80006	0	2	6	80023	6	0	6	0	5	1	0	5110	1	17	1	1	160043	1	80000	13	0	80000	320000	80100	160041	160057	160057	160041	160057
400204	160056	1198	0	0	0	0	0	0	0	0	20	0	1	0	0	1	160050	1	6	6	79946	25	480108	80100	320016	80000	80100	320000	80000	480499	400081	22714072	1	160046	0	160119	160056	79950	0	3	80047	480100	200	80000	320000	200	160000	640000	160065	160100	1	1	80201	100	99	100	0	100	80000	80000	0	100	80000	0	18	80014	0	0	14	80013	6	0	14	18	0	0	0	5110	1	17	1	1	160043	1	80000	13	13	80000	320000	80100	160066	160066	160066	160066	160066
400204	160065	1198	1	1	1	0	0	0	0	0	35	0	1	0	0	0	160041	1	6	6	79956	25	480108	80100	320008	80000	80100	320000	80000	480499	400057	22716044	1	160021	3	160040	160056	79934	0	3	80047	480100	200	80000	320000	200	160000	640000	160046	160046	1	1	80201	100	99	100	0	100	80000	80000	0	100	80007	6	0	80029	0	1	29	80000	0	1	14	18	0	0	0	5110	1	17	1	1	160062	0	80000	13	13	80000	320000	80100	160041	160041	160057	160041	160041
400204	160056	1199	0	0	0	0	0	1	0	0	0	0	1	0	0	0	160041	1	6	6	79956	25	480108	80100	320008	80000	80100	320000	80000	480499	400064	22712692	1	160037	0	160056	160056	79950	0	3	80038	480100	200	80000	320000	200	160000	640000	160056	160040	1	1	80201	100	99	100	0	100	80000	80000	0	100	80000	0	0	80000	0	0	14	80000	6	0	0	0	0	0	0	5110	1	17	1	1	160037	0	80000	10	0	80000	320000	80100	160041	160057	160057	160041	160041
400204	160110	1198	0	0	0	0	0	0	0	0	20	0	1	0	0	0	160041	0	6	6	79956	25	480108	80100	320008	80000	80100	320000	80000	480499	400061	22712692	1	160037	0	160056	160040	79934	0	3	80038	480100	200	80000	320000	200	160000	640000	160056	160056	1	1	80201	100	99	100	0	100	80000	80000	0	100	80000	0	18	80000	0	0	13	80014	6	1	0	0	0	0	0	5110	1	17	1	1	160053	0	80000	10	10	80000	320000	80100	160057	160057	160041	160057	160041
400204	160040	1198	0	0	0	0	0	0	0	0	20	0	1	0	0	0	160041	1	0	0	79940	25	480100	80100	320008	80000	80100	320000	80000	480499	400064	22712692	1	160091	0	160040	160040	79950	0	3	80038	480100	200	80000	320000	200	160000	640000	160040	160056	1	1	80201	100	99	100	0	100	80000	80000	1	100	80000	0	0	80013	1	0	13	80014	6	0	14	18	0	0	0	5110	1	26	1	1	160053	0	80000	10	0	80000	320000	80100	160041	160057	160041	160041	160041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
400025	160065	1198	1	0	0	0	1	1	0	0	262	0	0	0	0	0	160158	0	6	6	79956	25	480010	80010	320000	80000	80010	320000	80000	480049	400091	22717480	160046	160065	160065	79959	0	3	80038	480276	20	80045	320000	20	160000	640000	160056	160056	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	80016	2	0	14	80013	6	1	28	0	6	0	0	0	0	5020	0	12	17	0	0	8	10	160037	1	80000	13	10	80000	320000	80010	160060	160060	160060	160060	160060
400024	160171	1200	0	1	0	0	0	1	3	2	19	0	0	0	0	0	160044	1	6	6	79940	25	480010	80010	320008	80000	80058	320000	80000	480318	400072	22716044	160037	160059	160059	79950	0	3	80047	480010	20	80000	320000	20	160000	640000	160065	160065	1	1	80021	10	9	10	10	80000	80000	10	80007	8	27	80006	0	0	32	80022	0	1	29	0	6	1	0	0	0	5020	0	9	17	0	0	9	9	160062	1	80000	13	13	80000	320000	80010	160066	160066	160066	160047	160066
400024	160065	1199	1	0	1	1	0	0	0	0	90	0	1	0	0	0	160031	1	0	6	79965	25	480026	80010	320016	80000	80010	320000	80000	480049	400081	22717480	160046	160065	160065	79959	0	3	80047	480010	20	80000	320000	20	160000	640000	160065	160065	1	1	80021	10	9	10	10	80000	80000	10	80007	7	27	80030	4	1	29	80022	6	0	5	27	6	0	0	0	0	5020	0	7	17	0	0	9	11	160062	1	80000	13	13	80000	320000	80010	160066	160066	160066	160066	160066
400024	160065	1199	1	0	0	0	0	0	0	0	34	0	1	0	0	0	160050	1	6	6	79965	25	480018	80010	320008	80000	80010	320000	80000	480049	400079	22714072	160027	160065	160065	79959	0	3	80047	480010	20	80000	320000	20	160000	640000	160046	160065	1	1	80021	10	9	10	10	80000	80000	10	80006	6	0	80027	0	1	29	80022	6	0	28	27	6	1	0	0	0	5020	0	11	17	0	0	9	6	160062	1	80000	13	0	80000	320000	80010	160066	160047	160066	160066	160066
400024	160065	1198	1	0	1	1	0	0	0	0	34	0	1	0	0	0	160050	0	6	6	79965	25	480018	80010	320016	80000	80058	320000	80000	480049	400087	22717480	160046	160065	160065	79959	0	3	80047	480010	20	80000	320000	20	160000	640000	160065	160065	1	1	80021	10	9	10	10	80000	80000	10	80007	7	27	80007	0	0	28	80023	0	1	6	26	6	0	0	0	0	5020	0	10	17	0	0	7	9	160062	0	80000	13	0	80000	320000	80010	160066	160066	160066	160066	160066
400024	160046	1199	1	0	1	0	0	0	0	2	94	0	0	0	0	0	160050	0	6	0	79965	25	480026	80010	320016	80000	80010	320000	80000	480049	400081	22714072	160046	160065	160065	79959	0	3	80028	480010	20	80045	320000	20	160000	640000	160065	160046	1	1	80021	10	9	10	10	80000	80000	10	80007	6	0	80029	0	1	28	80000	6	0	28	26	5	0	0	0	0	5020	0	12	17	0	0	9	7	160043	1	80000	0	13	80000	320000	80010	160066	160066	160066	160066	160047
400024	160065	1199	1	0	0	1	0	0	0	0	360	0	0	0	0	1	160050	1	6	0	79946	25	480026	80010	320016	80000	80055	320000	80000	480049	400079	22717480	160027	160046	160065	79959	0	3	80047	480010	20	80000	320000	20	160000	640000	160065	160065	1	1	80021	10	9	10	10	80000	80000	10	80007	6	27	80007	0	0	6	80022	6	1	28	27	6	2	0	0	0	5020	0	7	17	0	0	7	12	160062	0	80000	0	0	80000	320000	80010	160066	160047	160066	160066	160066
400024	160065	1199	1	0	1	0	0	0	0	0	106	0	0	0	0	0	160050	1	6	0	79965	25	480026	80010	320016	80000	80058	320000	80000	480049	400058	22717480	160046	160065	160065	79959	0	3	80028	480010	20	80000	320000	20	160000	640000	160065	160065	1	1	80021	10	9	10	10	80000	80000	10	80006	5	26	80028	0	0	6	80023	6	1	29	26	5	2	0	0	0	5020	0	8	17	0	0	9	7	160043	1	80000	13	13	80000	320000	80010	160066	160047	160047	160066	160066
400024	160065	1198	1	0	1	1	0	0	0	0	513	0	1	0	0	0	160031	1	6	6	79965	25	480026	80010	320064	80000	80010	320000	80000	480049	400059	22717480	160046	160065	160065	79938	0	3	80047	480010	20	80000	320000	20	160000	640000	160065	160046	1	1	80021	10	9	10	10	80000	80000	10	80006	6	27	80029	0	0	32	80023	6	0	28	0	6	1	0	0	0	5020	0	10	17	0	0	9	7	160062	1	80000	13	13	80000	320000	80010	160047	160066	160066	160047	160047
400024	160065	1199	1	0	0	0	0	0	0	0	35	0	0	0	0	0	160050	1	6	6	79965	25	480026	80010	320016	80000	80010	320000	80000	480049	400085	22714072	160046	160046	160065	79959	0	3	80028	480010	20	80000	320000	20	160000	640000	160046	160065	1	1	80021	10	9	10	10	80000	80000	10	80005	6	27	80029	0	2	31	80023	0	0	28	27	6	1	0	0	0	5020	0	8	17	0	0	9	10	160062	0	80000	13	13	80000	320000	80010	160047	160066	160066	160047	160066

LD4 (single, post-index, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations