Firestorm: LDNP (D) measurements

Code:

  ldnp d0, d1, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2005	399	3	1	1	1	1	0	0	65	1	0	3	384	2	18	18	15	25	1000	1000	1000	15399	374	399	399	97	3	132	1000	2000	1000	398	398	1	1	1001	1000	1000	0	1020	21	41	1057	0	0	59	1038	6	1	57	42	19	1	73	1	16	1	1	395	1057	9	9	2	1000	1000	400	403	399	399	399
2004	399	3	1	1	1	0	0	1	65	0	0	2	384	2	18	18	16	25	1000	1000	1000	15358	373	398	398	96	3	131	1000	2000	1000	398	399	1	1	1001	1000	1000	0	1019	19	42	1057	2	1	59	1038	6	1	57	42	19	1	73	1	16	1	1	395	1057	9	9	2	1000	1000	399	400	400	400	399
2004	399	3	1	1	1	0	0	0	65	1	0	3	384	2	18	18	16	25	1000	1000	1000	15358	373	398	399	96	3	132	1000	2000	1000	399	398	1	1	1001	1000	1000	0	1020	20	42	1058	0	1	59	1037	6	1	57	42	19	1	73	1	16	1	1	395	1057	9	9	2	1000	1000	399	400	400	400	399
2004	399	3	1	0	1	1	0	0	65	0	0	3	384	2	18	18	15	25	1000	1000	1000	15352	374	398	398	96	3	132	1000	2000	1000	399	400	1	1	1001	1000	1000	0	1019	20	42	1058	1	2	59	1038	6	1	57	42	19	1	73	1	16	1	1	396	1057	9	9	2	1000	1000	400	400	400	400	399
2004	399	3	1	0	1	1	0	0	65	0	0	2	384	2	18	18	15	25	1000	1000	1000	15362	373	398	400	96	3	132	1000	2000	1000	399	398	1	1	1001	1000	1000	0	1019	21	42	1054	1	1	59	1038	6	1	57	42	19	1	73	1	16	1	1	396	1056	9	9	2	1000	1000	403	399	400	400	400
2004	398	3	1	0	1	0	0	0	65	0	0	3	384	2	18	18	15	25	1000	1000	1000	15362	373	398	399	96	3	132	1000	2000	1000	398	398	1	1	1001	1000	1000	0	1019	21	42	1058	1	1	59	1038	6	1	57	42	19	1	73	1	16	1	1	396	1057	9	9	2	1000	1000	400	399	399	399	400
2004	399	2	1	1	0	0	0	0	65	0	0	3	383	2	18	18	16	25	1000	1000	1000	15345	374	399	398	96	3	131	1000	2000	1000	412	399	1	1	1001	1000	1000	0	1019	19	42	1057	0	1	60	1038	6	1	57	42	19	1	73	1	16	1	1	395	1056	9	9	2	1000	1000	399	399	400	400	400
2004	398	3	1	0	1	0	0	0	65	0	0	2	384	2	18	18	16	25	1000	1000	1000	15358	373	398	398	96	3	132	1000	2000	1000	398	399	1	1	1001	1000	1000	0	1020	20	42	1057	1	1	59	1038	6	1	57	42	19	1	73	1	16	1	1	440	1057	9	9	2	1000	1000	400	400	400	399	399
2004	399	2	1	1	0	0	0	0	65	0	0	3	384	2	18	18	16	25	1000	1000	1000	15358	373	398	398	96	3	131	1000	2000	1000	399	398	1	1	1001	1000	1000	0	1020	20	41	1057	1	0	59	1036	6	1	57	42	19	1	73	1	16	1	1	396	1057	9	9	2	1000	1000	399	400	399	399	400
2004	399	3	1	0	1	0	0	0	65	0	0	3	384	3	18	6	16	25	1000	1000	1000	15344	374	399	399	96	3	131	1000	2000	1000	399	398	1	1	1001	1000	1000	0	1020	21	42	1059	1	1	59	1038	6	1	57	41	19	1	73	1	16	1	1	396	1057	9	9	2	1000	1000	399	399	399	400	399

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldnp d0, d1, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120103	931	0	0	0	0	0	0	1	0	0	0	0	120020	119538	109455	25	60100	40102	10001	10000	30100	10000	10000	1079126	5736035	6117882	0	120023	120047	120047	111881	3	112421	50100	30200	20000	10000	60200	10000	10000	120049	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	6	0	12	10000	1	0	1	0	0	0	3210	1	135	1	1	119657	10000	40002	0	6	0	10000	10000	40100	120051	120048	120051	120051	120036
60204	120050	899	0	0	1	0	0	0	6	0	0	0	0	120035	119494	109455	25	60103	40102	10001	10000	30100	10000	10000	1079126	5736035	6117599	0	120026	120035	120050	111881	3	112416	50100	30200	20126	10000	60200	10000	10000	120048	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	0	1	0	0	0	3210	1	100	1	1	119657	10000	40000	9	9	8	10000	10000	40100	120036	120051	120048	120051	120051
60204	120050	899	0	0	0	0	0	0	0	0	0	0	0	120035	119494	109458	25	60103	40102	10001	10000	30100	10000	10000	1079126	5735293	6117882	0	120026	120050	120047	111881	3	112374	50100	30200	20000	10000	60200	10000	10000	120051	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	0	1	0	0	0	3210	1	108	1	1	119655	10000	40002	0	6	8	10000	10000	40100	120051	120051	120036	120048	120036
60204	120050	900	0	0	0	0	0	0	9	0	0	0	0	120035	119538	109443	25	60103	40100	10000	10000	30100	10000	10000	1079539	5735293	6118250	0	120023	120035	120047	111881	3	112374	50100	30200	20000	10000	60200	10000	10000	120057	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	0	1	0	0	0	3210	1	132	1	1	119739	10000	40002	9	6	0	10000	10000	40100	120051	120036	120048	120048	120167
60204	120050	899	0	0	0	0	0	0	1	0	0	0	0	120035	119503	109443	25	60103	40102	10000	10000	30100	10000	10000	1079330	5736035	6118250	0	120026	120050	120053	111903	3	112416	50100	30200	20000	10000	60200	10000	10000	120048	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	0	0	0	0	0	3210	1	100	1	1	119646	10000	40002	9	6	8	10000	10000	40100	120051	120051	120051	120048	120036
60204	120047	899	0	0	0	0	0	0	1	0	1	0	0	120020	119494	109458	25	60100	40100	10001	10000	30100	10000	10000	1079539	5736035	6117599	0	120026	120050	120050	111895	3	112374	50100	30200	20000	10000	60200	10000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	0	1	0	0	0	3210	1	129	1	1	119657	10000	40000	9	9	0	10000	10000	40100	120051	120051	120051	120036	120036
60204	120050	899	0	0	0	0	0	0	1	0	0	0	0	120020	119503	109443	25	60103	40100	10001	10000	30100	10000	10000	1079539	5736035	6117599	0	120026	120050	120050	111895	7	112494	50123	30227	20022	10009	60254	10010	10009	120054	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	0	0	0	10000	0	0	1	0	0	0	3210	1	108	1	1	119656	10000	40000	0	10	0	10000	10000	40100	120052	120052	120052	120036	120055
60204	120054	899	0	0	0	0	0	0	0	0	0	1	0	120039	119509	109461	25	60103	40102	10001	10000	30100	10000	10000	1079126	5736230	6118285	0	120027	120099	120054	111900	3	112407	50100	30200	20000	10000	60200	10000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	0	0	0	10000	0	0	1	0	0	0	3210	1	108	1	1	119646	10000	40002	13	10	12	10000	10000	40100	120055	120055	120055	120055	120052
60204	120055	908	0	0	0	0	0	0	0	0	0	0	0	120039	119509	109461	25	60103	40102	10000	10000	30100	10000	10000	1079396	5736230	6117599	0	120011	120051	120054	111896	3	112407	50100	30200	20000	10000	60200	10000	10000	120035	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	0	0	1	0	0	0	3210	4	121	1	1	119666	10000	40002	13	0	12	10000	10000	40100	120036	120055	120055	120036	120052
60204	120035	899	0	0	0	0	0	0	6	0	0	0	0	120039	119509	109443	25	60100	40102	10001	10000	30100	10000	10000	1079396	5736230	6117599	0	120030	120054	120051	111900	3	112417	50100	30200	20000	10000	60200	10000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	0	0	3	10000	0	1	0	1	1	1	3220	0	16	0	0	119727	10000	40002	9	6	5	10000	10000	40100	120036	120051	120051	120051	120051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0060

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0f	1e	22	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120057	899	0	1	1	0	2	1	0	120045	119493	109467	25	60016	40014	10001	10000	30158	10000	10000	1079858	5736374	6126051	0	120036	120060	120057	111928	3	112481	50010	30020	20000	10000	60020	10000	10000	120041	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10002	0	0	2	1	10000	1	1	0	1	2	0	0	3140	0	12	99	0	8	8	119659	10001	40004	13	10	12	10000	10000	40010	120058	120061	120061	120042	120042
60024	120060	900	1	1	1	0	1	1	1	120230	119493	109467	25	60013	40014	10002	10000	30010	10000	10000	1079870	5736518	6126051	1	120033	120060	120057	111909	3	112486	50010	30020	20000	10000	60020	10000	10000	120060	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	3	1	10002	0	0	3	1	10000	0	1	1	1	1	0	0	3140	0	8	99	0	7	8	119678	10001	40004	13	0	0	10000	10000	40010	120063	120042	120064	120064	120042
60024	120060	899	1	1	1	0	2	1	0	120045	119493	109449	25	60016	40014	10002	10000	30010	10000	10000	1079942	5735593	6126051	1	120189	120060	120141	111928	3	112457	50010	30341	20428	10000	60342	10000	10160	120545	120250	6	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10003	0	1	0	1	10000	1	1	1	1	2	0	0	3140	0	9	99	0	7	7	119677	10001	40004	13	13	12	10000	10000	40010	120061	120042	120061	120042	120042
60024	120060	899	1	1	0	0	1	1	1	120042	119490	109464	25	60016	40014	10002	10000	30010	10000	10000	1079915	5736374	6126051	1	120036	120041	120053	112011	3	112454	50010	30665	20000	10000	60344	10064	10000	120059	120058	1	1	50021	10	9	10	40010	10000	10000	1	10	10002	2	0	10002	0	0	1	1	10000	1	1	1	1	0	0	0	3140	0	8	99	0	9	8	119659	10001	40004	0	10	0	10000	10000	40010	120061	120061	120061	120042	120058
60024	120060	900	1	0	0	0	2	1	0	120045	119493	109467	25	60016	40014	10002	10000	30010	10000	10000	1079942	5736374	6123500	1	120017	120060	120060	111909	3	112461	50010	30020	20000	10000	60020	10000	10000	120057	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10002	0	0	1	1	10000	1	1	1	1	1	0	0	3140	0	7	99	0	8	8	119678	10001	40018	13	10	9	10000	10000	40010	120042	120061	120061	120042	120061
60024	120057	899	1	0	1	0	2	1	0	120026	119484	109464	25	60016	40012	10001	10000	30010	10000	10000	1079942	5736422	6123500	1	120036	120060	120060	111928	3	112487	50010	30020	20000	10000	60020	10000	10000	120060	120060	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10002	0	2	1	16	10000	0	1	1	1	1	0	0	3140	0	8	99	0	8	8	119678	10001	40004	13	13	12	10000	10000	40010	120061	120042	120058	120061	120042
60024	120060	899	1	1	0	0	2	0	0	120026	119484	109449	25	60016	40014	10002	10000	30010	10000	10000	1079870	5736374	6126051	1	120036	120060	120060	111909	3	112474	50010	30020	20000	10000	60020	10000	10000	120060	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	0	10001	0	0	1	1	10000	1	1	1	1	0	0	0	3140	0	8	99	0	8	8	119675	10000	40002	13	0	0	10000	10000	40010	120042	120061	120042	120061	120061
60024	120052	899	1	0	0	0	1	1	0	120045	119493	109464	25	60016	40012	10002	10000	30010	10000	10000	1079942	5736518	6126051	1	120036	120041	120041	111925	3	112455	50010	30020	20000	10000	60020	10000	10000	120060	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10001	0	0	1	1	10000	1	1	1	1	1	0	0	3140	0	7	99	0	8	8	119678	10001	40004	13	10	9	10000	10000	40010	120058	120042	120042	120061	120061
60024	120057	900	1	0	1	0	1	1	0	120045	119493	109467	25	60016	40012	10003	10000	30010	10000	10000	1079870	5736374	6126051	1	120033	120060	120057	111928	3	112457	50010	30020	20000	10000	60020	10000	10000	120060	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	0	10002	0	0	1	1	10000	1	1	1	1	1	0	0	3140	0	7	99	2	8	8	119675	10001	40004	0	10	0	10000	10000	40010	120058	120058	120042	120042	120061
60024	120060	899	1	1	1	1	2	1	0	120045	119484	109467	25	60013	40012	10002	10000	30010	10000	10000	1079942	5736518	6123500	1	120036	120057	120060	111928	3	112472	50010	30020	20000	10000	60020	10000	10000	120060	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	0	10002	0	0	2	1	10000	1	1	1	1	0	0	0	3140	0	8	99	0	7	7	119659	10001	40010	13	13	12	10000	10000	40010	120058	120061	120061	120042	120066

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldnp d0, d1, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120057	899	1	1	1	1	0	1	2	1	0	2	120042	119512	109464	25	60106	40104	10002	10000	30100	10000	10000	1079423	5736374	6119172	1	120033	120057	120057	111903	3	112410	50100	30200	20000	10000	60200	10000	10000	120057	120057	1	1	50201	100	99	100	40100	10000	10000	1	100	10003	2	1	10002	1	1	1	10000	1	1	1	1	0	0	3212	7	121	8	7	119669	10001	40002	10	10	9	10000	10000	40100	120058	120058	120058	120058	120058
60204	120041	900	1	1	1	1	1	0	2	0	0	2	120042	119512	109449	25	60106	40104	10002	10000	30100	10000	10000	1079423	5735593	6119172	1	120033	120057	120105	111903	3	112410	50100	30200	20000	10000	60200	10000	10000	120057	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10002	0	2	1	10000	1	1	1	1	1	0	3212	7	100	7	5	119669	10001	40002	10	0	9	10000	10000	40100	120058	120058	120058	120042	120042
60204	120057	900	1	1	1	1	1	0	2	0	0	2	120042	119512	109464	25	60106	40102	10002	10000	30100	10000	10000	1079423	5736374	6119172	1	120033	120057	120059	111897	3	112415	50100	30200	20000	10000	60200	10000	10000	120057	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	0	10002	0	1	1	10000	1	1	1	1	0	0	3212	5	121	7	5	119669	10001	40004	10	0	9	10000	10000	40100	120042	120058	120058	120058	120058
60204	120149	899	1	1	1	1	1	0	7	0	0	2	120026	119530	109464	25	60103	40104	10002	10000	30100	10000	10000	1079423	5736374	6117518	1	120033	120041	120057	111903	3	112410	50100	30200	20000	10000	60200	10000	10000	120057	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	2	1	10000	0	0	0	10000	1	1	1	1	1	0	3212	7	121	7	7	119669	10001	40004	10	10	0	10000	10000	40100	120058	120058	120058	120058	120058
60204	120057	899	1	1	1	1	1	0	2	1	0	3	120042	119512	109464	25	60106	40104	10002	10000	30100	10000	10000	1079423	5736374	6119172	1	120033	120041	120057	111903	3	112415	50100	30200	20000	10000	60200	10000	10000	120057	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10002	0	0	1	10000	1	1	1	1	1	0	3212	7	121	7	7	119669	10001	40004	10	10	9	10000	10000	40100	120058	120058	120058	120058	120058
60204	120057	899	1	1	1	1	0	0	2	1	0	2	120042	119512	109575	25	60106	40104	10002	10000	30100	10000	10000	1079368	5736374	6117518	1	120017	120041	120057	111903	3	112410	50100	30200	20000	10000	60200	10000	10000	120057	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	2	0	10002	0	2	1	10000	1	1	1	1	1	0	3212	7	121	7	7	119669	10001	40002	10	10	9	10000	10000	40100	120058	120058	120058	120058	120058
60204	120057	899	1	1	0	1	1	0	2	1	0	1	120042	119512	109452	25	60106	40104	10002	10000	30100	10009	10000	1079368	5735593	6117518	1	120033	120057	120057	111903	3	112415	50100	30200	20000	10000	60200	10000	10000	120057	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	3	1	10002	0	1	1	10000	1	1	1	1	0	0	3212	7	100	7	5	119669	10001	40004	0	10	9	10000	10000	40100	120058	120058	120058	120058	120058
60204	120041	899	1	1	0	1	1	0	2	1	0	1	120026	119512	109464	25	60106	40112	10001	10000	30100	10000	10000	1079368	5736374	6117518	1	120017	120057	120057	111903	3	112415	50100	30200	20000	10000	60200	10000	10000	120041	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	3	1	10003	0	1	1	10000	1	1	1	1	1	0	3212	7	100	6	6	119669	10001	40004	10	11	0	10000	10000	40100	120042	120042	120058	120058	120058
60204	120057	899	1	1	1	1	0	0	2	1	0	1	120045	119512	109471	25	60106	40102	10002	10000	30100	10000	10000	1079423	5736374	6117518	1	120033	120057	120057	111903	3	112410	50100	30200	20000	10000	60200	10000	10000	120057	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10002	0	0	1	10000	0	1	1	1	1	0	3212	7	121	7	7	119670	10001	40002	10	0	9	10000	10000	40100	120042	120058	120058	120058	120058
60204	120057	899	1	1	1	1	1	0	2	1	0	2	120042	119512	109464	25	60106	40104	10002	10000	30100	10000	10000	1079423	5736374	6119172	1	120033	120057	120041	111903	3	112410	50100	30200	20000	10000	60200	10000	10000	120057	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10003	0	1	1	10000	1	1	1	1	1	0	3212	7	121	7	6	119651	10001	40004	10	10	0	10000	10000	40100	120058	120058	120058	120042	120042

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120053	899	0	0	0	1	0	0	0	21	0	1	0	0	120035	119483	109443	25	60010	40012	10000	10000	30010	10000	10000	1079769	5735888	6125581	0	0	120023	0	120047	120050	111918	0	3	112444	50010	30020	20000	10000	60020	10000	10000	120035	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	15	10000	1	1	0	0	0	3140	0	0	0	1	99	0	0	1	1	119665	10000	40002	6	6	0	10000	10000	40010	120036	120036	120051	120051	120048
60024	120047	899	0	0	0	1	1	0	0	1	0	1	0	0	120035	119483	109455	25	60013	40010	10001	10000	30010	10000	10000	1079769	5735888	6125581	0	0	120026	0	120035	120035	111918	0	3	112447	50010	30020	20000	10000	60020	10000	10000	120050	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	0	1	0	0	0	3140	0	0	0	1	99	0	0	1	1	119766	10000	40000	9	0	5	10000	10000	40010	120051	120036	120048	120051	120051
60024	120050	899	0	0	0	1	0	0	0	1	0	0	0	0	120035	119483	109458	25	60013	40012	10001	10000	30010	10000	10000	1079769	5736035	6125581	0	0	120026	0	120050	120047	111918	0	3	112447	50010	30020	20000	10000	60020	10000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	3140	0	0	0	1	99	0	0	1	1	119665	10000	40002	9	6	8	10000	10000	40010	120048	120048	120048	120036	120036
60024	120050	899	0	0	0	0	0	0	0	1	0	1	0	0	120020	119483	109458	25	60013	40010	10001	10000	30010	10000	10000	1079845	5736035	6125581	0	1	120011	0	120050	120050	111903	0	3	112447	50010	30020	20000	10000	60020	10000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	3	10000	0	0	0	0	0	3140	0	0	0	1	94	0	0	1	1	119665	10000	40000	9	9	8	10000	10000	40010	120036	120051	120036	120051	120051
60024	120035	899	0	0	0	0	0	0	0	6	0	0	0	0	120032	119483	109458	25	60013	40012	10001	10000	30010	10000	10000	1079845	5736035	6124344	0	0	120023	0	120050	120050	111903	0	3	112437	50010	30020	20000	10000	60020	10000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	0	0	0	0	0	3140	0	0	0	1	99	0	0	1	1	119668	10000	40002	9	6	8	10000	10000	40010	120051	120051	120051	120036	120036
60024	120050	899	0	0	0	0	1	0	0	10	0	0	0	0	120020	119489	109444	25	60013	40012	10001	10000	30010	10000	10000	1079845	5735888	6125714	0	0	120026	0	120050	120050	111918	0	3	112447	50010	30020	20000	10000	60020	10000	10000	120047	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	3140	0	0	0	1	94	0	0	1	1	119665	10000	40002	9	6	0	10000	10000	40010	120051	120048	120036	120051	120051
60024	120035	899	0	0	0	0	0	0	0	1	0	1	0	0	120052	119480	109455	25	60013	40010	10001	10000	30010	10000	10000	1079845	5736035	6125581	0	0	120026	0	120035	120050	111903	0	3	112444	50010	30020	20000	10000	60020	10000	10000	120047	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10032	4	0	10030	1	0	85931	10032	1	0	0	0	0	3860	0	0	0	2	319	0	0	3	3	120337	10037	40189	6	6	8	10000	10000	40010	120051	120036	120051	120051	120036
60024	120050	900	2	1	0	1	0	26	26	2655	2376	1	0	0	122900	120896	110245	950	60325	40240	10059	10054	34175	11627	11231	1153404	5805710	6178215	0	1	122446	0	124062	123416	112630	0	513	114313	59892	34999	24170	11927	70710	12026	11771	123717	123680	34	1	50021	10	9	10	40010	10000	10000	0	10	10001	0	0	10000	1	2	14525	10033	1	0	2	0	0	3140	0	0	0	1	94	0	0	5	4	121217	10040	40180	9	9	0	10000	10000	40010	120051	120053	120036	120051	122054
60024	120431	931	0	1	1	0	1	0	0	202	0	1	0	0	120035	120495	109562	961	60337	40256	10063	10064	35062	11897	11384	1151571	5804715	6190251	0	1	120026	0	120047	120047	111903	0	354	112447	50010	30020	20000	10000	60020	10000	10000	120115	120037	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	4	10000	0	1	0	0	0	3140	0	0	0	1	94	0	0	1	1	119672	10000	40002	10	10	12	10000	10000	40010	120055	120055	120055	120055	120055
60024	120051	899	0	0	0	1	1	0	0	1	0	0	0	1	120039	119484	109461	25	60010	40012	10001	10000	30010	10000	10000	1079858	5736230	6125746	0	1	120030	0	120035	120051	111987	0	3	112465	50010	30020	20000	10000	60020	10000	10000	120035	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	2	0	28729	10000	1	1	0	0	0	3140	0	0	0	1	99	0	0	1	1	119650	10000	40002	10	10	9	10000	10000	40010	120055	120052	120055	120055	120052

Test 4: throughput

Count: 8

Code:

  ldnp d0, d1, [x6]
  ldnp d0, d1, [x6]
  ldnp d0, d1, [x6]
  ldnp d0, d1, [x6]
  ldnp d0, d1, [x6]
  ldnp d0, d1, [x6]
  ldnp d0, d1, [x6]
  ldnp d0, d1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160205	26727	200	0	0	45	1	0	0	26714	2	12	18	18	25	80100	100	80000	100	80000	500	1168754	0	26702	26727	26722	6645	3	6685	80100	200	160000	200	80000	26722	26722	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	39	0	80035	0	1	42	80039	6	1	35	0	0	5110	2	16	2	2	26724	80035	10	6	2	80000	80000	100	26727	26728	26967	26740	26723
160204	26731	200	1	0	41	1	0	0	26712	2	12	18	118	25	80100	100	80000	100	80000	500	1174628	0	26706	26731	26707	6650	3	6685	80100	200	160000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	39	0	80035	0	0	38	80039	6	1	35	39	0	5110	2	16	2	2	26719	80000	6	6	4	80000	80000	100	26732	26728	26964	26739	26728
160204	26727	200	0	0	0	1	0	1	26712	3	12	0	125	25	80100	100	80000	100	80000	500	1174628	0	26702	26727	26727	6650	3	6680	80100	200	160000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	39	30	80039	0	1	39	80039	6	1	0	39	4	5110	2	16	2	2	26724	80039	10	8	4	80000	80000	100	26753	26729	26708	26728	26728
160204	26717	200	0	0	41	1	0	2	26712	2	12	12	16	25	80100	100	80000	100	80000	500	1173183	0	26702	26727	26707	6630	3	6680	80100	200	160000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	0	80039	0	0	39	80039	6	1	35	0	0	5110	2	16	2	2	26724	80039	10	10	4	80000	80000	100	26732	26738	26723	26728	26708
160204	26727	200	0	0	41	0	0	2	26692	2	12	12	16	25	80100	100	80000	100	80000	500	1170107	0	26697	26722	26727	6650	3	6685	80100	200	160000	200	80000	26727	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	0	80039	0	0	39	80035	6	1	35	43	0	5110	2	16	2	2	26724	80039	0	0	4	80000	80000	100	26734	26730	26723	26708	26728
160204	26727	200	0	0	45	0	0	2	26692	2	12	18	16	25	80100	100	80000	100	80000	500	1174628	0	26682	26707	26727	6630	3	6685	80100	200	160000	200	80000	26727	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	0	80039	0	0	39	80035	6	1	0	43	0	5110	2	16	2	2	26724	80039	10	10	4	80000	80000	100	26736	26731	26732	26723	26728
160204	26727	200	0	0	45	0	0	2	26692	2	12	18	16	25	80100	100	80000	100	80000	500	1168754	0	26697	26707	26722	6652	3	6685	80100	200	160000	200	80000	26707	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	0	80035	0	0	39	80039	6	1	0	43	0	5110	2	16	2	2	26724	80039	6	6	2	80000	80000	100	26731	26715	26737	26735	26728
160204	26727	200	0	0	45	0	0	2	26712	2	12	12	25	25	80100	100	80000	100	80000	500	1168880	0	26702	26707	26722	6645	3	6685	80100	200	160000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	0	80039	0	0	39	80039	6	1	0	43	0	5110	2	16	2	2	26719	80039	10	10	2	80000	80000	100	26708	26723	26877	26782	26724
160204	26727	200	0	0	45	1	0	2	26712	2	12	12	20	25	80100	100	80000	100	80000	500	1174628	0	26782	26727	26707	6645	3	6680	80100	200	160000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	39	0	80035	0	0	39	80039	6	1	39	43	0	5110	2	16	2	2	26724	80039	10	10	4	80000	80000	100	26840	26727	26740	26811	26728
160204	26722	200	1	1	45	0	0	2	26712	2	18	18	70	25	80100	100	80000	100	80000	500	1170107	0	26702	26727	26727	6645	3	6680	80100	200	160000	200	80000	26707	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	0	80035	0	0	39	80035	6	1	35	43	0	5110	2	16	2	2	26724	80039	10	6	0	80000	80000	100	26737	26748	26734	26728	26728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160025	26722	200	0	0	0	1	0	0	41	0	0	0	26692	0	0	12	76	25	80010	10	80000	10	80000	50	1174628	26702	26707	26722	6668	3	6702	80010	20	160000	20	80000	26707	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	0	80039	0	39	80039	6	1	0	0	5020	28	16	26	26	26719	80035	10	6	0	80000	80000	10	26743	26743	26728	26728	26723
160024	26727	200	0	0	0	0	1	0	45	0	1	0	26692	0	18	0	16	25	80010	10	80000	10	80000	50	1168880	26682	26724	26707	6653	3	6711	80010	20	160000	20	80000	26727	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	0	80039	0	39	80035	0	1	35	43	5020	24	16	14	24	26704	80035	10	6	0	80000	80000	10	26811	26734	26731	26723	26728
160024	26727	200	0	0	0	0	0	0	0	0	1	2	26712	2	0	12	3	25	80010	10	80000	10	80000	50	1173183	26702	26710	26722	6672	3	6687	80010	20	160000	20	80000	26707	26722	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	39	0	80035	0	39	80039	6	1	39	39	5020	26	16	13	25	26704	80000	0	6	2	80000	80000	10	26825	26730	26716	26723	26728
160024	26722	200	0	0	0	0	0	0	46	0	1	2	26707	2	12	0	14	25	80010	10	80000	10	80000	50	1170107	26682	26722	26727	6653	3	6707	80010	20	160000	20	80000	26722	26731	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	43	0	80035	2	39	80000	6	1	35	43	5020	12	16	24	13	26724	80039	0	6	4	80000	80000	10	26723	26735	26713	26708	26718
160024	26715	200	0	0	0	0	0	0	0	0	0	0	26712	2	12	18	0	25	80010	10	80000	10	80000	50	1168880	26702	26727	26707	6672	3	6687	80010	20	160384	20	80000	26727	26722	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	0	0	80035	0	39	80000	6	1	0	39	5020	25	16	15	24	26719	80035	10	0	4	80000	80000	10	26807	26734	26742	26723	26708
160024	26727	200	0	0	0	0	0	0	41	0	0	0	26712	0	18	0	12	25	80010	10	80000	10	80000	50	1170107	26682	26707	26722	6668	3	6687	80010	20	160000	20	80000	26707	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	0	80035	0	38	80000	6	0	35	0	5020	20	16	26	21	26719	80039	6	0	4	80000	80000	10	26734	26739	26723	26728	26728
160024	26727	200	0	0	0	0	0	0	45	0	1	0	26692	2	12	0	0	25	80010	10	80000	10	80000	50	1168754	26697	26707	26727	6673	3	6707	80010	20	160000	20	80000	26727	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	0	80000	54	0	80000	6	0	35	39	5020	13	16	26	13	26704	80039	10	10	4	80000	80000	10	26739	26737	26708	26728	26708
160024	26722	201	0	0	0	0	0	0	0	0	1	0	26712	2	12	0	17	25	80010	10	80000	10	80000	50	1170107	26702	26727	26707	6673	3	6707	80010	20	160000	20	80000	26707	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	0	80039	0	39	80000	6	0	35	43	5020	19	16	25	12	26724	80000	0	0	0	80000	80000	10	26883	26931	27006	26936	26723
160024	26727	200	0	0	0	0	0	0	0	0	1	0	26712	2	12	18	2	25	80010	10	80000	10	80000	50	1168880	26907	26722	26707	6672	3	6702	80010	20	160000	20	80000	26727	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	0	80016	0	96	80039	6	1	39	43	5020	28	25	20	26	26704	80000	0	0	4	80000	80000	10	26728	26728	26855	26778	26727
160024	27043	202	1	1	0	0	0	0	197	104	0	0	26712	2	18	0	342	60	80010	10	80000	10	80000	50	1173183	26706	26727	26727	6672	3	6687	80010	20	160000	20	80000	26727	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	0	80039	3	39	80000	6	1	39	43	5020	26	16	13	25	26704	80035	0	6	2	80000	80000	10	26743	26725	26740	26728	26708

LDNP (D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations