Firestorm: LDNP (Q) measurements

Code:

  ldnp q0, q1, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
2005	727	6	45	0	1	713	2	12	12	16	25	2000	2000	2000	29597	1	705	727	727	425	3	460	2000	2000	2000	728	727	1	1	1001	1000	1000	1	2000	43	2039	0	39	2039	6	1	39	43	73	5	16	6	6	724	2039	10	10	4	2000	728	734	728	728	728
2004	727	5	45	0	1	712	2	12	12	16	25	2000	2000	2000	29624	1	702	732	732	429	3	464	2000	2000	2000	727	727	1	1	1001	1000	1000	0	2000	43	2040	0	38	2038	6	1	38	44	73	6	16	6	6	729	2038	10	10	7	2000	733	732	732	733	732
2004	732	5	44	0	1	717	2	1	1	16	25	2000	2000	2000	29873	1	702	731	727	429	3	461	2000	2000	2000	731	727	1	1	1001	1000	1000	1	2000	43	2039	0	38	2038	6	1	39	44	73	6	16	6	6	729	2038	14	14	7	2000	733	734	733	733	732
2004	727	5	44	0	1	716	2	1	1	19	25	2000	2000	2000	29850	1	707	731	732	429	3	464	2000	2000	2000	732	727	1	1	1001	1000	1000	1	2000	43	2039	0	39	2000	6	1	39	44	73	6	16	6	6	725	2038	10	10	7	2000	729	732	733	733	732
2004	732	5	45	0	1	717	2	1	1	19	25	2000	2000	2000	29624	1	707	731	732	429	3	461	2000	2000	2000	732	727	1	1	1001	1000	1000	0	2000	43	2039	1	39	2038	6	1	39	44	73	6	16	5	5	724	2038	14	14	7	2000	733	732	732	733	732
2004	727	5	46	0	1	717	2	1	1	16	25	2000	2000	2000	33122	1	706	731	731	425	3	465	2000	2000	2000	727	727	1	1	1001	1000	1000	0	2000	43	2039	0	38	2039	6	1	39	44	73	6	16	6	6	728	2038	14	14	4	2000	732	728	733	732	732
2004	732	5	44	0	1	716	2	1	12	19	25	2000	2000	2000	29873	1	706	731	731	449	3	464	2000	2000	2000	731	727	1	1	1001	1000	1000	0	2000	43	2039	0	38	2039	6	1	38	44	73	6	16	6	6	728	2038	14	10	7	2000	732	732	733	732	732
2004	790	5	62	0	1	716	2	12	1	19	25	2000	2000	2000	29873	1	705	731	731	430	3	465	2000	2000	2000	731	727	1	1	1001	1000	1000	0	2000	43	2039	0	38	2038	6	1	38	44	73	6	16	6	6	728	2038	14	14	7	2000	732	732	728	729	732
2004	732	5	44	0	1	721	2	12	1	16	25	2000	2000	2000	29763	1	706	732	731	429	3	465	2000	2000	2000	728	728	1	1	1001	1000	1000	0	2000	43	2039	0	39	2039	6	1	39	43	73	6	16	6	5	729	2038	14	10	4	2000	733	739	732	733	732
2004	731	6	44	0	1	716	2	1	1	19	25	2000	2000	2000	29850	1	707	732	732	429	3	464	2000	2000	2000	732	727	1	1	1001	1000	1000	0	2000	43	2039	0	39	2038	0	1	39	44	73	6	16	6	6	728	2038	14	14	7	2000	729	728	728	729	733

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldnp q0, q1, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0055

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60206	120073	968	0	0	0	0	1	1	0	0	4	0	1	0	0	120042	96716	109736	25	70100	40102	10001	20000	30100	10000	20000	10427265	5733532	3465684	1	120033	0	120057	120041	112145	3	112515	60100	30200	20000	10000	60200	20000	10000	120053	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	20002	3	2	20004	0	1	2	20000	2	2	0	2	0	3210	1	16	1	0	119824	20000	40002	6	6	9	20000	40100	120048	120052	120036	120052	120052
60204	120047	899	0	0	0	0	1	0	0	0	2	0	0	0	0	120020	96716	109724	25	70103	40102	10001	20000	30100	10000	20000	10425228	5733436	3465510	1	120023	0	120051	120051	112139	3	112509	60100	30200	20000	10000	60200	20000	10000	120051	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	0	20000	0	0	0	20000	2	0	2	0	0	3210	1	16	1	1	119820	20000	40002	10	6	9	20000	40100	120052	120048	120052	120052	120048
60204	120035	900	0	0	0	0	0	0	0	0	2	0	0	0	1	120036	97403	109743	25	70100	40102	10001	20000	30100	10000	20000	10426743	5733436	3465156	0	120027	3	120051	120052	112139	3	112524	60100	30200	20000	10000	60200	20000	10000	120057	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	1	0	0	20000	2	0	2	0	0	3210	1	16	1	1	119883	20000	40002	10	10	9	20000	40100	120036	120096	120080	120053	120052
60204	120035	899	0	0	0	0	0	0	0	0	2	0	0	0	1	120036	96712	109740	25	70103	40102	10000	20000	30100	10000	20000	10426743	5733436	3465510	1	120023	0	120052	120035	112141	3	112493	60100	30200	20000	10000	60200	20000	10000	120053	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	20008	2	0	20000	1	2	3	20008	0	2	0	0	0	3220	1	16	1	3	120199	20006	40002	10	0	9	20000	40100	120052	120052	120052	120036	120048
60204	120052	955	0	0	0	0	0	0	0	0	0	0	0	0	0	120040	96720	109744	25	70103	40102	10001	20000	30100	10000	20000	10427091	5732666	3465626	0	120031	0	120035	120051	112143	3	112513	60100	30200	20000	10000	60200	20000	10000	120052	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	3	20000	2	0	2	0	0	3210	1	16	1	1	119904	20002	40022	14	0	0	20000	40100	120058	120036	120062	120238	120056
60204	120192	904	0	1	1	0	0	0	0	0	18	0	0	1	1	120040	96720	109744	25	70103	40102	10001	20000	30100	10000	20000	10425228	5733628	3465626	0	120011	0	120051	120051	112139	3	112514	60100	30200	20000	10000	60200	20000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	2	0	3	20000	2	0	2	0	0	3210	1	16	1	1	119828	20004	40002	0	10	9	20000	40100	120053	120057	120056	120057	120036
60204	120055	899	0	0	0	0	0	0	0	0	2	0	0	0	1	120083	96720	109744	25	70100	40102	10000	20000	30100	10000	20000	10427091	5732762	3465156	1	120031	0	120051	120035	112143	3	112513	60100	30200	20000	10000	60200	20000	10000	120055	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	20000	2	0	2	0	0	3210	1	16	1	1	119828	20000	40002	0	14	9	20000	40100	120052	120056	120052	120036	120056
60204	120055	899	0	0	0	0	0	0	0	0	2	0	0	0	0	120040	96723	109744	25	70100	40102	10000	20000	30100	10031	20000	10427091	5732666	3465626	1	120011	0	120035	120055	112143	3	112513	60100	30200	20000	10000	60200	20000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	0	2	20000	0	0	0	20000	0	0	0	0	0	3210	1	16	1	1	119828	20000	40010	0	14	13	20000	40100	120036	120056	120036	120056	120036
60204	120055	935	0	0	0	0	0	0	0	0	0	0	0	0	0	120040	96720	109724	25	70103	40102	10001	20000	30100	10000	20000	10425228	5732666	3465626	1	120031	0	120055	120035	112143	3	112513	60100	30200	20000	10000	60200	20000	10000	120055	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	20003	2	0	20002	0	1	2	20000	2	2	2	2	0	3210	1	16	1	1	119834	20000	40002	10	10	9	20000	40100	120056	120041	120056	120056	120056
60204	120055	899	0	0	0	0	0	0	0	0	2	0	0	1	1	120020	96720	109724	25	70103	40102	10001	20000	30100	10000	20000	10427091	5733436	3465626	1	120027	0	120051	120051	112139	3	112509	60100	30200	20000	10000	60200	20000	10000	120055	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	0	20000	0	0	0	20000	2	0	0	0	0	3210	1	16	1	1	119882	20000	40002	14	0	9	20000	40100	120036	120056	120056	120056	120060

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	18	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120047	899	1	0	1	2	11	1	0	0	120032	93975	109724	25	70013	40010	10000	20000	30010	10000	20000	10425026	5733244	3464880	120023	120047	120047	112146	3	112527	60010	30020	20000	10000	60020	20000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	1	10	20000	0	20000	0	0	0	20000	2	0	0	0	0	3140	4	16	4	6	119822	20000	40002	76	6	9	20000	40010	120048	120048	120048	120048	120048
60024	120047	899	0	1	0	0	690	1	0	0	120020	96637	109736	25	70013	40012	10001	20000	30010	10000	20000	10425026	5733244	3465234	120023	120047	120047	112158	3	112527	60010	30020	20000	10000	60020	20000	10000	120035	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	0	20000	2	2	0	0	0	3140	4	16	4	6	119822	20000	40002	75	0	0	20000	40010	120036	120036	120036	120048	120048
60024	120047	899	0	1	1	0	2	0	0	0	120032	96637	109736	25	70013	40010	10001	20000	30010	10000	20000	10425026	5733244	3465234	120129	120035	120055	112158	3	112515	60010	30020	20000	10000	60020	20000	10000	120035	120088	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	0	20000	2	2	0	0	0	3140	5	16	5	3	119822	20000	40002	56	6	5	20000	40010	120048	120036	120048	120048	120036
60024	120047	899	0	0	0	0	2	1	0	0	120032	93975	109724	25	70013	40010	10001	20000	30010	10000	20000	10425026	5733244	3465234	120023	120047	120047	112158	3	112527	60010	30020	20000	10000	60020	20000	10000	120047	120035	1	1	50021	10	9	10	40010	10000	10000	1	10	20000	2	20000	0	0	0	20000	2	2	0	0	0	3140	5	16	5	5	119822	20000	40000	56	6	5	20000	40010	120048	120048	120048	120036	120048
60024	120047	899	0	0	0	0	2	1	0	0	120032	96637	109736	25	70013	40010	10001	20000	30010	10000	20000	10425026	5732666	3466666	120011	120035	120047	112158	3	112527	60010	30020	20000	10000	60020	20000	10000	120035	120047	1	1	50021	10	9	10	40010	10000	10000	1	10	20000	2	20000	0	0	0	20000	2	2	0	0	0	3140	5	16	5	3	119822	20000	40000	56	6	5	20000	40010	120048	120048	120048	120048	120048
60024	120047	900	0	0	0	0	2	1	0	0	120020	96637	109736	25	70013	40012	10000	20000	30010	10000	20000	10425026	5733244	3464880	120023	120047	120047	112158	3	112527	60010	30020	20000	10000	60020	20000	10000	120047	120035	1	1	50022	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	0	20000	2	2	0	0	0	3140	6	16	4	5	119822	20000	40002	56	6	5	20000	40010	120048	120048	120036	120048	120086
60024	120047	899	0	0	0	0	2	1	0	0	120032	96637	109724	25	70013	40010	10000	20000	30010	10000	20000	10425026	5733244	3465234	120023	120035	120035	112146	3	112531	60010	30020	20000	10000	60020	20000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	0	20000	2	2	0	0	0	3140	3	16	6	6	119822	20000	40002	56	6	5	20000	40010	120036	120036	120052	120048	120036
60024	120047	900	0	0	1	0	2	0	0	0	120032	96640	109736	42	70010	40010	10000	20000	30010	10000	20000	10423974	5733244	3465234	120023	120035	120047	112158	3	112527	60010	30020	20000	10000	60020	20000	10000	120047	120075	1	1	50021	10	9	10	40010	10000	10000	1	10	20000	2	20000	1	0	0	20000	2	2	0	0	0	3140	7	16	4	6	119822	20000	40002	71	6	5	20000	40010	120048	120048	120036	120036	120048
60024	120035	899	0	0	0	0	0	1	0	0	120032	93975	109736	25	70010	40012	10001	20000	30010	10000	20000	10423974	5733244	3464880	120023	120047	120035	112158	3	112527	60010	30020	20000	10033	60020	20000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	1	10	20000	2	20000	0	0	0	20000	2	2	0	0	0	3140	5	16	4	5	119822	20000	40002	56	0	5	20000	40010	120048	120052	120048	120048	120036
60024	120047	899	0	0	0	0	2	1	0	0	120032	93975	109736	25	70013	40010	10001	20000	30010	10000	20000	10423974	5733244	3464880	120011	120047	120051	112158	3	112515	60010	30020	20000	10000	60020	20000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	0	20000	2	2	0	0	0	3140	5	16	5	6	119810	20000	40002	56	6	5	20000	40010	120049	120048	120048	120036	120048

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldnp q0, q1, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120047	899	1	1	2	1	0	120041	96712	109724	25	70103	40102	10001	20000	30100	10000	20000	10426743	5733436	3465156	120023	120047	120035	112139	3	112505	60100	30200	20000	10000	60200	20000	10000	120051	120047	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	0	20000	0	0	3	20000	2	2	3210	1	16	1	1	119808	20002	40000	10	6	5	20000	40100	120052	120048	120036	120052	120052
60204	120047	899	0	0	2	1	0	120020	97403	109736	25	70103	40100	10001	20000	30100	10000	20000	10426743	5732666	3465156	120023	120047	120051	112135	3	112509	60100	30200	20000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	2	20000	0	0	0	20000	2	0	3210	1	16	1	1	119808	20000	40002	0	6	9	20000	40100	120052	120052	120052	120036	120048
60204	120092	899	0	0	2	1	1	120036	96712	109736	25	70100	40102	10001	20000	30100	10000	20000	10425228	5732810	3465156	120027	120051	120051	112135	3	112509	60100	30200	20000	10000	60200	20000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	20008	2	20000	0	0	0	20000	2	2	3210	1	16	1	1	119824	20000	40002	10	0	0	20000	40100	120036	120036	120052	120036	120036
60204	120047	899	0	0	2	0	0	120023	96720	109724	25	70103	40100	10001	20000	30100	10000	20000	10425228	5733244	3465510	120011	120035	120058	112139	3	112493	60100	30200	20000	10000	60200	20000	10000	120051	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	0	20000	2	2	3210	1	16	1	1	119809	20000	40002	10	0	9	20000	40100	120036	120036	120052	120048	120148
60204	120035	899	0	1	0	1	1	120032	96716	109740	25	70103	40102	10000	20000	30100	10000	20000	10426743	5733436	3465510	120023	120035	120035	112135	3	112493	60100	30200	20000	10000	60200	20000	10000	120051	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	20000	0	0	0	20000	0	2	3210	1	16	1	1	119824	20000	40002	10	0	0	20000	40100	120036	120052	120048	120036	120048
60204	120051	899	0	1	2	1	1	120038	97403	109724	25	70103	40102	10001	20000	30100	10000	20000	10426395	5732666	3465156	120023	120035	120047	112123	3	112509	60100	30200	20000	10000	60200	20000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	0	20000	0	0	0	20000	2	2	3210	1	16	1	1	119824	20000	40002	0	6	5	20000	40100	120052	120036	120048	120048	120048
60204	120047	899	1	1	2	1	1	120020	96716	109740	25	70100	40102	10001	20000	30100	10000	20000	10425228	5732666	3465510	120027	120035	120051	112139	3	112509	60100	30200	20000	10000	60200	20000	10000	120051	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	0	20000	0	2	3239	1	16	1	1	119824	20000	40002	10	6	9	20000	40100	120052	120052	120052	120036	120052
60204	120047	899	0	0	2	1	0	120034	96712	109740	25	70100	40102	10001	20000	30100	10000	20000	10426395	5733244	3465510	120027	120047	120035	112135	3	112505	60100	30200	20000	10000	60200	20000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	1	0	0	20000	2	0	3210	1	16	1	1	119820	20000	40002	10	0	9	20000	40100	120036	120048	120052	120036	120049
60204	120051	899	0	0	0	0	0	120032	96712	109724	25	70103	40102	10000	20000	30100	10000	20000	10425228	5733436	3465510	120027	120047	120047	112139	3	112509	60100	30200	20000	10000	60200	20000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	1	0	0	20000	2	0	3210	1	16	1	1	119824	20000	40002	10	6	9	20000	40100	120036	120052	120052	120052	120052
60204	120035	899	0	0	2	0	1	120032	96716	109736	25	70103	40102	10001	20000	30100	10000	20000	10426743	5732666	3465626	120027	120051	120051	112139	3	112493	60100	30200	20000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	0	20000	0	0	0	20000	2	2	3210	1	16	1	1	119820	20000	40002	6	0	0	20000	40100	120049	120048	120036	120048	120036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120051	899	0	1	0	0	0	0	0	0	2	0	0	0	0	120036	93975	109744	25	70013	40010	10001	20000	30010	10000	20000	10423974	5733628	3465350	0	120027	0	120055	120051	112146	3	112535	60010	30020	20000	10000	60020	20000	10000	120122	120069	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	20000	2	2	0	0	0	0	3140	6	16	4	6	119826	20000	40000	10	0	0	20000	40010	120056	120056	120036	120052	120052
60024	120035	899	0	0	0	0	0	0	0	0	0	0	0	0	1	120040	93975	109744	25	70013	40010	10001	20000	30010	10000	20000	10425374	5733628	3465466	0	120011	0	120035	120059	112162	3	112531	60010	30020	20000	10000	60020	20000	10000	120051	120084	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	20000	0	0	20000	2	2	0	0	0	0	3140	4	16	3	4	119830	20000	40002	10	10	0	20000	40010	120056	120056	120036	120056	120052
60024	120051	899	0	0	0	0	0	0	0	0	99	0	0	0	0	120040	96645	109724	25	70013	40012	10001	20000	30010	10000	20000	10423974	5732666	3465466	0	120011	0	120055	120055	112166	3	112535	60010	30020	20000	10000	60020	20000	10000	120051	120096	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	20000	2	2	0	0	0	0	3140	4	17	4	4	119810	20000	40002	0	10	13	20000	40010	120036	120052	120052	120056	120056
60024	120035	899	0	0	0	0	0	0	0	0	2	0	0	0	1	120020	96641	109744	25	70013	40012	10001	20000	30010	10031	20000	10425635	5733772	3464880	1	120011	3	120051	120055	112146	3	112531	60010	30020	20000	10000	60020	20000	10000	120035	120099	5	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	3	20000	2	2	0	0	0	0	3140	4	16	3	4	119810	20000	40002	10	10	0	20000	40010	120150	120036	120198	120057	120036
60024	120055	900	0	0	0	0	0	0	0	0	11	0	0	0	0	120319	96641	109724	25	70013	40012	10000	20000	30010	10000	20000	10423974	5733628	3465350	0	120027	0	120051	120035	112166	3	112535	60010	30020	20000	10000	60020	20000	10000	120109	120059	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	1	0	20000	0	0	0	0	0	1	3140	4	16	4	4	119830	20000	40000	0	0	0	20000	40010	120056	120052	120052	120056	120052
60024	120055	899	0	0	0	0	0	0	0	0	14	0	0	0	1	120020	93975	109745	25	70010	40012	10001	20000	30010	10000	20000	10425374	5732666	3465466	0	120031	0	120215	120152	112202	3	112701	60184	30210	20000	10000	60020	20000	10000	120104	120279	4	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	1	3	20000	0	2	0	0	0	0	3140	4	16	4	3	119832	20000	40002	14	0	13	20000	40010	120056	120056	120037	120056	120037
60024	120035	899	0	0	0	0	0	0	0	0	2	0	0	0	0	120041	96647	109744	25	70013	40012	10000	20000	30010	10000	20000	10423974	5733628	3465350	0	120331	0	120035	120035	112166	3	112666	60010	30020	20000	10000	60020	20000	10000	120117	120036	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	20000	0	0	20000	2	2	0	0	0	0	3140	3	16	3	4	119830	20000	40002	14	14	13	20000	40010	120056	120036	120056	120052	120056
60024	120055	900	0	0	0	0	1	0	0	0	0	0	0	0	3	123349	97029	110915	582	70412	40236	10074	20112	32399	10795	21308	10552302	5802268	3507384	0	122060	0	122387	122381	113249	160	114046	64672	32578	21696	10887	64942	20944	10570	122334	122457	28	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20064	1	62653	20066	2	2	2	0	0	0	3668	5	169	9	14	121665	20062	40251	14	0	13	20000	40010	122444	122521	122150	122706	122647
60024	122098	917	1	0	2	1	0	0	36	42	5550	3080	0	0	0	120020	97032	110424	550	70359	40205	10076	20096	32675	10952	21312	10567063	5813944	3510164	0	120027	0	120051	120055	112162	87	112752	63470	32564	21454	10820	64942	21256	10951	122814	123283	34	1	50021	10	9	10	40010	10000	10000	0	10	20058	2	20000	0	0	20000	0	2	0	0	0	0	3140	4	16	3	7	119830	20022	40216	14	10	9	20000	40010	123574	123238	123263	123239	123068
60024	120055	930	0	0	0	1	1	1	0	0	15	0	0	1	0	120032	96637	109741	25	70010	40012	10001	20000	30010	10000	20000	10425374	5732714	3465234	0	120023	0	120047	120047	112146	3	112531	60010	30020	20000	10000	60020	20000	10000	120051	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	20000	2	2	0	0	0	0	3140	4	16	3	4	119810	20000	40000	10	6	0	20000	40010	120048	120052	120036	120036	120052

Test 4: throughput

Count: 8

Code:

  ldnp q0, q1, [x6]
  ldnp q0, q1, [x6]
  ldnp q0, q1, [x6]
  ldnp q0, q1, [x6]
  ldnp q0, q1, [x6]
  ldnp q0, q1, [x6]
  ldnp q0, q1, [x6]
  ldnp q0, q1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6674

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	09	0e	0f	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160205	53394	400	1	1	1	1	0	45	0	1	0	1	53383	2	1	1	13	25	160100	100	160000	100	160000	500	2333962	0	53373	53398	53398	33317	3	33332	160100	200	160000	200	160000	53394	53374	1	1	80201	100	99	100	100	80000	80000	1	100	160000	0	43	0	160000	0	0	38	160000	6	1	39	43	0	1	5110	1	16	1	1	53391	160038	0	10	0	160000	100	53375	53395	53395	53375	53395
160204	53398	400	0	0	0	0	0	44	0	0	0	0	53359	2	1	1	16	25	160100	100	160000	100	160000	500	2299840	0	53349	53398	53398	33321	3	33356	160100	200	160000	200	160000	53394	53394	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	0	160000	0	0	39	160038	0	0	0	44	0	0	5110	1	16	1	1	53395	160000	14	0	7	160000	100	53395	53395	53375	53399	53395
160204	53398	399	0	0	0	0	0	45	0	1	0	1	53359	2	12	12	16	25	160100	100	160000	100	160000	500	2333262	0	53369	53398	53394	33317	3	33332	160100	200	160000	200	160000	53374	53394	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	0	160038	0	0	38	160038	6	0	39	43	0	0	5110	1	16	1	1	53391	160038	10	10	0	160000	100	53395	53375	53395	53375	53399
160204	53394	400	0	0	0	0	0	44	0	1	0	0	53379	2	1	1	19	25	160100	100	160000	100	160000	500	2336264	0	53373	53374	53394	33320	3	33356	160100	200	160000	200	160000	53394	53394	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	0	160038	0	0	43	160038	6	1	39	44	0	0	5110	1	16	1	1	53391	160038	14	14	7	160000	100	53399	53375	53399	53375	53399
160204	53374	400	0	0	0	0	0	0	0	1	0	1	53379	2	1	12	0	25	160100	100	160000	100	160000	500	2336264	0	53373	53398	53374	33321	3	33356	160100	200	160000	200	160766	53374	53409	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	43	122	160000	0	0	38	160038	0	1	39	0	0	0	5110	1	16	1	1	53371	160038	14	0	4	160000	100	53399	53396	53396	53420	53405
160204	53398	400	0	0	0	0	0	44	0	1	0	1	53383	0	1	0	19	25	160100	100	160000	100	160000	500	2352275	0	53373	53398	53398	33320	3	33356	160100	200	160000	200	160000	53394	53374	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	43	0	160039	0	0	0	160038	0	1	39	44	0	0	5110	1	16	1	1	53371	160039	14	10	7	160000	100	53399	53399	53375	53399	53399
160204	53398	400	0	0	1	0	0	0	0	1	0	1	53383	2	1	12	0	25	160100	100	160000	100	160000	500	2332897	0	53349	53398	53374	33321	3	33332	160100	200	160000	200	160000	53398	53394	1	1	80201	100	99	100	100	80000	80000	1	100	160000	0	43	0	160000	0	0	38	160038	0	1	39	44	0	0	5110	1	16	1	1	53371	160054	14	0	7	160000	100	53397	53399	53467	53468	53375
160204	53374	400	0	0	0	1	0	0	0	0	0	0	53383	2	1	0	19	25	160100	100	160000	100	160000	500	2336264	0	53373	53374	53398	33321	3	33332	160100	200	160000	200	160000	53398	53394	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	0	160000	1	0	38	160000	0	1	38	44	0	0	5110	1	16	1	1	53395	160038	0	0	7	160000	100	53375	53399	53375	53375	53399
160204	53394	400	0	0	0	0	0	44	88	0	0	0	53383	2	0	12	0	25	160100	100	160000	100	160000	500	2332897	0	53349	53398	53398	33321	3	33356	160100	200	160000	200	160000	53398	53374	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	43	0	160038	0	0	39	160000	6	1	39	43	0	0	5110	1	16	1	1	53395	160038	10	14	7	160000	100	53399	53375	53399	53399	53395
160204	53394	399	0	0	0	0	0	45	0	0	0	1	53359	2	0	0	0	25	160100	100	160000	100	160000	500	2332897	0	53373	53374	53398	33296	3	33356	160100	200	160000	200	160768	53398	53489	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	43	0	160039	0	0	38	160000	6	1	0	44	0	0	5110	1	16	1	1	53395	160039	14	10	0	160000	100	53399	53399	53399	53375	53395

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160025	53402	400	1	1	0	0	0	0	21	1	0	1	53366	3	0	7	1	25	160010	10	160000	10	160000	50	2335132	1	53377	53867	53414	33354	3	33382	160010	20	160000	20	160000	53402	53402	1	1	80021	10	9	0	10	10	80000	80000	0	10	160020	20	43	0	160019	1	0	3	25	160039	6	1	59	43	19	0	5020	6	16	0	6	5	53400	160059	13	0	5	160000	10	53403	53404	53404	53403	53403
160024	53402	400	1	0	1	1	0	0	21	1	0	2	53398	0	7	0	19	25	160010	10	160000	10	160000	50	2332997	1	53377	53411	53408	33348	3	33382	160010	20	160000	20	160000	53403	53402	1	1	80021	10	9	0	10	10	80000	80000	0	10	160019	19	43	0	160019	1	0	0	61	160040	0	1	21	43	19	1	5020	2	16	0	2	3	53378	160019	0	13	5	160000	10	53403	53382	53382	53403	53403
160024	53402	400	1	0	1	0	0	0	21	0	0	2	53387	2	0	7	19	25	160010	10	160000	10	160000	50	2334678	1	53356	53411	53417	33348	3	33382	160010	20	160000	20	160000	53402	53402	1	1	80021	10	9	0	10	10	80000	80000	0	10	160019	19	43	0	160019	0	0	0	21	160000	6	1	59	43	19	2	5020	3	16	0	3	3	53399	160059	13	13	5	160000	10	53403	53403	53403	53403	53382
160024	53402	399	1	1	0	1	0	0	21	1	0	1	53387	0	0	7	1	25	160010	10	160000	10	160000	50	2332997	1	53377	53400	53408	33326	3	33382	160010	20	160000	20	160000	53402	53403	1	1	80021	10	9	0	10	10	80000	80000	0	10	160020	20	43	30	160019	1	1	2	30	160000	0	1	59	0	19	0	5020	6	16	0	3	3	53448	160059	13	0	5	160000	10	53403	53403	53404	53403	53406
160024	53402	400	1	1	0	0	0	0	67	0	0	3	53366	2	7	0	0	25	160010	10	160000	10	160000	50	2335781	1	53377	53392	53413	33347	3	33382	160010	20	160000	20	160000	53406	53402	1	1	80021	10	9	0	10	10	80000	80000	0	10	160019	19	43	0	160059	1	0	1	21	160039	0	0	19	0	19	1	5020	3	16	0	5	5	53399	160058	13	13	5	160000	10	53403	53403	53403	53403	53403
160024	53381	400	1	1	0	1	0	0	21	1	0	3	53478	0	7	7	1	25	160010	10	160000	10	160000	61	2346902	1	53623	53406	53385	33361	3	33364	160010	20	160000	20	160000	53853	53403	1	1	80021	10	9	0	10	10	80000	80000	0	10	160020	19	43	0	160058	0	0	2	21	160039	6	1	59	43	19	1	5020	6	16	0	5	3	53399	160059	13	13	0	160000	10	53411	53406	53403	53406	53382
160024	53381	400	1	1	1	1	0	0	66	1	0	2	53387	2	0	7	19	25	160010	10	160000	10	160000	50	2335781	1	53389	53402	53402	33326	3	33382	160010	20	160000	20	160000	53403	53402	1	1	80021	10	9	0	10	10	80000	80000	0	10	160019	19	43	0	160059	1	0	1	21	160039	6	1	59	45	19	1	5020	5	16	0	5	5	53399	160019	0	13	0	160000	10	53382	53403	53403	53403	53403
160024	53402	400	1	1	1	0	0	0	21	1	0	0	53366	3	7	7	0	25	160010	10	160000	10	160000	50	2329020	1	53356	53411	53418	33348	3	33383	160010	20	160000	20	160000	53406	53402	1	1	80021	10	9	0	10	10	80000	80000	0	10	160019	19	43	0	160019	0	1	1	21	160000	6	0	19	0	19	0	5020	5	16	0	5	5	53399	160019	13	13	5	160000	10	53403	53403	53403	53408	53405
160024	53417	400	1	0	0	1	0	0	66	1	0	1	53387	0	0	0	2	25	160010	10	160000	10	160000	50	2329020	1	53377	53419	53410	33326	3	33382	160010	20	160000	20	160000	53402	53402	1	1	80021	10	9	0	10	10	80000	80000	0	10	160019	20	43	0	160059	1	1	1	61	160040	6	1	19	0	18	1	5020	5	16	0	3	6	53399	160059	13	13	0	160000	10	53403	53404	53382	53403	53403
160024	53402	400	1	0	0	1	1	0	66	1	0	3	53387	0	7	7	0	25	160010	10	160000	10	160000	50	2328655	1	53403	53402	53402	33326	3	33361	160010	20	160000	20	160000	53402	53381	1	1	80021	10	9	0	10	10	80000	80000	0	10	160021	19	43	0	160060	0	0	0	61	160040	6	1	59	43	19	1	5020	3	16	0	6	5	53378	160019	13	13	0	160000	10	53403	53403	53382	53382	53403

LDNP (Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations