Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ldnp s0, s1, [x6]
mov x0, 1 mov x1, 2 mov x8, 0
(no loop instructions)
Retires: 2.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
retire uop (01) | cycle (02) | 03 | 0e | 0f | 1e | 22 | 23 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd load (98) | inst ldst (9b) | 9d | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ld nt uop (e6) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
2005 | 402 | 3 | 0 | 0 | 61 | 1 | 0 | 0 | 387 | 17 | 0 | 19 | 20 | 25 | 1000 | 1000 | 1000 | 15456 | 357 | 383 | 402 | 100 | 3 | 115 | 1000 | 2000 | 1000 | 402 | 402 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 0 | 1055 | 0 | 25 | 1055 | 6 | 1 | 25 | 44 | 73 | 1 | 16 | 1 | 1 | 399 | 1025 | 10 | 0 | 6 | 1000 | 1000 | 403 | 383 | 409 | 384 | 384 |
2004 | 402 | 3 | 0 | 0 | 70 | 1 | 0 | 1 | 387 | 25 | 4 | 19 | 20 | 25 | 1000 | 1000 | 1000 | 14453 | 377 | 402 | 402 | 100 | 3 | 139 | 1000 | 2000 | 1000 | 402 | 383 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 59 | 1025 | 0 | 58 | 1055 | 6 | 0 | 55 | 44 | 73 | 1 | 16 | 1 | 1 | 399 | 1055 | 10 | 10 | 6 | 1000 | 1000 | 403 | 384 | 403 | 403 | 403 |
2004 | 383 | 3 | 0 | 0 | 61 | 0 | 0 | 0 | 368 | 17 | 4 | 0 | 20 | 25 | 1000 | 1000 | 1000 | 15487 | 377 | 402 | 383 | 80 | 3 | 135 | 1000 | 2000 | 1000 | 402 | 402 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 59 | 1055 | 0 | 55 | 1055 | 6 | 0 | 55 | 0 | 73 | 1 | 16 | 1 | 1 | 380 | 1056 | 10 | 0 | 6 | 1000 | 1000 | 383 | 383 | 384 | 384 | 403 |
2004 | 402 | 3 | 1 | 1 | 61 | 1 | 0 | 1 | 387 | 25 | 4 | 0 | 20 | 25 | 1000 | 1000 | 1000 | 15456 | 357 | 402 | 385 | 100 | 3 | 135 | 1000 | 2000 | 1000 | 402 | 382 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 59 | 1025 | 0 | 25 | 1025 | 6 | 1 | 55 | 44 | 73 | 1 | 16 | 1 | 1 | 399 | 1055 | 10 | 10 | 6 | 1000 | 1000 | 384 | 403 | 403 | 403 | 403 |
2004 | 402 | 3 | 0 | 0 | 61 | 1 | 0 | 1 | 387 | 17 | 0 | 0 | 3 | 25 | 1000 | 1000 | 1000 | 15456 | 357 | 382 | 402 | 100 | 3 | 135 | 1000 | 2000 | 1000 | 402 | 383 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 59 | 1055 | 0 | 55 | 1055 | 6 | 1 | 25 | 44 | 73 | 1 | 16 | 1 | 1 | 380 | 1055 | 0 | 10 | 6 | 1000 | 1000 | 384 | 384 | 384 | 384 | 403 |
2004 | 402 | 3 | 1 | 0 | 61 | 1 | 0 | 1 | 387 | 17 | 0 | 19 | 20 | 25 | 1000 | 1000 | 1000 | 14515 | 358 | 402 | 402 | 100 | 3 | 135 | 1000 | 2000 | 1000 | 382 | 402 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 0 | 1055 | 0 | 55 | 1055 | 6 | 1 | 25 | 0 | 73 | 1 | 16 | 1 | 1 | 399 | 1055 | 10 | 0 | 6 | 1000 | 1000 | 403 | 403 | 384 | 403 | 384 |
2004 | 383 | 3 | 0 | 1 | 25 | 1 | 0 | 1 | 387 | 17 | 0 | 19 | 20 | 25 | 1000 | 1000 | 1000 | 15456 | 358 | 402 | 402 | 100 | 3 | 135 | 1000 | 2000 | 1000 | 402 | 383 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 59 | 1055 | 0 | 55 | 1025 | 6 | 1 | 55 | 0 | 73 | 1 | 16 | 1 | 1 | 379 | 1025 | 10 | 10 | 6 | 1000 | 1000 | 403 | 403 | 403 | 403 | 403 |
2004 | 402 | 2 | 0 | 0 | 61 | 0 | 0 | 1 | 387 | 17 | 4 | 0 | 20 | 25 | 1000 | 1000 | 1000 | 15499 | 377 | 402 | 402 | 100 | 3 | 135 | 1000 | 2000 | 1000 | 402 | 402 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 59 | 1055 | 0 | 55 | 1055 | 0 | 1 | 55 | 44 | 73 | 1 | 16 | 1 | 1 | 399 | 1055 | 10 | 10 | 6 | 1000 | 1000 | 383 | 403 | 403 | 403 | 384 |
2004 | 382 | 4 | 0 | 0 | 61 | 1 | 0 | 0 | 387 | 17 | 4 | 19 | 20 | 25 | 1000 | 1000 | 1000 | 15456 | 382 | 402 | 402 | 80 | 3 | 135 | 1000 | 2000 | 1000 | 402 | 382 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 59 | 1025 | 0 | 58 | 1055 | 6 | 1 | 25 | 44 | 73 | 1 | 16 | 1 | 1 | 399 | 1055 | 0 | 0 | 0 | 1000 | 1000 | 403 | 411 | 403 | 403 | 403 |
2004 | 402 | 3 | 1 | 0 | 61 | 0 | 0 | 1 | 387 | 17 | 4 | 19 | 20 | 25 | 1000 | 1000 | 1000 | 15499 | 381 | 383 | 407 | 100 | 3 | 135 | 1000 | 2000 | 1000 | 402 | 402 | 1 | 1 | 1001 | 1000 | 1000 | 1 | 1000 | 0 | 1025 | 0 | 25 | 1055 | 6 | 1 | 55 | 44 | 73 | 1 | 16 | 1 | 1 | 399 | 1055 | 10 | 10 | 0 | 1000 | 1000 | 384 | 403 | 403 | 403 | 383 |
Chain cycles: 3
Code:
ldnp s0, s1, [x6] fmov x0, d0 eor x8, x8, x0 eor x8, x8, x0 add x6, x6, x8
mov x0, 1 mov x1, 2 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 9.0047
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | l1d cache miss ld nonspec (bf) | c2 | branch cond mispred nonspec (c5) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ld nt uop (e6) | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
60205 | 120053 | 899 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 120032 | 119538 | 109443 | 25 | 60103 | 40102 | 10000 | 10000 | 30100 | 10000 | 10000 | 1079330 | 5736035 | 6117882 | 1 | 120023 | 0 | 120047 | 120050 | 111905 | 3 | 112421 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120047 | 120047 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10001 | 1 | 1 | 10002 | 0 | 1 | 1 | 10000 | 1 | 1 | 0 | 0 | 3210 | 1 | 100 | 1 | 1 | 119657 | 10000 | 40002 | 6 | 6 | 5 | 10000 | 10000 | 40100 | 120048 | 120036 | 120048 | 120036 | 120036 |
60204 | 120047 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 120032 | 119503 | 109455 | 25 | 60103 | 40102 | 10000 | 10000 | 30100 | 10000 | 10000 | 1079330 | 5735888 | 6117882 | 1 | 120023 | 0 | 120035 | 120047 | 111903 | 3 | 112421 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120035 | 120047 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 0 | 1 | 0 | 0 | 3210 | 1 | 100 | 1 | 1 | 119646 | 10000 | 40002 | 6 | 6 | 5 | 10000 | 10000 | 40100 | 120048 | 120048 | 120048 | 120048 | 120036 |
60204 | 120047 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 120020 | 119494 | 109455 | 25 | 60103 | 40100 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079330 | 5735888 | 6117882 | 1 | 120011 | 0 | 120047 | 120035 | 111903 | 3 | 112421 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120050 | 120035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 1 | 135 | 1 | 1 | 119646 | 10000 | 40002 | 6 | 6 | 8 | 10000 | 10000 | 40100 | 120036 | 120048 | 120036 | 120048 | 120036 |
60204 | 120047 | 899 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 120020 | 119538 | 109455 | 25 | 60103 | 40100 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079126 | 5735888 | 6117882 | 1 | 120023 | 0 | 120035 | 120050 | 111881 | 3 | 112421 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120047 | 120047 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 0 | 1 | 0 | 0 | 3210 | 1 | 100 | 1 | 1 | 119655 | 10000 | 40000 | 6 | 0 | 5 | 10000 | 10000 | 40100 | 120048 | 120048 | 120048 | 120048 | 120036 |
60204 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 120020 | 119538 | 109455 | 25 | 60100 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079330 | 5735888 | 6119034 | 0 | 120026 | 0 | 120047 | 120047 | 111894 | 3 | 112421 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120047 | 120047 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 3210 | 1 | 100 | 1 | 1 | 119657 | 10000 | 40002 | 6 | 0 | 0 | 10000 | 10000 | 40100 | 120036 | 120036 | 120048 | 120048 | 120048 |
60204 | 120047 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 120032 | 119494 | 109455 | 25 | 60103 | 40102 | 10001 | 10000 | 30250 | 10000 | 10000 | 1079126 | 5735888 | 6118250 | 1 | 120023 | 0 | 120047 | 120035 | 111895 | 3 | 112421 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120035 | 120047 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 3210 | 2 | 100 | 1 | 1 | 119646 | 10000 | 40000 | 9 | 6 | 5 | 10000 | 10000 | 40100 | 120048 | 120036 | 120048 | 120048 | 120048 |
60204 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 120034 | 119545 | 109443 | 25 | 60111 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079330 | 5735888 | 6117882 | 1 | 120011 | 0 | 120047 | 120047 | 111903 | 3 | 112421 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120047 | 120047 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 0 | 1 | 0 | 0 | 3210 | 1 | 100 | 1 | 1 | 119657 | 10000 | 40002 | 0 | 9 | 5 | 10000 | 10000 | 40100 | 120104 | 120036 | 120048 | 120048 | 120048 |
60204 | 120049 | 899 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 120032 | 119507 | 109446 | 25 | 60138 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079330 | 5735888 | 6118038 | 0 | 120014 | 0 | 120047 | 120047 | 111897 | 3 | 112421 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120047 | 120035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 1 | 135 | 1 | 1 | 119646 | 10000 | 40000 | 6 | 6 | 5 | 10000 | 10000 | 40100 | 120048 | 120048 | 120048 | 120048 | 120036 |
60204 | 120047 | 900 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 120032 | 119538 | 109455 | 25 | 60100 | 40100 | 10000 | 10000 | 30100 | 10000 | 10000 | 1079330 | 5735293 | 6117599 | 0 | 120023 | 0 | 120119 | 120035 | 111881 | 3 | 112517 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120047 | 120047 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 1 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 3210 | 1 | 135 | 1 | 1 | 119657 | 10000 | 40002 | 9 | 0 | 0 | 10000 | 10000 | 40100 | 120036 | 120036 | 120048 | 120048 | 120048 |
60204 | 120047 | 899 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 120032 | 119538 | 109443 | 25 | 60100 | 40100 | 10000 | 10000 | 30251 | 10000 | 10000 | 1079393 | 5735888 | 6117882 | 0 | 120023 | 0 | 120035 | 120047 | 111903 | 3 | 112374 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120035 | 120047 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 0 | 1 | 0 | 0 | 3210 | 1 | 100 | 1 | 1 | 119657 | 10000 | 40002 | 6 | 0 | 5 | 10000 | 10000 | 40100 | 120048 | 120036 | 120036 | 120048 | 120048 |
Result (median cycles for code, minus 3 chain cycles): 9.0047
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 22 | 23 | 3a | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | int prf full (71) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | df | e0 | ld nt uop (e6) | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
60025 | 120047 | 899 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 120020 | 119489 | 109491 | 25 | 60013 | 40010 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079809 | 5735888 | 6124344 | 0 | 120013 | 120050 | 120047 | 111915 | 0 | 3 | 112444 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120047 | 120047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3145 | 1 | 99 | 1 | 1 | 2 | 119650 | 10000 | 40002 | 0 | 6 | 5 | 10000 | 10000 | 40010 | 120048 | 120048 | 120048 | 120078 | 120048 |
60024 | 120050 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 120020 | 119480 | 109488 | 25 | 60010 | 40012 | 10000 | 10000 | 30010 | 10000 | 10000 | 1079769 | 5735293 | 6125581 | 0 | 120023 | 120047 | 120047 | 111903 | 0 | 3 | 112437 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120047 | 120047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3145 | 1 | 99 | 1 | 1 | 2 | 119650 | 10000 | 40002 | 6 | 6 | 5 | 10000 | 10000 | 40010 | 120036 | 120048 | 120054 | 120107 | 120048 |
60024 | 120047 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 120032 | 119559 | 109457 | 25 | 60013 | 40010 | 10001 | 10000 | 30010 | 10000 | 10000 | 1081911 | 5735437 | 6124344 | 0 | 120011 | 120047 | 120047 | 111915 | 0 | 3 | 112444 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120047 | 120047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 0 | 0 | 1 | 0 | 0 | 0 | 3145 | 1 | 99 | 1 | 1 | 2 | 119650 | 10002 | 40002 | 6 | 6 | 0 | 10000 | 10000 | 40010 | 120051 | 120036 | 120055 | 120093 | 120052 |
60024 | 120047 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 120035 | 119565 | 109456 | 25 | 60013 | 40010 | 10000 | 10002 | 30010 | 10000 | 10000 | 1079809 | 5735293 | 6125841 | 0 | 120011 | 120035 | 120047 | 111918 | 0 | 3 | 112444 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120035 | 120035 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 0 | 0 | 3145 | 1 | 94 | 1 | 1 | 2 | 119650 | 10000 | 40002 | 6 | 6 | 5 | 10000 | 10000 | 40010 | 120048 | 120048 | 120054 | 120091 | 120036 |
60024 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 120020 | 119486 | 109477 | 25 | 60013 | 40012 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079769 | 5735888 | 6125581 | 1 | 120023 | 120047 | 120047 | 111915 | 0 | 3 | 112559 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120035 | 120035 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 0 | 0 | 3145 | 1 | 99 | 1 | 1 | 2 | 119650 | 10000 | 40002 | 6 | 6 | 5 | 10000 | 10000 | 40010 | 120036 | 120048 | 120054 | 120076 | 120048 |
60024 | 120047 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 120020 | 119549 | 109456 | 25 | 60013 | 40012 | 10000 | 10000 | 30010 | 10000 | 10000 | 1079769 | 5735888 | 6125581 | 0 | 120023 | 120047 | 120035 | 111903 | 0 | 3 | 112444 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120047 | 120047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 0 | 0 | 3145 | 1 | 99 | 1 | 1 | 2 | 119665 | 10000 | 40000 | 6 | 6 | 0 | 10000 | 10000 | 40010 | 120036 | 120036 | 120054 | 120092 | 120048 |
60024 | 120047 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9 | 1 | 0 | 0 | 120020 | 119553 | 109443 | 25 | 60010 | 40012 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079769 | 5735888 | 6125581 | 0 | 120011 | 120047 | 120035 | 111903 | 0 | 3 | 112444 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120047 | 120047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 0 | 0 | 1 | 0 | 0 | 0 | 3145 | 1 | 99 | 1 | 3 | 2 | 119710 | 10000 | 40002 | 9 | 6 | 5 | 10000 | 10000 | 40010 | 120052 | 120036 | 120089 | 120065 | 120036 |
60024 | 120047 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 120032 | 119486 | 109471 | 25 | 60013 | 40010 | 10000 | 10000 | 30010 | 10000 | 10000 | 1079809 | 5735888 | 6125581 | 0 | 120023 | 120035 | 120047 | 111915 | 0 | 3 | 112444 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120047 | 120035 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3145 | 1 | 99 | 1 | 1 | 2 | 119665 | 10000 | 40002 | 0 | 0 | 0 | 10000 | 10000 | 40010 | 120048 | 120048 | 120092 | 120060 | 120070 |
60024 | 120047 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 120081 | 119486 | 109473 | 25 | 60013 | 40012 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079809 | 5735293 | 6125581 | 0 | 120011 | 120047 | 120047 | 111915 | 0 | 3 | 112444 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120047 | 120087 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3145 | 1 | 99 | 1 | 1 | 2 | 119650 | 10000 | 40002 | 0 | 0 | 5 | 10000 | 10000 | 40010 | 120036 | 120048 | 120107 | 120090 | 120036 |
60024 | 120035 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 23 | 0 | 0 | 0 | 120038 | 119486 | 109472 | 25 | 60016 | 40014 | 10002 | 10000 | 30010 | 10000 | 10000 | 1079878 | 5736182 | 6125852 | 0 | 120029 | 120053 | 120053 | 111909 | 0 | 3 | 112450 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120053 | 120041 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10003 | 2 | 1 | 10002 | 0 | 1 | 1 | 10000 | 1 | 1 | 1 | 1 | 2 | 0 | 3145 | 1 | 99 | 1 | 1 | 2 | 119671 | 10001 | 40002 | 0 | 6 | 0 | 10000 | 10000 | 40010 | 120054 | 120057 | 120054 | 120086 | 120054 |
Chain cycles: 3
Code:
ldnp s0, s1, [x6] fmov x1, d1 eor x8, x8, x1 eor x8, x8, x1 add x6, x6, x8
mov x0, 1 mov x1, 2 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 9.0051
retire uop (01) | cycle (02) | 03 | 09 | l2 tlb miss data (0b) | 0e | 0f | 1e | 22 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | l1d cache miss ld nonspec (bf) | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ld nt uop (e6) | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
60205 | 120051 | 899 | 3 | 0 | 0 | 0 | 1 | 1 | 120036 | 119495 | 109443 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079126 | 5736084 | 6118285 | 1 | 120027 | 0 | 120051 | 120051 | 111881 | 3 | 112374 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120051 | 120051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 3210 | 1 | 108 | 1 | 1 | 119656 | 10000 | 40002 | 10 | 10 | 0 | 10000 | 10000 | 40100 | 120058 | 120055 | 120036 | 120052 | 120036 |
60204 | 120051 | 899 | 1 | 0 | 1 | 0 | 1 | 1 | 120036 | 119495 | 109443 | 25 | 60103 | 40100 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079126 | 5736084 | 6118285 | 0 | 120011 | 0 | 120051 | 120035 | 111896 | 3 | 112374 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120035 | 120054 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 3210 | 1 | 135 | 1 | 1 | 119646 | 10000 | 40000 | 0 | 10 | 0 | 10000 | 10000 | 40100 | 120052 | 120036 | 120037 | 120052 | 120052 |
60204 | 120051 | 899 | 0 | 0 | 0 | 0 | 1 | 0 | 120036 | 119495 | 109459 | 25 | 60100 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079552 | 5736084 | 6117599 | 0 | 120011 | 0 | 120051 | 120051 | 111896 | 3 | 112417 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120035 | 120035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 1 | 10000 | 0 | 39 | 10000 | 1 | 1 | 0 | 3210 | 1 | 135 | 1 | 1 | 119646 | 10000 | 40000 | 10 | 10 | 9 | 10000 | 10000 | 40100 | 120057 | 120052 | 120052 | 120052 | 120036 |
60204 | 120035 | 899 | 0 | 0 | 0 | 0 | 1 | 1 | 120020 | 119503 | 109459 | 25 | 60103 | 40100 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079552 | 5736084 | 6117599 | 0 | 120027 | 0 | 120035 | 120035 | 111881 | 3 | 112417 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120051 | 120035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 1 | 0 | 0 | 3210 | 1 | 108 | 1 | 1 | 119646 | 10000 | 40000 | 0 | 10 | 0 | 10000 | 10000 | 40100 | 120055 | 120066 | 120053 | 120052 | 120052 |
60204 | 120051 | 899 | 0 | 0 | 0 | 0 | 0 | 1 | 120036 | 119495 | 109459 | 25 | 60103 | 40100 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079552 | 5736230 | 6118285 | 0 | 120011 | 0 | 120051 | 120051 | 111881 | 3 | 112417 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120035 | 120051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10001 | 0 | 10000 | 0 | 0 | 10000 | 0 | 1 | 0 | 3210 | 1 | 108 | 1 | 1 | 119656 | 10000 | 40002 | 10 | 0 | 9 | 10000 | 10000 | 40100 | 120041 | 120052 | 120052 | 120052 | 120036 |
60204 | 120051 | 900 | 0 | 0 | 0 | 0 | 574 | 1 | 120020 | 119518 | 109459 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079552 | 5736084 | 6118285 | 0 | 120011 | 0 | 120035 | 120051 | 111881 | 3 | 112374 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120051 | 120051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 3210 | 1 | 108 | 1 | 1 | 119656 | 10000 | 40002 | 10 | 10 | 0 | 10000 | 10000 | 40100 | 120055 | 120052 | 120052 | 120052 | 120052 |
60204 | 120051 | 899 | 0 | 0 | 0 | 0 | 1 | 0 | 120036 | 119495 | 109443 | 25 | 60103 | 40102 | 10000 | 10000 | 30100 | 10000 | 10000 | 1079126 | 5736084 | 6118285 | 0 | 120011 | 0 | 120035 | 120051 | 111896 | 3 | 112417 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120054 | 120051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 3210 | 1 | 108 | 1 | 1 | 119656 | 10000 | 40000 | 10 | 0 | 9 | 10000 | 10000 | 40100 | 120052 | 120036 | 120052 | 120036 | 120052 |
60204 | 120035 | 899 | 0 | 0 | 0 | 0 | 1 | 1 | 120020 | 119495 | 109459 | 25 | 60103 | 40102 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079552 | 5741635 | 6118285 | 0 | 120011 | 0 | 120035 | 120035 | 111881 | 3 | 112417 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120051 | 120051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 1 | 0 | 0 | 3210 | 1 | 108 | 1 | 1 | 119646 | 10000 | 40002 | 0 | 10 | 0 | 10000 | 10000 | 40100 | 120052 | 120052 | 120052 | 120036 | 120052 |
60204 | 120035 | 899 | 0 | 0 | 0 | 0 | 34 | 0 | 120020 | 119495 | 109459 | 25 | 60103 | 40102 | 10000 | 10000 | 30100 | 10000 | 10000 | 1079552 | 5735293 | 6117599 | 0 | 120027 | 0 | 120035 | 120051 | 111881 | 3 | 112417 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120051 | 120051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 0 | 1 | 0 | 3210 | 1 | 108 | 1 | 1 | 119646 | 10000 | 40002 | 0 | 0 | 0 | 10000 | 10000 | 40100 | 120071 | 120053 | 120052 | 120052 | 120036 |
60204 | 120051 | 899 | 0 | 0 | 0 | 0 | 0 | 1 | 120020 | 119495 | 109446 | 25 | 60100 | 40100 | 10001 | 10000 | 30100 | 10000 | 10000 | 1079552 | 5736084 | 6118285 | 0 | 120011 | 0 | 120035 | 120051 | 111896 | 3 | 112374 | 50100 | 30200 | 20000 | 10000 | 60200 | 10000 | 10000 | 120051 | 120051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 3210 | 1 | 135 | 1 | 1 | 119656 | 10000 | 40000 | 0 | 10 | 0 | 10000 | 10000 | 40100 | 120054 | 120036 | 120052 | 120052 | 120052 |
Result (median cycles for code, minus 3 chain cycles): 9.0051
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 0e | 0f | 18 | 1e | 22 | 23 | 24 | 3a | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | int prf full (71) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ld nt uop (e6) | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
60025 | 120051 | 899 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 120042 | 119491 | 109464 | 25 | 60013 | 40012 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079858 | 5736230 | 6124344 | 0 | 1 | 120027 | 0 | 120051 | 120051 | 111919 | 0 | 3 | 112451 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120051 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 3140 | 5 | 94 | 2 | 2 | 119675 | 10001 | 40002 | 0 | 10 | 9 | 10000 | 10000 | 40010 | 120058 | 120058 | 120058 | 120042 | 120042 |
60024 | 120057 | 899 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 1 | 120026 | 119490 | 109464 | 25 | 60016 | 40014 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079915 | 5736374 | 6126051 | 0 | 0 | 120033 | 0 | 120041 | 120057 | 111925 | 0 | 3 | 112438 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120057 | 120057 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10002 | 3 | 0 | 10003 | 0 | 1 | 10000 | 1 | 1 | 1 | 1 | 0 | 3140 | 2 | 17 | 2 | 2 | 119672 | 10000 | 40000 | 0 | 10 | 9 | 10000 | 10000 | 40010 | 120100 | 120036 | 120052 | 120052 | 120052 |
60024 | 120051 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 120020 | 119484 | 109459 | 25 | 60013 | 40010 | 10000 | 10000 | 30010 | 10000 | 10000 | 1079858 | 5735293 | 6125746 | 0 | 1 | 120030 | 0 | 120051 | 120051 | 111903 | 0 | 3 | 112448 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120035 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 0 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 3140 | 2 | 99 | 3 | 3 | 119669 | 10000 | 40002 | 10 | 10 | 0 | 10000 | 10000 | 40010 | 120036 | 120052 | 120052 | 120052 | 120052 |
60024 | 120054 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 136 | 0 | 0 | 0 | 0 | 120020 | 119484 | 109459 | 25 | 60010 | 40012 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079769 | 5736084 | 6125746 | 0 | 1 | 120027 | 0 | 120035 | 120051 | 111922 | 0 | 3 | 112448 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120051 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 10000 | 0 | 0 | 1 | 0 | 0 | 3140 | 2 | 99 | 3 | 2 | 119650 | 10000 | 40000 | 10 | 10 | 9 | 10000 | 10000 | 40010 | 120036 | 120036 | 120055 | 120052 | 120052 |
60024 | 120051 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 120036 | 119489 | 109443 | 25 | 60013 | 40012 | 10000 | 10000 | 30010 | 10000 | 10000 | 1079858 | 5736084 | 6124344 | 0 | 1 | 120027 | 0 | 120035 | 120051 | 111919 | 0 | 3 | 112451 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120035 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 3140 | 2 | 94 | 3 | 6 | 119651 | 10000 | 40000 | 10 | 10 | 9 | 10000 | 10000 | 40010 | 120052 | 120036 | 120052 | 120052 | 120052 |
60024 | 120051 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 120036 | 119484 | 109459 | 25 | 60013 | 40012 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079858 | 5736084 | 6125746 | 0 | 1 | 120030 | 0 | 120035 | 120051 | 111903 | 0 | 3 | 112437 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120041 | 120041 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 1 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 10000 | 0 | 0 | 1 | 0 | 0 | 3140 | 2 | 94 | 3 | 2 | 119650 | 10000 | 40002 | 10 | 10 | 0 | 10000 | 10000 | 40010 | 120052 | 120036 | 120055 | 120036 | 120052 |
60024 | 120051 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 120036 | 119484 | 109459 | 25 | 60010 | 40012 | 10000 | 10000 | 30010 | 10000 | 10000 | 1079858 | 5736084 | 6125746 | 0 | 1 | 120027 | 0 | 120051 | 120051 | 111919 | 0 | 3 | 112448 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120051 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 0 | 3140 | 2 | 99 | 2 | 2 | 119676 | 10001 | 40004 | 10 | 10 | 9 | 10000 | 10000 | 40010 | 120058 | 120058 | 120058 | 120058 | 120058 |
60024 | 120057 | 899 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 120042 | 119490 | 109449 | 25 | 60016 | 40014 | 10002 | 10000 | 30010 | 10000 | 10000 | 1079915 | 5735593 | 6126051 | 0 | 0 | 120017 | 0 | 120057 | 120057 | 111925 | 0 | 3 | 112438 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120057 | 120057 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10002 | 1 | 0 | 10001 | 2 | 4 | 10000 | 1 | 1 | 0 | 1 | 1 | 3140 | 2 | 99 | 3 | 2 | 119675 | 10001 | 40004 | 13 | 10 | 0 | 10000 | 10000 | 40010 | 120052 | 120055 | 120040 | 120052 | 120052 |
60024 | 120054 | 899 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 120036 | 119484 | 109459 | 25 | 60013 | 40012 | 10001 | 10000 | 30010 | 10000 | 10000 | 1079858 | 5735293 | 6125746 | 0 | 1 | 120011 | 0 | 120051 | 120051 | 111919 | 0 | 3 | 112437 | 50010 | 30020 | 20000 | 10000 | 60020 | 10000 | 10000 | 120051 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 2 | 3810 | 5 | 321 | 16 | 11 | 121549 | 10038 | 40191 | 10 | 10 | 9 | 10000 | 10000 | 40010 | 122390 | 122551 | 122438 | 122436 | 122531 |
60024 | 122551 | 918 | 0 | 2 | 1 | 0 | 1 | 0 | 0 | 1 | 19 | 13 | 1 | 0 | 0 | 1 | 122621 | 120532 | 110204 | 838 | 60321 | 40221 | 10045 | 10056 | 33808 | 11160 | 11383 | 1148153 | 5786450 | 6184780 | 0 | 0 | 122048 | 0 | 122985 | 122696 | 112566 | 0 | 417 | 113507 | 56571 | 34446 | 22242 | 11346 | 67726 | 11393 | 11129 | 124273 | 123141 | 29 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10007 | 2 | 0 | 10000 | 1 | 0 | 10000 | 1 | 0 | 1 | 0 | 16 | 3999 | 2 | 99 | 2 | 2 | 120869 | 10000 | 40002 | 10 | 13 | 9 | 10000 | 10000 | 40010 | 120055 | 120036 | 120052 | 120052 | 120158 |
Count: 8
Code:
ldnp s0, s1, [x6] ldnp s0, s1, [x6] ldnp s0, s1, [x6] ldnp s0, s1, [x6] ldnp s0, s1, [x6] ldnp s0, s1, [x6] ldnp s0, s1, [x6] ldnp s0, s1, [x6]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.3341
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6d | 6e | map stall dispatch (70) | simd prf full (72) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ld nt uop (e6) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160205 | 26724 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 2 | 26707 | 2 | 0 | 12 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1173519 | 0 | 26702 | 26727 | 26722 | 6650 | 0 | 3 | 6685 | 80100 | 200 | 160000 | 200 | 80000 | 26707 | 26856 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 39 | 80039 | 0 | 0 | 39 | 80035 | 6 | 0 | 35 | 0 | 5110 | 2 | 16 | 2 | 2 | 26785 | 80039 | 10 | 6 | 0 | 80000 | 80000 | 100 | 27366 | 26730 | 26721 | 26708 | 26708 |
160204 | 26727 | 200 | 0 | 0 | 1 | 0 | 0 | 0 | 45 | 396 | 1 | 0 | 1 | 26712 | 0 | 0 | 18 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 522 | 1170107 | 0 | 26702 | 26727 | 26707 | 6645 | 0 | 3 | 6680 | 80100 | 200 | 160000 | 200 | 80000 | 26707 | 26723 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 39 | 80035 | 0 | 0 | 35 | 80035 | 6 | 1 | 35 | 43 | 5110 | 2 | 16 | 2 | 2 | 26841 | 80039 | 10 | 6 | 2 | 80000 | 80000 | 100 | 26746 | 26728 | 26723 | 26728 | 26728 |
160204 | 26707 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 41 | 0 | 1 | 0 | 1 | 26692 | 0 | 12 | 12 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1168880 | 1 | 26706 | 26888 | 26890 | 6675 | 0 | 3 | 6685 | 80100 | 200 | 160000 | 200 | 80000 | 26727 | 26722 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 39 | 80039 | 0 | 0 | 39 | 80039 | 0 | 1 | 39 | 43 | 5110 | 2 | 16 | 2 | 2 | 26728 | 80000 | 10 | 10 | 2 | 80000 | 80000 | 100 | 26728 | 26708 | 26728 | 26723 | 26728 |
160204 | 26722 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 1 | 0 | 1 | 26716 | 2 | 12 | 12 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1170107 | 1 | 26697 | 26727 | 26727 | 6650 | 0 | 3 | 6665 | 80100 | 200 | 160000 | 200 | 80000 | 26707 | 26722 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 39 | 80035 | 0 | 0 | 39 | 80035 | 0 | 1 | 0 | 43 | 5110 | 2 | 16 | 2 | 2 | 26730 | 80039 | 10 | 6 | 2 | 80000 | 80000 | 100 | 26728 | 26708 | 26723 | 26708 | 26728 |
160204 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 2 | 26735 | 2 | 12 | 0 | 12 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1175837 | 1 | 26697 | 26727 | 26722 | 6645 | 0 | 3 | 6680 | 80100 | 200 | 160000 | 200 | 80000 | 26722 | 26707 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 80000 | 0 | 0 | 0 | 80000 | 6 | 0 | 35 | 0 | 5110 | 2 | 16 | 2 | 2 | 26730 | 80000 | 10 | 10 | 4 | 80000 | 80000 | 100 | 26742 | 26728 | 26708 | 26728 | 26723 |
160204 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 21 | 0 | 1 | 0 | 1 | 26699 | 2 | 12 | 12 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1174628 | 1 | 26697 | 26722 | 26722 | 6650 | 0 | 3 | 6680 | 80100 | 200 | 160000 | 200 | 80000 | 26707 | 26726 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 39 | 80039 | 0 | 0 | 35 | 80035 | 6 | 1 | 0 | 43 | 5110 | 2 | 16 | 2 | 2 | 26741 | 80039 | 10 | 10 | 4 | 80000 | 80000 | 100 | 26728 | 26708 | 26728 | 26708 | 26723 |
160204 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 1 | 26712 | 2 | 0 | 18 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1176084 | 1 | 26702 | 26727 | 26727 | 6650 | 0 | 3 | 6665 | 80100 | 200 | 160000 | 200 | 80000 | 26722 | 26722 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 39 | 80000 | 0 | 0 | 39 | 80000 | 6 | 1 | 39 | 39 | 5110 | 2 | 16 | 2 | 2 | 26805 | 80035 | 6 | 6 | 2 | 80000 | 80000 | 100 | 26708 | 26728 | 26708 | 26728 | 26728 |
160204 | 26707 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 1 | 0 | 0 | 26719 | 2 | 0 | 12 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80356 | 500 | 1168573 | 1 | 26702 | 26727 | 26707 | 6650 | 0 | 3 | 6665 | 80100 | 200 | 160000 | 200 | 80000 | 26727 | 26722 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 80035 | 0 | 0 | 35 | 80000 | 0 | 0 | 35 | 43 | 5110 | 2 | 16 | 2 | 2 | 26730 | 80039 | 10 | 10 | 2 | 80000 | 80000 | 100 | 26728 | 26728 | 26728 | 26732 | 26745 |
160204 | 26740 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 2 | 26712 | 0 | 0 | 12 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1174628 | 1 | 26702 | 26727 | 26712 | 6650 | 0 | 3 | 6972 | 80100 | 200 | 160000 | 200 | 80000 | 26707 | 26990 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 39 | 80000 | 0 | 0 | 35 | 80000 | 6 | 1 | 35 | 43 | 5110 | 2 | 16 | 2 | 2 | 26823 | 80000 | 0 | 10 | 2 | 80000 | 80000 | 100 | 26708 | 26728 | 26728 | 26728 | 26728 |
160204 | 26707 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 1 | 26707 | 0 | 18 | 18 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 1170107 | 0 | 26682 | 26707 | 26727 | 6630 | 0 | 3 | 6665 | 80100 | 200 | 160000 | 200 | 80000 | 26727 | 26722 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80130 | 39 | 80039 | 0 | 0 | 39 | 80039 | 0 | 1 | 35 | 43 | 5110 | 2 | 16 | 2 | 2 | 26735 | 80000 | 0 | 6 | 4 | 80000 | 80000 | 100 | 26708 | 26728 | 26728 | 26728 | 26728 |
Result (median cycles for code divided by count): 0.3340
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | l2 tlb miss data (0b) | 0e | 0f | 18 | 1e | 22 | 23 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6d | 6e | map stall dispatch (70) | simd prf full (72) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ld nt uop (e6) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160025 | 26723 | 200 | 0 | 0 | 1 | 1 | 0 | 41 | 0 | 0 | 2 | 26712 | 2 | 18 | 0 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1173183 | 1 | 26702 | 26727 | 26707 | 6672 | 0 | 3 | 6702 | 80010 | 20 | 160000 | 20 | 80000 | 26707 | 26776 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 1 | 10 | 80000 | 0 | 0 | 80035 | 0 | 0 | 39 | 80000 | 6 | 0 | 0 | 39 | 0 | 5020 | 8 | 16 | 5 | 7 | 26724 | 80000 | 10 | 0 | 4 | 80000 | 80000 | 10 | 26708 | 26728 | 26723 | 26708 | 26708 |
160024 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 26712 | 2 | 12 | 12 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1170107 | 1 | 26702 | 26727 | 26727 | 6653 | 0 | 3 | 6687 | 80010 | 20 | 160000 | 20 | 80000 | 26727 | 26707 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 80039 | 0 | 0 | 35 | 80039 | 6 | 1 | 35 | 43 | 0 | 5020 | 5 | 16 | 7 | 7 | 26724 | 80000 | 10 | 6 | 4 | 80000 | 80000 | 10 | 26728 | 26708 | 26708 | 26728 | 26728 |
160025 | 26707 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 26692 | 2 | 0 | 0 | 12 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1174628 | 1 | 26682 | 26727 | 26722 | 6653 | 0 | 3 | 6687 | 80010 | 20 | 160000 | 20 | 80000 | 26732 | 26819 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 80039 | 0 | 0 | 35 | 80039 | 6 | 1 | 35 | 0 | 0 | 5020 | 7 | 16 | 7 | 5 | 26725 | 80000 | 10 | 10 | 4 | 80000 | 80000 | 10 | 26728 | 26728 | 26723 | 26723 | 26708 |
160024 | 26722 | 200 | 0 | 0 | 0 | 0 | 0 | 41 | 0 | 0 | 1 | 26712 | 2 | 18 | 18 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1174628 | 1 | 26702 | 26727 | 26707 | 6673 | 0 | 3 | 6707 | 80010 | 20 | 160000 | 20 | 80000 | 26707 | 26789 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 80035 | 0 | 0 | 0 | 80039 | 6 | 1 | 0 | 43 | 0 | 5020 | 7 | 16 | 7 | 7 | 26719 | 80039 | 0 | 10 | 2 | 80000 | 80000 | 10 | 26728 | 26728 | 26723 | 26723 | 26728 |
160024 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 45 | 1 | 0 | 1 | 26712 | 2 | 18 | 0 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1173183 | 1 | 26702 | 26722 | 26707 | 6673 | 0 | 3 | 6707 | 80010 | 20 | 160000 | 20 | 80000 | 26722 | 26722 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 80000 | 0 | 0 | 39 | 80000 | 6 | 1 | 0 | 39 | 0 | 5020 | 7 | 16 | 7 | 5 | 26719 | 80039 | 0 | 0 | 4 | 80000 | 80000 | 10 | 26723 | 26708 | 26708 | 26708 | 26708 |
160024 | 26707 | 200 | 0 | 0 | 1 | 1 | 0 | 45 | 1 | 0 | 2 | 26707 | 0 | 18 | 7 | 12 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1174628 | 1 | 26702 | 26707 | 26707 | 6673 | 0 | 3 | 6711 | 80010 | 20 | 160000 | 20 | 80000 | 26845 | 26807 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 43 | 80035 | 0 | 0 | 35 | 80165 | 6 | 1 | 35 | 0 | 0 | 5020 | 5 | 16 | 5 | 7 | 26724 | 80039 | 6 | 6 | 0 | 80000 | 80000 | 10 | 26728 | 26728 | 26728 | 26708 | 26728 |
160024 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 26692 | 2 | 18 | 12 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1174628 | 1 | 26682 | 26725 | 26755 | 6673 | 0 | 3 | 6687 | 80010 | 20 | 160000 | 20 | 80000 | 26731 | 26878 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 80000 | 0 | 0 | 39 | 80000 | 6 | 1 | 35 | 0 | 0 | 5020 | 7 | 16 | 7 | 7 | 26801 | 80039 | 10 | 6 | 2 | 80000 | 80000 | 10 | 26708 | 26728 | 26708 | 26723 | 26728 |
160024 | 26722 | 200 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 26707 | 0 | 12 | 0 | 12 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1168880 | 1 | 26682 | 26707 | 26707 | 6673 | 0 | 3 | 6707 | 80010 | 20 | 160000 | 20 | 80000 | 26722 | 26722 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 0 | 80000 | 0 | 0 | 0 | 80035 | 6 | 1 | 35 | 39 | 0 | 5020 | 5 | 16 | 5 | 7 | 26704 | 80000 | 6 | 0 | 4 | 80000 | 80000 | 10 | 26708 | 26708 | 26723 | 26723 | 26723 |
160024 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 1 | 26712 | 2 | 12 | 18 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1168880 | 1 | 26702 | 26727 | 26722 | 6668 | 0 | 3 | 6687 | 80010 | 20 | 160000 | 20 | 80000 | 26714 | 26732 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 80035 | 0 | 0 | 0 | 80039 | 6 | 1 | 0 | 39 | 0 | 5020 | 5 | 16 | 7 | 5 | 26725 | 80000 | 0 | 6 | 0 | 80000 | 80000 | 10 | 26728 | 26708 | 26728 | 26708 | 26723 |
160024 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 26757 | 2 | 0 | 18 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1170107 | 1 | 26697 | 26707 | 26707 | 6653 | 0 | 3 | 6691 | 80010 | 20 | 160000 | 20 | 80000 | 26810 | 26722 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 1 | 10 | 80000 | 0 | 39 | 80039 | 0 | 0 | 39 | 80000 | 6 | 1 | 35 | 0 | 0 | 5020 | 7 | 16 | 5 | 7 | 26726 | 80039 | 6 | 6 | 2 | 80000 | 80000 | 10 | 26728 | 26708 | 26728 | 26708 | 26708 |