Firestorm: LDNP (signed offset, D) measurements

Code:

  ldnp d0, d1, [x6, #0x10]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2005	402	2	0	0	0	44	1	0	1	383	2	1	1	16	25	1000	1000	1000	15014	373	398	398	96	3	127	1000	2000	1000	398	394	1	1	1001	1000	1000	0	1000	43	1038	0	42	1038	6	1	39	43	73	1	16	2	2	391	1039	10	10	4	1000	1000	395	395	395	397	395
2004	394	3	0	0	0	45	1	0	1	383	2	0	1	16	25	1000	1000	1000	15284	373	398	398	96	3	131	1000	2000	1000	398	394	1	1	1001	1000	1000	0	1000	43	1039	0	38	1039	6	1	39	43	73	1	16	2	2	398	1038	14	10	7	1000	1000	395	400	399	399	395
2004	397	3	0	0	0	44	1	0	1	383	2	1	1	19	25	1000	1000	1000	15288	373	398	398	96	3	127	1000	2000	1000	398	394	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	40	43	73	1	16	2	2	391	1039	10	10	4	1000	1000	395	395	395	395	397
2004	394	2	0	0	0	176	0	0	1	379	2	1	1	19	25	1000	1000	1000	15288	373	398	398	96	3	131	1000	2000	1000	398	394	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	38	44	73	1	16	2	2	395	1038	14	14	7	1000	1000	399	399	399	399	395
2004	398	3	0	0	0	44	0	0	1	383	2	1	12	16	25	1000	1000	1000	15014	369	398	394	96	3	127	1000	2000	1000	398	394	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	1	16	2	1	391	1039	10	10	4	1000	1000	395	400	400	398	395
2004	394	3	0	0	0	45	0	0	1	379	2	12	12	16	25	1000	1000	1000	15065	372	398	398	96	3	131	1000	2000	1000	394	394	1	1	1001	1000	1000	0	1000	44	1038	0	40	1038	6	1	38	43	73	1	16	2	2	391	1038	14	14	7	1000	1000	399	399	399	399	399
2004	398	3	0	0	0	44	0	0	1	383	0	1	1	16	25	1000	1000	1000	15284	373	398	394	96	3	131	1000	2000	1000	394	394	1	1	1001	1000	1000	0	1000	44	1038	0	38	1038	6	1	38	44	73	1	16	1	1	395	1038	14	14	7	1000	1000	399	399	399	399	399
2004	398	3	0	0	0	45	1	0	1	397	2	1	1	16	25	1000	1000	1000	15053	373	398	398	92	3	131	1000	2000	1000	398	394	1	1	1001	1000	1000	0	1000	44	1038	0	38	1038	6	1	38	44	73	1	16	2	2	391	1038	14	14	4	1000	1000	395	399	399	399	399
2004	394	3	0	0	0	44	1	0	1	380	2	1	12	19	25	1000	1000	1000	15284	373	398	398	96	3	131	1000	2000	1000	398	394	1	1	1001	1000	1000	1	1000	43	1038	0	38	1038	6	1	38	44	73	1	16	2	2	391	1038	14	14	4	1000	1000	399	399	399	399	401
2004	398	3	0	0	1	44	0	0	1	383	0	1	1	16	25	1000	1000	1000	15288	373	398	394	96	3	131	1000	2000	1000	398	394	1	1	1001	1000	1000	0	1000	44	1038	0	38	1038	6	1	38	44	73	1	16	2	2	395	1039	14	10	4	1000	1000	399	399	399	400	399

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldnp d0, d1, [x6, #0x10]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120047	899	1	0	1	1	1	1	27	24	3582	2376	1	0	0	1	123126	121373	110237	1064	60450	40386	10069	10062	34915	11414	11664	1158514	5797203	6191066	1	122183	0	123502	123864	112682	0	647	114125	60338	36997	23942	12367	72416	12233	11859	124096	124103	37	1	50201	100	99	100	40100	10000	10000	0	100	10052	0	1	10000	0	0	0	0	10000	1	1	0	0	0	3262	6	135	7	7	119657	10000	40002	18	6	8	10000	10000	40100	120053	120048	120048	120048	120048
60204	120038	930	1	1	1	0	1	1	0	0	4	0	1	0	0	1	120035	119531	109459	25	60103	40102	10000	10000	30251	10000	10000	1079126	5735293	6118337	1	120011	0	120051	120035	111896	0	3	112374	50100	30200	20000	10000	60200	10000	10000	120056	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	0	0	3214	7	135	7	8	119646	10000	40002	10	10	9	10000	10000	40100	120052	120055	120036	120052	120036
60204	120035	899	1	0	1	0	0	0	0	0	1	0	0	0	1	1	120039	119503	109461	25	60103	40100	10001	10000	30100	10000	10057	1080056	5735725	6118285	1	120031	0	120054	120056	111896	0	3	112407	50100	30200	20000	10000	60200	10000	10000	120035	120054	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	3	10000	1	1	0	0	0	3214	7	135	6	6	119666	10000	40002	0	0	12	10000	10000	40100	120055	120055	120036	120055	120036
60204	120055	900	1	0	1	0	0	0	0	0	1	0	0	0	1	1	120020	119509	109461	25	60100	40102	10001	10000	30100	10000	10000	1079153	5736084	6118285	0	120030	0	120054	120054	111900	0	3	112407	50100	30200	20000	10000	60200	10000	10000	120054	120035	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	0	0	10000	0	1	0	0	0	3212	8	121	7	6	119666	10000	40002	13	13	0	10000	10000	40100	120036	120036	120052	120055	120036
60204	120035	899	1	0	1	0	0	0	0	0	1	0	0	0	0	1	120039	119509	109443	25	60103	40102	10001	10000	30100	10000	10000	1079441	5736230	6117599	0	120030	0	120035	120051	111881	0	3	112407	50100	30200	20000	10000	60200	10000	10000	120051	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	0	10000	1	0	0	0	0	3212	8	135	7	8	119666	10000	40002	10	13	0	10000	10000	40100	120036	120055	120036	120055	120036
60204	120035	900	1	0	1	0	0	0	0	0	1	0	0	0	0	1	120020	119503	109461	25	60103	40102	10001	10000	30100	10000	10000	1079396	5736230	6118285	0	120011	0	120054	120088	111881	0	3	112417	50100	30200	20000	10000	60200	10000	10000	120035	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	0	0	0	3212	8	135	8	7	119646	10000	40002	0	10	0	10000	10000	40100	120052	120052	120036	120060	120055
60204	120035	899	1	0	1	0	0	0	0	0	1	0	0	1	0	1	120020	119503	109461	25	60103	40102	10000	10000	30100	10000	10000	1079396	5736230	6118540	1	120030	0	120054	120035	111896	0	3	112407	50100	30200	20000	10000	60200	10000	10000	120036	120051	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	0	0	3214	7	121	8	7	119666	10000	40002	0	10	12	10000	10000	40100	120036	120055	120036	120055	120036
60204	120054	899	1	0	1	0	0	0	0	0	1	0	0	0	0	1	120020	119503	109443	25	60100	40102	10001	10000	30100	10000	10000	1079396	5735293	6118285	0	120030	0	120051	120054	111882	0	3	112407	50100	30200	20000	10000	60200	10000	10000	120054	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	0	0	3212	7	108	8	6	119646	10000	40002	13	13	12	10000	10000	40100	120055	120055	120036	120036	120055
60204	120054	899	1	0	1	0	0	0	0	0	0	0	0	0	0	2	120020	119503	109459	25	60100	40100	10001	10000	30100	10000	10000	1079552	5736230	6118285	0	120030	0	120035	120054	111900	0	3	112374	50100	30200	20000	10000	60200	10000	10000	120054	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	0	10000	1	0	0	0	0	3214	6	135	8	8	119666	10000	40000	0	0	12	10000	10000	40100	120036	120036	120055	120055	120036
60204	120035	899	1	0	1	0	0	0	0	0	1	0	0	1	0	1	120039	119503	109443	25	60103	40102	10001	10000	30100	10000	10000	1079396	5736230	6117599	0	120030	3	120054	120054	111900	0	3	112407	50100	30200	20000	10000	60200	10000	10000	120054	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	0	0	0	3212	8	121	7	7	119666	10000	40000	13	10	0	10000	10000	40100	120052	120055	120055	120036	120055

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120047	899	0	0	0	0	1	0	0	120020	119483	109443	25	60013	40010	10001	10000	30010	10000	10000	1079809	5736035	6124344	0	120023	120047	120050	111903	3	112447	50010	30020	20000	10000	60020	10000	10000	120068	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3141	0	3	99	3	3	119650	10000	40002	9	0	0	10000	10000	40010	120051	120048	120048	120048	120048
60024	120047	899	0	0	1	0	1	1	0	120035	119489	109443	25	60013	40012	10000	10000	30010	10000	10000	1079809	5735888	6125581	0	120026	120035	120050	111918	3	112437	50010	30020	20000	10000	60020	10000	10000	120097	120079	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	12	10000	0	0	1	0	0	3141	0	3	99	3	3	119668	10000	40002	6	6	8	10000	10000	40010	120048	120048	120051	120048	120036
60024	120101	899	0	0	0	0	1	1	0	120032	119483	109443	25	60013	40012	10001	10000	30010	10000	10000	1079845	5736035	6124344	0	120011	120035	120047	111915	3	112437	50010	30020	20000	10000	60020	10000	10000	120091	120093	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3141	0	3	99	3	3	119650	10000	40002	9	0	5	10000	10000	40010	120036	120036	120051	120036	120036
60024	120047	899	0	0	1	0	1	1	0	120035	119480	109458	25	60013	40012	10000	10000	30010	10000	10000	1079769	5736035	6125581	0	120026	120050	120050	111918	3	112444	50010	30020	20000	10000	60020	10000	10000	120085	120050	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	3	10000	1	0	1	0	0	3141	0	3	99	3	3	119650	10000	40002	0	6	8	10000	10000	40010	120051	120051	120036	120051	120036
60024	120047	899	0	0	0	0	1	1	0	120035	119489	109458	25	60010	40012	10001	10000	30010	10000	10000	1079769	5736035	6125581	0	120026	120035	120035	111903	3	112447	50010	30020	20000	10000	60020	10000	10000	120088	120430	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	3141	0	3	99	3	3	119650	10000	40002	0	6	8	10000	10000	40010	120036	120048	120036	120051	120036
60024	120050	899	0	0	0	0	1	1	0	120035	119489	109455	25	60013	40012	10001	10000	30010	10000	10000	1079769	5736035	6124344	0	120011	120035	120035	111903	3	112437	50010	30020	20000	10000	60020	10000	10000	120072	120056	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	3141	0	3	99	3	3	119665	10000	40000	0	0	8	10000	10000	40010	120051	120036	120051	120048	120048
60024	120035	899	0	0	0	0	10	0	0	120032	119483	109458	25	60010	40012	10001	10000	30010	10000	10000	1079809	5735293	6125581	0	120026	120035	120050	111918	3	112437	50010	30020	20000	10000	60020	10000	10000	120107	120066	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	0	1	10000	1	0	36	10000	1	0	1	0	0	3141	0	3	99	3	3	119668	10000	40002	0	0	8	10000	10000	40010	120036	120036	120052	120139	120270
60024	120035	900	1	0	0	0	1	0	0	120032	119489	109443	25	60013	40012	10001	10000	30010	10000	10000	1079809	5736035	6125581	0	120026	120050	120050	111921	3	112447	50010	30020	20000	10000	60020	10000	10000	120099	120082	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	0	10000	1	0	1	0	0	3141	0	3	99	3	3	119650	10000	40000	9	0	5	10000	10000	40010	120053	120264	120051	120341	120334
60024	120050	902	0	0	0	1	1	0	0	120032	119483	109443	25	60010	40010	10001	10000	30010	10000	10000	1079809	5736035	6124500	0	120013	120050	120050	111915	3	112447	50010	30020	20000	10000	60020	10000	10000	120091	120062	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	1	0	3	10000	1	0	1	0	0	3141	0	3	99	3	3	119668	10000	40000	6	6	5	10000	10000	40010	120436	120819	120052	120051	120051
60024	120431	899	0	0	0	0	1	0	0	120020	119480	109458	25	60010	40012	10001	10000	30010	10000	10000	1079769	5735293	6124344	0	120029	120035	120035	111903	3	112437	50010	30020	20000	10064	60020	10000	10000	120086	120415	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	1	0	3615	10000	0	0	0	0	0	3141	0	3	99	3	3	119668	10000	40000	9	0	0	10000	10000	40010	120036	120051	120051	120051	120048

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldnp d0, d1, [x6, #0x10]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0055

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0e	0f	18	1e	23	3a	3f	43	49	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120061	899	0	2	0	0	0	1	0	0	120040	1	0	119534	109462	25	60106	40104	10001	10000	30100	10000	10000	1079417	5736278	6119081	0	120031	0	120055	120055	111901	3	112420	50100	30200	20000	10213	60200	10000	10000	120043	120055	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	2	10001	0	0	1	10001	1	1	1	3210	1	110	2	1	119666	10001	40004	6	6	0	10000	10000	40100	120056	120056	120045	120056	120044
60204	120043	899	0	0	0	0	0	2	0	0	120028	1	1	119534	109462	25	60103	40104	10002	10000	30100	10000	10000	1079417	5735692	6117652	0	120031	0	120055	120043	111901	3	112419	50100	30200	20000	10000	60200	10000	10000	120055	120055	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	2	10001	0	0	1	10001	1	1	1	3210	2	97	1	2	119669	10001	40004	0	6	5	10000	10000	40100	120056	120056	120044	120044	120056
60204	120043	900	0	0	0	1	0	112	1	0	120040	1	1	119499	109462	25	60106	40102	10002	10000	30100	10000	10000	1079417	5736278	6119081	0	120031	0	120055	120055	111899	3	112420	50100	30200	20000	10000	60200	10000	10000	120043	120043	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	2	10001	0	0	1	10001	1	1	1	3210	1	110	2	1	119666	10001	40004	6	6	5	10000	10000	40100	120044	120056	120056	120056	120056
60204	120055	899	0	0	0	0	0	2	0	0	120040	1	1	119534	109462	25	60106	40102	10002	10000	30100	10000	10000	1079417	5736278	6119081	0	120031	0	120055	120055	111901	3	112454	50100	30200	20000	10000	60200	10000	10000	120043	120055	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10001	1	0	1	10001	0	1	1	3210	1	110	1	2	119666	10001	40004	6	6	5	10000	10000	40100	120056	120044	120056	120056	120056
60204	120055	899	0	0	0	0	0	1	0	0	120028	1	0	119499	109462	25	60103	40102	10002	10000	30100	10000	10000	1079417	5736278	6119081	0	120031	0	120055	120055	111901	3	112419	50100	30200	20000	10000	60200	10000	10000	120055	120055	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10001	0	0	1	10001	1	1	0	3210	2	110	2	1	119666	10001	40002	6	6	5	10000	10000	40100	120056	120056	120056	120044	120056
60204	120055	900	0	0	0	0	0	2	0	0	120040	1	1	119499	109462	25	60106	40104	10002	10000	30100	10000	10000	1079269	5736278	6117652	0	120031	0	120055	120044	111901	3	112419	50100	30200	20000	10000	60200	10000	10216	120045	120078	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10001	0	0	1	10001	0	1	1	3210	1	97	1	1	119666	10001	40002	0	0	0	10000	10000	40100	120056	120056	120044	120056	120044
60204	120055	899	0	0	1	1	0	1	1	0	120028	1	1	119499	109451	25	60103	40104	10002	10000	30100	10000	10000	1079269	5736278	6119081	0	120031	0	120055	120055	111901	3	112419	50100	30200	20000	10000	60200	10000	10000	120055	120055	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	2	10001	0	0	1	10001	1	1	1	3210	2	97	1	2	119650	10001	40004	6	0	5	10000	10000	40100	120056	120056	120056	120056	120056
60204	120055	899	0	0	0	0	0	2	0	0	120028	1	1	119499	109462	25	60106	40104	10002	10000	30100	10000	10000	1079269	5736278	6119081	0	120031	0	120055	120055	111899	3	112419	50100	30200	20000	10000	60200	10000	10000	120043	120055	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	2	10001	0	0	1	10001	1	1	1	3210	1	110	2	2	119650	10001	40004	0	6	5	10000	10000	40100	120056	120056	120056	120044	120056
60204	120055	899	0	0	0	0	0	2	0	0	120040	1	1	119499	109451	25	60106	40104	10002	10000	30100	10000	10000	1079269	5736278	6119081	0	120019	0	120043	120043	111899	3	112419	50100	30200	20000	10000	60200	10000	10000	120055	120043	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	2	10001	0	0	1	10003	0	1	1	3210	2	110	2	2	119666	10001	40004	0	6	5	10000	10000	40100	120056	120044	120056	120056	120056
60204	120055	899	0	0	0	1	0	2	0	0	120028	1	0	119499	109462	25	60106	40104	10002	10000	30100	10000	10000	1079269	5736278	6119081	0	120031	0	120055	120055	111901	3	112419	50100	30200	20000	10000	60200	10000	10000	120043	120043	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10001	0	0	1	10001	1	1	0	3210	1	110	1	2	119666	10001	40004	6	6	5	10000	10000	40100	120056	120056	120044	120056	120056

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120035	899	0	0	1	0	0	1	0	0	0	1	0	0	0	0	120032	119480	109443	25	60013	40012	10009	10000	30010	10000	10000	1079809	5735293	6125581	1	120012	0	120035	120047	111915	3	112437	50010	30020	20000	10000	60020	10000	10000	120437	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	3	0	10000	1	1	0	0	3140	0	2	94	0	1	1	119668	10000	40002	6	6	5	10000	10000	40010	120048	120049	120446	120048	120036
60024	120148	900	0	0	0	0	0	0	0	0	0	1	0	1	0	0	120032	119480	109455	25	60013	40012	10000	10000	30010	10000	10000	1079809	5735293	6124344	1	120023	0	120047	120047	111915	3	112444	50010	30666	20108	10000	60020	10000	10000	120047	120035	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	3140	0	1	94	0	1	1	119650	10000	40000	0	6	8	10000	10000	40010	120051	120036	120048	120048	120036
60024	120050	899	0	0	1	0	0	0	0	0	0	1	0	0	0	0	120032	119483	109458	25	60013	40010	10001	10000	30151	10052	10000	1079845	5736035	6124344	0	120026	0	120050	120050	111915	3	112447	50010	30020	20000	10000	60020	10000	10000	120047	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	3140	0	1	99	0	1	1	119668	10000	40000	6	9	0	10000	10000	40010	120036	120048	120036	120051	120036
60024	120336	899	0	0	0	0	0	0	0	0	4	1	0	1	0	0	120035	119483	109443	25	60013	40010	10001	10000	30010	10000	10000	1079845	5736035	6124344	1	120026	0	120035	120050	111918	3	112447	50253	30020	20000	10000	60020	10000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	3	10005	1	1	0	0	3140	0	1	94	0	1	1	119665	10000	40002	6	6	5	10000	10000	40010	120048	120036	120048	120048	120048
60024	120047	899	2	0	1	0	0	1	1	0	0	1	0	1	0	0	120032	119480	109455	25	60010	40012	10001	10000	30010	10158	10000	1079769	5735293	6124344	1	120023	0	120047	120047	111935	3	112444	50010	30020	20000	10000	60020	10000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	0	10000	0	0	0	0	3140	0	1	99	0	1	1	119665	10000	40002	6	0	5	10000	10000	40010	120048	120441	120036	120048	120036
60024	120047	899	0	0	0	1	0	0	0	4	0	1	0	0	0	0	120020	119480	109443	25	60013	40010	10009	10000	30010	10000	10000	1079809	5735293	6124344	1	120025	0	120047	120047	111915	3	112437	50010	30020	20000	10000	60020	10000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	3140	0	1	99	0	3	1	119665	10000	40000	6	6	5	10000	10000	40010	120036	120048	120036	120048	120036
60024	120047	899	0	0	0	0	0	0	0	0	0	52	352	1	0	0	120032	119480	109455	105	60010	40012	10000	10000	30010	10000	10000	1079809	5735293	6124344	1	120023	0	120047	120047	111915	3	112437	50010	30659	20108	10000	60020	10000	10000	120035	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	3140	0	1	99	0	1	6	119650	10000	40002	6	6	5	10000	10000	40010	120048	120048	120036	120048	120051
60024	120047	899	0	0	0	0	0	0	0	1	0	27	0	0	0	0	120020	119489	109455	25	60010	40012	10000	10000	30010	10000	10000	1084781	5735293	6125581	1	120023	0	120049	120047	111915	3	112444	50010	30020	20000	10000	60020	10000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	3140	0	1	94	0	1	1	119650	10000	40002	6	6	5	10000	10000	40010	120036	120048	120048	120036	120420
60024	120050	899	0	0	0	0	0	0	0	0	0	37	0	1	0	0	120032	119481	109443	25	60010	40012	10001	10000	30010	10000	10000	1079827	5744350	6125737	1	120014	0	120035	120047	111915	3	112444	50010	30020	20000	10000	60020	10000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	0	1	0	0	3140	0	2	127	0	1	1	119665	10000	40002	6	6	0	10000	10000	40010	122253	122314	122421	122448	122408
60024	122333	917	4	1	1	0	0	0	0	25	25	3313	2200	1	0	0	122543	120658	110183	25	60010	40078	10000	10000	30010	10000	10000	1079845	5738245	6124344	0	121999	0	122526	122542	112414	382	113294	56362	34239	22760	11455	68094	11181	11128	122640	122564	27	1	50021	10	9	10	40010	10000	10000	0	10	10043	0	1	10037	1	7	96170	10027	1	1	2	0	4250	0	7	425	0	10	9	122510	10048	40238	9	9	8	10000	10000	40010	122849	122625	120037	120051	120051

Test 4: throughput

Count: 8

Code:

  ldnp d0, d1, [x6, #0x10]
  ldnp d0, d1, [x6, #0x10]
  ldnp d0, d1, [x6, #0x10]
  ldnp d0, d1, [x6, #0x10]
  ldnp d0, d1, [x6, #0x10]
  ldnp d0, d1, [x6, #0x10]
  ldnp d0, d1, [x6, #0x10]
  ldnp d0, d1, [x6, #0x10]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160205	26729	200	1	0	0	0	0	0	44	1	0	1	26712	2	0	0	16	25	80100	100	80000	100	80000	500	1168880	1	26682	26707	26727	6630	0	3	6787	80100	200	160000	200	80000	26727	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80039	0	39	80039	6	1	39	44	0	5110	5	16	3	1	26704	80038	0	10	7	80000	80000	100	26732	26732	26728	26732	26728
160204	26727	200	0	0	0	1	0	0	44	1	0	1	26712	0	1	1	19	25	80100	100	80000	100	80000	500	1174628	1	26706	26707	26731	6630	0	3	6751	80100	200	160000	200	80000	26731	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80000	0	38	80038	6	1	0	44	0	5110	3	16	5	3	26704	80000	0	14	7	80000	80000	100	26708	26708	26732	26732	26732
160204	26731	200	0	0	0	0	0	0	44	0	0	1	26694	0	12	0	0	25	80100	100	80000	100	80000	500	1168627	1	26682	26707	26707	6630	0	3	6797	80100	200	160000	200	80000	26731	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80038	1	41	80000	0	1	0	44	0	5110	3	16	4	2	26724	80000	10	10	4	80000	80000	100	26728	26728	26732	26732	26732
160204	26707	200	0	0	0	0	0	0	45	0	0	1	26716	0	0	0	19	25	80100	100	80000	100	80000	500	1168880	1	26706	26731	26731	6654	0	3	6665	80100	200	160000	200	80000	26731	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80000	0	38	80038	6	1	38	44	0	5110	4	16	4	4	26704	80038	0	0	0	80000	80000	100	26708	26732	26728	26728	26734
160204	26707	200	0	0	0	0	0	0	0	1	0	1	26716	2	1	0	0	25	80100	100	80000	100	80000	500	1169085	1	26706	26707	26731	6654	0	3	6805	80100	200	160000	200	80000	26707	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80038	0	39	80038	6	1	38	44	0	5110	4	16	4	2	26728	80000	14	14	0	80000	80000	100	26732	26732	26708	26728	26732
160204	26731	200	0	0	0	0	0	0	44	0	0	1	26795	0	1	0	0	25	80100	100	80000	100	80000	500	1168880	1	26706	26731	26707	6650	0	3	6800	80100	200	160000	200	80000	26707	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80038	0	39	80039	6	1	38	0	0	5110	5	16	4	2	26728	80000	14	10	7	80000	80000	100	26708	26732	26732	26732	26728
160204	26707	200	0	0	0	0	0	0	44	0	1	0	26692	2	12	12	19	25	80100	100	80000	100	80000	500	1174887	1	26709	26731	26731	6654	0	3	6665	80100	200	160000	200	80000	26727	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80001	43	80038	1	39	80039	6	1	38	44	0	5110	6	16	4	2	26728	80038	14	14	7	80000	80000	100	26728	26728	26728	26728	26711
160204	26753	201	0	1	0	0	0	0	53	0	1	1	26692	0	1	12	0	25	80100	100	80000	100	80000	500	1168880	1	26706	26731	26707	6630	0	3	6740	80100	200	160000	200	80000	26731	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80038	0	38	80038	6	0	39	0	0	5110	5	16	3	1	26728	80038	14	14	4	80000	80000	100	26732	26732	26708	26708	26732
160204	26731	200	0	0	0	0	0	0	44	0	1	0	26716	2	1	0	0	46	80100	100	80000	100	80000	500	1168627	1	26706	26731	26727	6630	0	3	6760	80100	200	160000	200	80000	26707	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80038	0	38	80038	6	1	38	0	0	5110	5	16	4	1	26728	80000	0	14	0	80000	80000	100	26708	26708	26732	26732	26732
160204	26731	200	0	0	0	0	0	0	3	0	0	1	26716	0	12	1	19	25	80100	100	80000	100	80000	500	1174628	1	26706	26727	26707	6630	0	3	6757	80100	200	160000	200	80000	26731	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80038	0	42	80038	6	1	0	0	0	5110	4	16	4	3	26728	80038	0	0	7	80000	80000	100	26708	26708	26708	26708	26708

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160025	26728	200	1	0	0	0	96	0	0	0	0	26692	2	12	0	16	25	80010	10	80000	10	80000	50	1168754	1	26711	26736	26782	6662	0	3	6707	80010	20	160000	20	80000	26727	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	43	80039	0	0	80000	6	0	39	43	0	5020	9	16	6	6	26724	80039	0	10	0	80000	80000	10	26728	26708	26728	26728	26728
160024	26728	200	1	1	0	0	45	0	1	0	0	26712	2	12	12	0	25	80010	10	80000	10	80000	50	1173183	0	26711	26827	26735	6688	0	3	6707	80010	20	160000	20	80000	26727	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	43	80039	0	39	80039	6	1	39	43	0	5020	6	16	6	6	26724	80000	10	0	4	80000	80000	10	26728	26728	26728	26728	26728
160024	26727	200	0	0	0	0	45	0	0	0	0	26692	2	12	0	16	25	80010	10	80000	10	80000	50	1173183	0	26711	26848	26720	6672	0	3	6707	80010	20	160000	20	80000	26727	26707	1	1	80021	10	9	10	10	80000	80000	0	10	80000	43	80039	1	39	80039	6	1	39	43	0	5020	5	16	8	7	26724	80039	0	10	4	80000	80000	10	26728	26708	26728	26728	26729
160024	26896	201	0	0	1	1	177	440	1	0	1	26712	2	12	12	16	25	80010	10	80000	10	80000	50	1168754	1	26711	26707	26727	6728	0	3	6712	80010	20	160756	20	80192	26894	26727	2	1	80021	10	9	10	10	80000	80000	0	10	80000	43	80000	0	1114	80039	6	1	39	43	0	5042	7	16	6	5	26724	80260	10	0	4	80000	80000	10	26728	26728	26728	26728	26728
160024	26727	200	0	0	0	0	45	0	0	0	0	26692	2	12	12	338	98	80140	10	80130	10	80000	50	1174628	0	26711	26739	26837	6673	0	3	6707	80010	20	160000	20	80000	26727	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	80000	0	42	80039	6	1	39	43	0	5020	7	16	7	7	26707	80039	10	10	4	80000	80000	10	26733	26710	26732	26728	26730
160024	26727	200	0	0	0	0	54	0	1	0	1	26719	2	12	12	0	25	80010	10	80000	10	80000	50	1174628	1	26689	26739	26744	6674	0	3	6707	80010	20	160000	20	80000	26727	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	43	80039	0	39	80039	0	1	39	43	0	5020	7	16	5	6	26724	80039	10	10	4	80000	80000	10	26728	26728	26708	26728	26728
160024	26727	200	0	0	0	0	0	0	1	0	1	26692	2	12	0	2	25	80010	10	80000	10	80000	50	1173183	0	26711	26736	26743	6672	0	3	6707	80010	20	160000	20	80000	26727	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	43	80039	0	0	80039	0	1	39	43	0	5020	5	16	7	5	26704	80039	10	10	4	80000	80000	10	26728	26728	26708	26728	26728
160024	26727	200	0	0	0	0	45	0	1	0	1	26692	2	12	12	16	25	80010	10	80000	10	80000	50	1168880	0	26711	26734	26738	6672	0	3	6687	80010	20	160000	20	80000	26727	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	43	80039	0	42	80039	6	0	0	0	0	5020	6	16	6	5	26704	80039	10	10	4	80000	80000	10	26728	26708	26728	26708	26728
160024	26727	200	0	0	4	0	93	0	1	0	1	26692	2	12	12	80	25	80010	10	80000	10	80000	50	1170007	0	26711	26729	26728	6672	0	3	6687	80010	20	160000	20	80000	26727	26707	1	1	80021	10	9	10	10	80000	80000	0	10	80000	43	80039	0	39	80039	6	1	39	43	0	5020	5	16	6	4	26726	80039	10	10	4	80000	80000	10	26708	26728	26728	26728	26728
160024	26707	200	0	0	0	0	45	0	1	0	1	26712	0	0	12	16	25	80010	10	80000	10	80000	50	1168754	1	26873	26728	26797	6682	0	3	6707	80010	20	160000	20	80000	26727	26727	1	1	80021	10	9	10	10	80000	80000	1	10	80000	43	80039	0	39	80039	6	1	39	43	0	5020	7	16	5	7	26724	80039	10	10	4	80000	80000	10	26728	26731	26728	26708	26728

LDNP (signed offset, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations