Firestorm: LDNP (signed offset, Q) measurements

Code:

  ldnp q0, q1, [x6, #0x10]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
2005	722	7	1	0	45	0	0	0	2	693	2	18	18	16	25	2000	2000	2000	29646	703	727	708	405	3	460	2000	2000	2000	708	708	1	1	1001	1000	1000	1	2000	0	39	2000	0	0	0	2000	6	1	35	0	73	1	16	1	1	720	2039	10	6	4	2000	728	729	728	728	729
2004	727	6	0	0	45	0	0	1	2	716	2	12	0	16	25	2000	2000	2000	29574	697	727	730	405	3	460	2000	2000	2000	727	708	1	1	1001	1000	1000	0	2000	0	0	2000	0	0	39	2035	6	1	35	39	73	1	16	1	1	719	2000	0	6	0	2000	709	728	723	728	728
2004	731	6	0	0	45	0	0	1	2	712	2	0	12	16	25	2000	2000	2000	28591	702	708	728	425	3	460	2000	2000	2000	728	722	1	1	1001	1000	1000	0	2000	0	39	2039	0	0	39	2039	6	1	0	39	73	1	16	1	1	724	2039	10	0	4	2000	728	713	729	728	733
2004	727	7	0	0	45	0	0	0	2	707	0	12	0	16	25	2000	2000	2000	29391	698	708	727	425	3	460	2000	2000	2000	722	728	1	1	1001	1000	1000	0	2000	0	39	2039	0	0	0	2000	0	1	35	39	73	1	16	1	1	720	2039	10	6	4	2000	728	728	728	728	729
2004	727	6	0	0	45	0	0	1	1	693	2	0	18	16	25	2000	2000	2000	29574	697	727	708	405	3	460	2000	2000	2000	727	723	1	1	1001	1000	1000	0	2000	0	0	2039	0	0	42	2000	6	1	35	39	73	1	16	1	1	724	2039	10	6	4	2000	709	728	728	709	728
2004	727	7	0	0	41	0	0	0	2	712	2	12	12	16	25	2000	2000	2000	29574	702	722	727	425	3	460	2000	2000	2000	727	722	1	1	1001	1000	1000	0	2000	0	39	2000	0	0	39	2039	6	1	35	0	73	1	16	1	1	719	2000	10	0	0	2000	728	728	728	728	728
2004	728	7	0	0	45	0	0	0	1	712	0	0	12	16	25	2000	2000	2000	29574	697	708	728	405	3	460	2000	2000	2000	728	723	1	1	1001	1000	1000	0	2000	0	39	2039	1	0	39	2000	6	1	39	0	73	1	16	1	1	705	2000	6	6	4	2000	728	709	728	728	729
2004	727	6	0	0	45	0	1	0	2	693	2	0	12	16	25	2000	2000	2000	29624	697	708	722	425	3	460	2000	2000	2000	721	722	1	1	1001	1000	1000	0	2000	0	0	2000	0	0	39	2000	0	0	0	0	73	1	16	1	1	725	2039	0	0	0	2000	709	709	728	729	728
2004	727	6	0	0	0	0	0	0	2	707	0	12	0	16	25	2000	2000	2000	28591	697	727	727	425	3	460	2000	2000	2000	727	727	1	1	1001	1000	1000	0	2000	0	0	2039	0	0	0	2000	6	1	35	0	73	1	16	1	1	719	2039	6	10	4	2000	728	728	709	728	728
2004	727	6	1	0	0	0	0	0	2	717	2	12	0	17	25	2000	2000	2000	29574	697	708	711	425	3	460	2000	2000	2000	730	708	1	1	1001	1000	1000	0	2000	0	39	2035	0	0	39	2000	6	0	39	39	73	1	16	1	1	724	2039	10	10	4	2000	728	729	709	709	723

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldnp q0, q1, [x6, #0x10]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	23	24	3a	3f	43	49	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120061	899	1	0	1	2	0	1	0	2	0	1	0	0	1	120038	0	0	96718	109733	40	70103	40104	10002	20000	30100	10000	20000	10425957	5733532	3465336	0	120017	120053	120053	112141	3	112511	60100	30200	20000	10000	60200	20000	10000	120053	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	20003	3	2	20002	0	0	2	20000	2	2	2	2	0	0	0	3210	2	16	1	1	119826	20002	40004	6	6	5	20000	40100	120054	120054	120054	120042	120054
60204	120053	900	1	0	1	1	1	1	0	4	0	0	1	0	1	120026	0	0	96706	109742	25	70103	40102	10001	20000	30100	10000	20000	10426917	5733532	3465684	0	120017	120053	120053	112141	3	112511	60100	30200	20000	10000	60200	20000	10000	120041	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	20003	3	2	20002	1	0	2	20000	2	2	0	2	0	0	0	3210	1	16	1	1	119814	20002	40002	6	6	0	20000	40100	120042	120054	120054	120054	120054
60204	120056	931	1	0	1	1	0	0	0	4	0	0	1	0	0	120038	0	0	96706	109742	25	70103	40104	10002	20000	30100	10000	20000	10426917	5733532	3465684	0	120029	120053	120053	112129	3	112499	60100	30200	20000	10000	60200	20000	10000	120041	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	20002	3	2	20002	0	1	2	20000	2	2	2	2	1	0	0	3210	1	16	1	1	119814	20002	40004	0	6	5	20000	40100	120042	120054	120054	120054	120054
60204	120053	899	1	0	1	1	0	0	0	4	0	0	1	0	0	120038	0	0	96718	109742	25	70106	40104	10001	20000	30100	10000	20000	10426917	5732956	3465684	0	120017	120053	120053	112141	3	112552	60100	30200	20000	10000	60200	20000	10000	120053	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	20002	2	0	20003	0	1	2	20000	2	2	2	2	1	0	0	3210	1	16	1	1	119826	20002	40004	6	0	0	20000	40100	120054	120042	120042	120054	120054
60204	120053	900	1	0	1	1	0	0	0	4	0	0	1	0	0	120046	2	2	96726	109750	25	70109	40106	10002	20000	30100	10000	20000	10427613	5733916	3465916	0	120017	120041	120053	112141	3	112511	60100	30200	20000	10000	60200	20000	10000	120041	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	20002	4	0	20003	0	1	2	20000	2	2	2	2	1	0	0	3210	1	16	1	1	119814	20002	40002	6	6	0	20000	40100	120054	120054	120042	120042	120054
60204	120053	899	1	0	1	0	0	1	0	4	0	0	1	0	1	120042	0	0	96715	109744	25	70117	40102	10001	20000	30100	10000	20000	10425873	5733532	3465684	0	120017	120041	120041	112129	3	112511	60100	30200	20000	10000	60200	20000	10000	120041	120053	2	1	50201	100	99	100	40100	10000	10000	0	100	20003	3	2	20003	0	1	2	20000	2	2	2	2	0	0	0	3210	1	16	1	1	119814	20002	40004	6	0	5	20000	40100	120054	120042	120054	120054	120054
60204	120041	900	1	0	1	1	1	1	0	28	0	0	0	0	1	120038	0	0	96706	109730	25	70106	40102	10002	20000	30100	10000	20000	10426917	5732956	3465684	0	120029	120041	120053	112129	3	112511	60100	30200	20000	10000	60404	20000	10000	120041	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	20003	2	2	20003	0	1	2	20000	2	2	2	2	1	0	0	3210	1	16	1	1	119826	20002	40004	6	0	0	20000	40100	120054	120054	120042	120054	120042
60204	120053	899	1	0	1	1	0	1	0	2	0	0	1	0	0	120038	0	0	96718	109730	25	70106	40104	10002	20000	30100	10000	20000	10425873	5733532	3465684	0	120017	120053	120053	112129	3	112511	60100	30200	20000	10000	60200	20000	10000	120053	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	20003	2	2	20003	0	1	2	20000	2	2	2	2	2	0	0	3210	1	16	1	1	119826	20002	40004	6	6	5	20000	40100	120054	120042	120054	120054	120042
60204	120053	899	1	0	0	1	1	1	0	4	0	0	0	0	1	120026	0	0	96706	109742	25	70103	40104	10001	20000	30100	10000	20000	10425873	5733532	3465684	0	120025	120049	120061	112167	3	112536	60100	30200	20000	10000	60200	20000	10000	120061	120061	1	1	50201	100	99	100	40100	10000	10000	0	100	20002	2	0	20004	0	1	4	20002	2	2	2	2	2	0	0	3210	1	16	1	1	119826	20002	40004	0	0	0	20000	40100	120058	120054	120042	120042	120058
60204	120053	900	1	0	1	1	1	0	0	4	0	0	0	0	0	120038	0	0	96722	109742	25	70106	40104	10002	20000	30100	10000	20000	10425873	5733724	3465684	0	120017	120057	120057	112141	3	112515	60100	30200	20000	10000	60200	20000	10000	120098	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	20003	2	0	20002	0	0	5	20000	2	2	2	2	3	0	0	3210	1	16	1	1	119814	20002	40004	6	0	0	20000	40100	120058	120042	120042	120058	120059

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120053	899	1	0	1	1	1	0	0	4	0	0	0	2	120038	96647	109730	25	70016	40014	10001	20000	30103	10000	20000	10425896	5733724	3465408	0	120029	0	120057	120041	112168	3	112533	60010	30020	20000	10000	60020	20000	10000	120057	120053	1	1	50021	10	9	10	40010	10000	10000	1	10	20004	3	2	20002	0	0	2	20000	2	2	2	2	0	3140	4	16	4	3	119828	20002	40002	6	6	9	20000	40010	120042	120042	120058	120058	120058
60024	120057	899	1	0	1	0	0	0	0	2	0	0	0	1	120026	96647	109746	25	70028	40012	10001	20000	30010	10000	20000	10424504	5733724	3465408	0	120033	0	120057	120057	112168	3	112524	60010	30020	20000	10000	60020	20000	10000	120057	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	20002	2	2	20003	1	2	2	20000	2	2	0	2	0	3140	3	16	3	4	119832	20002	40002	0	0	0	20000	40010	120058	120042	120054	120058	120042
60024	120041	899	1	0	1	0	0	0	0	4	0	0	0	2	120042	96632	109746	25	70013	40012	10002	20000	30010	10000	20000	10425896	5733724	3465408	0	120033	0	120057	120057	112168	3	112533	60010	30020	20000	10000	60020	20000	10000	120041	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	20003	2	2	20002	0	1	2	20000	2	2	2	2	1	3140	4	16	3	4	119832	20002	40002	10	10	9	20000	40010	120054	120058	120042	120042	120054
60024	120104	899	1	0	1	0	0	0	0	61	0	1	0	2	120026	96647	109746	25	70016	40012	10002	20000	30010	10000	20000	10424504	5733724	3465524	0	120023	0	120041	120057	112168	3	112533	60010	30020	20000	10000	60020	20000	10000	120057	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	20003	5	2	20002	1	0	2	20000	2	2	2	2	0	3140	4	16	4	3	119832	20002	40004	10	6	9	20000	40010	120058	120238	120058	120334	120058
60024	120041	899	1	1	0	0	0	0	0	2	0	0	0	1	120042	96647	109746	25	70016	40012	10001	20000	30010	10000	20000	10424504	5733724	3465408	0	120033	0	120041	120057	112152	3	112537	60010	30020	20000	10000	60020	20000	10000	120057	120053	1	1	50021	10	9	10	40010	10000	10000	1	10	20002	2	2	20003	0	1	5	20000	2	2	2	2	0	3140	4	16	3	4	119828	20002	40004	0	6	9	20000	40010	120042	120044	120054	120054	120054
60024	120053	899	1	0	0	0	0	0	0	2	0	0	0	0	120026	96647	109730	25	70013	40014	10002	20000	30010	10000	20000	10424504	5733820	3465408	0	120033	0	120061	120061	112168	3	112521	60010	30020	20000	10000	60020	20000	10000	120041	120057	1	1	50021	10	9	10	40010	10000	10000	1	10	20003	2	2	20004	0	1	2	20000	2	2	2	2	0	3140	3	16	3	4	119832	20002	40004	0	6	5	20000	40010	120058	120058	120058	120042	120042
60024	120053	899	1	0	0	0	0	0	0	8	0	0	0	2	120042	96647	109746	25	70016	40014	10002	20000	30010	10000	20000	10424504	5732956	3465408	0	120017	0	120041	120041	112168	3	112537	60010	30020	20000	10000	60020	20000	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	20002	4	2	20004	0	0	2	20000	2	2	2	2	0	3140	4	16	4	4	119816	20002	40004	10	6	9	20000	40010	120042	120042	120042	120058	120058
60024	120057	899	1	0	0	0	0	0	0	4	0	0	0	0	120026	96631	109742	25	70013	40014	10002	20000	30010	10000	20000	10425896	5733724	3465060	0	120033	0	120053	120041	112152	3	112537	60010	30020	20000	10000	60020	20000	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	20002	2	2	20004	0	1	2	20000	2	2	0	2	3	3140	4	16	4	4	119816	20002	40029	10	6	9	20000	40010	120054	120058	120058	120132	120054
60024	120053	899	1	0	0	0	0	0	1	4	0	0	0	0	120026	96647	109746	25	70013	40014	10002	20000	30010	10000	20000	10425896	5733532	3465060	0	120033	0	120057	120053	112152	3	112521	60010	30020	20000	10000	60020	20000	10000	120041	120041	1	1	50021	10	9	10	40010	10000	10000	1	10	20002	2	2	20002	2	1	5	20000	0	2	0	2	1	3140	4	16	4	4	119832	20002	40004	10	0	9	20000	40010	120058	120042	120058	120058	120054
60024	120053	899	1	0	0	0	0	0	0	2	0	0	0	0	120042	96647	109746	25	70013	40014	10002	20000	30010	10000	20000	10424504	5733724	3465408	0	120033	0	120057	120041	112168	3	112521	60010	30020	20000	10000	60020	20000	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	20004	3	2	20002	1	2	23	20000	0	2	0	2	1	3140	4	16	3	4	119832	20002	40004	10	0	0	20000	40010	120054	120058	120058	120058	120042

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldnp q0, q1, [x6, #0x10]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0048

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120048	899	1	0	1	1	2	1	0	0	120033	96717	109741	25	70103	40102	10001	20000	30100	10000	20000	10425228	5733484	3465539	1	120011	0	120052	120048	112136	3	112506	60100	30200	20000	10000	60200	20000	10000	120035	120048	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	2	20000	0	0	20000	2	0	0	3210	1	16	1	1	119808	20000	40002	6	0	5	20000	40100	120139	120241	120579	120555	120053
60204	120048	899	0	0	0	0	0	1	0	1	120058	96717	109737	25	70103	40100	10001	20000	30100	10000	20000	10426830	5733292	3465655	0	120024	0	120052	120048	112140	3	112506	60100	30200	20000	10000	60200	20000	10000	120035	120048	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	20000	2	0	0	3210	1	16	1	1	119825	20000	40002	6	0	5	20000	40100	120053	120049	120053	120053	120036
60204	120052	899	1	0	0	0	2	0	0	0	120033	96717	109737	25	70103	40102	10001	20000	30100	10000	20000	10425228	5732666	3465539	0	120028	0	120035	120052	112140	3	112506	60100	30200	20000	10000	60200	20000	10000	120048	120048	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	20000	0	0	0	3210	1	16	1	1	119825	20000	40002	6	6	0	20000	40100	120053	120036	120036	120036	120053
60204	120048	899	1	0	0	0	2	0	0	1	120033	96717	109741	25	70103	40102	10001	20000	30100	10000	20000	10426830	5733484	3465539	0	120011	0	120052	120052	112140	3	112510	60100	30200	20000	10000	60200	20000	10000	120052	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	20000	2	2	0	3210	1	16	1	1	119825	20000	40002	0	10	9	20000	40100	120053	120036	120053	120036	120036
60204	120052	899	0	0	0	0	2	0	0	0	120033	97403	109724	25	70103	40102	10001	20000	30100	10000	20000	10426830	5732666	3465539	1	120028	0	120095	120052	112123	3	112510	60100	30200	20000	10000	60200	20000	10000	120035	120048	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	0	20000	0	0	20000	2	2	0	3210	1	16	1	1	119825	20000	40002	10	6	9	20000	40100	120036	120053	120036	120053	120036
60204	120052	899	0	0	0	0	6	0	0	0	120033	96717	109741	25	70100	40100	10001	20000	30100	10000	20000	10425228	5733484	3465539	0	120028	0	120052	120048	112140	3	112506	60100	30200	20000	10000	60200	20000	10000	120048	120048	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	2	20000	0	0	20000	0	2	0	3210	1	16	1	1	119808	20000	40002	0	6	5	20000	40100	120053	120053	120053	120036	120036
60204	120035	900	0	0	0	0	0	1	0	0	120033	96717	109741	25	70100	40102	10001	20000	30100	10000	20000	10426830	5733484	3465539	0	120028	0	120052	120052	112123	3	112493	60100	30200	20000	10000	60200	20000	10000	120052	120048	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	20000	2	0	0	3210	1	16	1	1	119808	20000	40002	6	10	5	20000	40100	120049	120053	120049	120053	120036
60204	120048	899	0	0	0	0	0	0	0	0	120140	96713	109737	25	70103	40100	10000	20000	30100	10000	20000	10426482	5733484	3465539	0	120024	0	120048	120052	112123	3	112493	60100	30200	20000	10000	60200	20000	10000	120048	120048	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	20000	2	0	0	3210	1	16	1	1	119825	20000	40002	6	6	9	20000	40100	120053	120036	120036	120053	120053
60204	120052	900	0	0	0	0	0	0	0	0	120033	96717	109737	25	70100	40102	10001	20000	30100	10000	20000	10425228	5733484	3465655	0	120028	0	120052	120048	112123	3	112493	60100	30200	20000	10000	60200	20000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	2	20000	0	0	20000	2	2	0	3210	1	16	1	1	119825	20000	40002	6	10	0	20000	40100	120053	120053	120036	120036	120036
60204	120048	900	1	0	0	0	2	0	0	0	120037	96717	109741	25	70103	40102	10001	20000	30194	10000	20000	10426830	5733628	3466775	0	120011	0	120052	120035	112123	3	112510	60100	30200	20000	10000	60200	20000	10032	120035	120056	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	0	20000	0	0	20000	2	2	0	3210	1	16	1	1	119825	20000	40000	6	6	5	20000	40100	120049	120036	120036	120036	120036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0062

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	df	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120058	899	1	0	0	0	0	0	0	4	0	1	0	2	120052	96652	109730	25	70016	40014	10001	20000	30103	10000	20000	10424504	5733772	3465553	0	120038	120041	120058	112173	3	112538	60010	30020	20000	10000	60020	20000	10000	120041	120062	1	1	50021	10	9	10	40010	10000	10000	0	10	20003	2	2	20002	0	0	0	2	20000	2	2	2	2	0	0	0	1	3143	3	1	16	1	1	3	119837	20002	40002	2	10	0	20000	40010	120063	120063	120042	120063	120063
60024	120058	899	1	1	0	0	0	0	0	4	0	1	0	0	120026	96652	109730	25	70013	40014	10002	20000	30010	10000	20000	10426331	5733964	3465553	0	120038	120062	120062	112173	3	112542	60010	30020	20000	10000	60020	20000	10000	120041	120058	1	1	50021	10	9	10	40010	10000	10000	1	10	20002	3	2	20004	0	1	0	2	20000	2	2	2	2	1	0	0	0	3143	3	1	16	1	1	3	119837	20002	40002	0	14	0	20000	40010	120063	120043	120042	120042	120063
60024	120041	899	1	0	1	0	0	0	0	11	0	0	0	1	120026	96648	109730	25	70016	40014	10002	20000	30010	10000	20000	10425983	5733964	3465669	0	120034	120062	120062	112173	3	112542	60010	30020	20000	10000	60020	20000	10000	120062	120041	1	1	50021	10	9	10	40010	10000	10000	1	10	20002	2	0	20002	0	0	1	2	20000	0	2	0	2	0	1	0	0	3143	3	1	16	2	1	3	119833	20002	40002	10	0	13	20000	40010	120063	120042	120043	120042	120042
60024	120062	899	1	0	0	0	0	0	0	4	0	0	0	1	120043	96631	109751	25	70016	40014	10001	20000	30010	10000	20000	10426331	5733964	3465060	0	120038	120062	120062	112152	3	112542	60010	30020	20000	10000	60020	20000	10000	120062	120058	1	1	50021	10	9	10	40010	10000	10000	0	10	20002	2	0	20002	0	0	1	2	20000	2	2	2	2	1	0	0	0	3143	3	1	16	1	1	3	119816	20002	40002	0	14	0	20000	40010	120042	120063	120063	120042	120063
60024	120062	899	1	1	0	0	0	0	0	2	0	1	0	0	120026	96631	109730	25	70013	40012	10001	20000	30010	10000	20000	10424504	5732956	3465553	0	120038	120062	120058	112152	3	112521	60010	30020	20000	10000	60020	20066	10000	120062	120058	1	1	50021	10	9	10	40010	10000	10000	0	10	20003	2	2	20002	0	1	1	2	20000	2	2	0	2	0	0	0	0	3143	3	1	16	1	1	3	119819	20002	40004	14	0	13	20000	40010	120063	120063	120063	120063	120063
60024	120062	899	1	1	0	0	0	0	0	4	0	0	0	0	120026	96652	109730	25	70016	40014	10002	20000	30010	10000	20000	10426331	5733964	3465060	0	120038	120041	120058	112169	3	112542	60010	30020	20000	10000	60020	20000	10000	120062	120041	1	1	50021	10	9	10	40010	10000	10000	1	10	20002	2	2	20003	0	0	1	2	20000	2	2	2	2	1	0	0	0	3143	3	1	16	1	1	3	119816	20002	40002	14	0	13	20000	40010	120063	120042	120059	120042	120062
60024	120041	899	1	0	0	0	0	0	0	2	0	0	0	0	120043	96631	109747	25	70016	40014	10002	20000	30010	10000	20000	10425983	5733964	3465669	0	120038	120041	120058	112152	3	112521	60010	30020	20000	10000	60020	20000	10000	120041	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	20002	3	0	20002	0	0	0	2	20000	2	2	2	2	0	0	0	0	3143	3	1	16	1	1	3	119837	20002	40004	14	14	9	20000	40010	120059	120063	120042	120042	120063
60025	120062	899	1	0	0	0	0	0	0	4	0	0	0	0	120043	96656	109751	25	70013	40014	10001	20000	30010	10000	20000	10426331	5732956	3465553	0	120017	120062	120061	112177	3	112538	60010	30020	20000	10000	60020	20000	10000	120041	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	20003	3	2	20002	0	0	0	2	20002	2	2	2	2	1	0	0	0	3143	3	1	16	1	1	3	119837	20002	40004	14	10	13	20000	40010	120059	120063	120063	120042	120059
60024	120062	899	1	1	1	0	0	25	25	3188	2288	0	0	2	122340	96510	110909	572	70430	40237	10078	20104	32561	10821	21354	10549937	5807096	3508204	0	120938	122429	122502	113288	15	112538	60528	30020	20000	10032	60020	20000	10000	120062	120058	1	1	50021	10	9	10	40010	10000	10000	0	10	20056	5	2	20061	0	1	0	62560	20064	2	2	2	2	0	0	0	0	3846	3	1	233	1	3	3	122370	20090	40309	14	14	9	20000	40010	123596	123898	123407	123768	123531
60024	123680	955	1	0	0	0	1	34	42	4	0	1	0	0	123398	97750	109730	47	70082	40030	10007	20076	30837	10153	20508	10595925	5813758	3512573	0	120041	120251	120432	112245	16	112662	60010	30020	20000	10000	60020	20000	10000	120059	120058	1	1	50021	10	9	10	40010	10000	10000	0	10	20003	2	2	20003	0	3	0	71677	20074	0	2	0	2	0	0	0	0	4074	3	1	16	3	3	3	119841	20002	40002	0	10	13	20000	40010	120059	120059	120059	120059	120066

Test 4: throughput

Count: 8

Code:

  ldnp q0, q1, [x6, #0x10]
  ldnp q0, q1, [x6, #0x10]
  ldnp q0, q1, [x6, #0x10]
  ldnp q0, q1, [x6, #0x10]
  ldnp q0, q1, [x6, #0x10]
  ldnp q0, q1, [x6, #0x10]
  ldnp q0, q1, [x6, #0x10]
  ldnp q0, q1, [x6, #0x10]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6674

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160205	53390	400	0	1	0	0	0	0	41	0	1	0	2	53379	2	0	18	16	25	160100	100	160000	100	160000	500	2333962	0	53349	53374	53389	33317	3	33347	160100	200	160000	200	160000	53389	53389	1	1	80201	100	99	100	100	80000	80000	0	100	160000	39	0	160035	0	0	35	160039	6	1	36	43	0	5110	1	17	1	0	53650	160035	10	6	4	160000	100	53375	53395	53396	53395	53395
160204	53394	400	0	0	0	0	0	0	78	0	1	0	2	53361	2	12	12	22	25	160100	100	160000	100	160000	500	2331836	0	53369	53402	53398	33324	3	33363	160280	200	160000	200	160000	53385	54009	1	1	80201	100	99	100	100	80000	80000	0	100	160000	39	94	160035	0	3	42	160035	6	1	35	43	0	5110	1	16	1	1	53706	160039	6	6	4	160000	100	53375	53375	53396	53392	53403
160204	53394	400	0	0	0	0	0	0	57	0	0	0	1	53374	0	18	18	0	25	160100	100	160000	100	160000	500	2366784	0	53349	53394	53394	33298	3	33483	160100	200	160000	200	160000	53389	53405	1	1	80201	100	99	100	100	80000	80000	1	100	160000	0	0	160301	0	0	48	160039	0	1	39	0	0	5110	1	16	1	1	53386	160039	10	0	0	160000	100	53395	53375	53390	53395	53395
160204	53397	400	0	0	0	0	0	0	45	0	1	0	0	53359	2	12	12	16	25	160100	100	160000	100	160000	500	2333962	0	53369	53394	53389	33312	3	33352	160100	200	160000	200	160000	53394	53389	1	1	80201	100	99	100	100	80000	80000	0	100	160000	39	0	160000	0	0	39	160039	0	1	36	39	0	5110	1	16	1	1	53386	160035	0	6	0	160000	100	53390	53390	53375	53390	53390
160204	53394	400	0	0	1	0	0	0	45	0	0	0	1	53379	2	0	12	16	25	160100	100	160000	100	160000	500	2333262	0	53364	53374	53374	33296	3	33332	160100	200	160000	200	160000	53681	53389	1	1	80201	100	99	100	100	80000	80000	0	100	160000	43	0	160035	0	0	39	160035	6	1	35	43	0	5110	1	16	1	1	53390	160039	10	6	2	160000	100	53375	53395	53375	53390	53397
160204	53394	399	0	0	0	0	0	0	0	0	0	0	2	53379	2	12	0	16	25	160100	100	160000	100	160000	500	2333262	1	53349	53389	53394	33317	3	33352	160100	200	160000	200	160000	53374	53389	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	160000	0	0	35	160039	6	1	39	43	1	5110	1	16	1	1	53386	160000	6	6	0	160000	100	53395	53395	53375	53390	53375
160204	53394	400	0	0	0	0	0	0	45	0	1	0	2	53379	0	12	0	16	25	160100	100	160000	100	160000	500	2333962	0	53349	53394	53374	33317	3	33353	160100	200	160000	200	160000	53389	53374	1	1	80201	100	99	100	100	80000	80000	0	100	160000	39	0	160039	0	0	0	160000	0	1	0	0	0	5110	1	16	1	1	53386	160039	10	0	2	160000	100	53375	53390	53395	53395	53395
160204	53394	400	0	0	0	0	0	0	0	0	0	0	2	53359	2	18	18	16	25	160100	100	160000	100	160000	500	2333962	1	53364	53389	53389	33503	3	33347	160100	200	160000	200	160000	53394	53389	1	1	80201	100	99	100	100	80000	80000	0	100	160000	39	0	160000	0	0	39	160040	6	1	0	39	0	5110	1	16	1	1	53386	160039	10	6	4	160000	100	53375	53390	53395	53395	53395
160204	53394	400	0	0	0	0	0	0	45	0	1	0	1	53359	2	12	12	0	25	160100	100	160000	100	160000	500	2333962	0	53369	53394	53389	33317	3	33332	160100	200	160000	200	160000	53394	53389	1	1	80201	100	99	100	100	80000	80000	0	100	160000	39	0	160000	0	0	39	160039	6	0	35	43	0	5110	1	16	1	1	53694	160039	10	6	4	160000	100	53395	53395	53375	53375	53395
160204	53389	400	0	0	0	0	0	0	45	0	0	0	1	53379	2	18	18	16	25	160100	100	160000	100	160000	500	2332897	0	53349	53394	53374	33312	3	33352	160100	200	160000	200	160000	53389	53374	1	1	80201	100	99	100	100	80000	80000	0	100	160000	39	0	160039	0	0	0	160000	6	0	35	43	0	5110	1	16	1	1	53391	160039	10	10	4	160000	100	53395	53375	53375	53395	53398

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160025	53398	400	1	1	0	1	1	0	0	65	0	1	0	2	53384	2	0	0	16	25	160010	10	160000	10	160000	50	2331086	1	53356	53399	53399	33344	3	33379	160010	20	160000	20	160000	53381	53381	1	1	80021	10	9	10	10	80000	80000	0	10	160020	21	0	160019	1	0	1	59	160038	0	1	57	42	19	1	5020	7	5	16	17	8	53395	160057	0	9	2	160000	10	53400	53400	53382	53382	53382
160024	53399	400	1	0	0	1	0	0	0	65	0	0	0	3	53366	0	18	0	16	25	160010	10	160000	10	160000	50	2338371	0	53356	53388	53399	33326	3	33381	160010	20	160000	20	160000	53416	53399	1	1	80021	10	9	10	10	80000	80000	1	10	160019	21	0	160057	0	1	2	71	160038	0	1	57	42	19	1	5020	6	6	16	17	8	53396	160057	9	9	2	160000	10	53399	53382	53400	53399	53400
160024	53398	400	1	1	1	0	0	0	0	21	0	0	0	2	53383	0	18	18	16	25	160010	10	160000	10	160000	50	2342750	1	53373	53398	53398	33326	3	33379	160010	20	160000	20	160000	53548	53407	1	1	80021	10	9	10	10	80000	80000	0	10	160020	20	42	160019	0	0	0	21	160038	0	0	57	42	19	0	5020	6	16	16	17	17	53395	160057	0	9	0	160000	10	53382	53399	53400	53400	53382
160024	53399	400	1	1	1	0	0	0	0	65	0	0	0	3	53366	2	18	0	16	25	160010	10	160000	10	160000	50	2355367	0	53374	53399	53381	33330	6	33382	160010	20	160000	20	160000	53505	53399	1	1	80021	10	9	10	10	80000	80000	0	10	160019	20	0	160019	0	0	0	59	160038	0	0	57	0	19	1	5020	6	14	16	6	17	53396	160057	9	9	0	160000	10	53400	53399	53400	53382	53400
160024	53381	400	1	0	1	1	0	0	3	21	0	0	0	3	53383	3	18	18	16	25	160010	10	160000	10	160000	50	2328974	0	53373	53398	53398	33326	3	33361	160010	20	160000	20	160000	53398	53396	1	1	80021	10	9	10	10	80000	80000	0	10	160019	19	42	160057	1	0	2	59	160000	6	0	56	42	19	0	5020	6	7	16	17	7	53396	160058	9	9	2	160000	10	53400	53382	53400	53382	53400
160024	53398	400	1	1	1	1	0	0	0	65	0	1	0	3	53384	0	18	0	16	25	160010	10	160000	10	160000	50	2355367	0	53374	53381	53399	33326	3	33378	160010	20	160000	20	160000	53466	53389	1	1	80021	10	9	10	10	80000	80000	0	10	160020	21	42	160057	1	0	1	59	160038	6	1	57	42	19	0	5020	7	16	16	8	17	53378	160057	0	9	0	160000	10	53400	53400	53400	53400	53399
160024	53381	400	1	0	1	0	0	0	0	65	0	1	0	0	53366	2	0	0	0	25	160010	10	160000	10	160000	50	2334497	0	53373	53398	53398	33327	3	33379	160010	20	160000	20	160000	53400	53408	1	1	80021	10	9	10	10	80000	80000	1	10	160020	20	42	160056	1	0	0	60	160038	6	1	19	0	19	0	5020	7	16	16	17	7	53395	160057	9	9	2	160000	10	53399	53400	53386	53404	53399
160024	53399	400	1	1	1	1	0	0	0	21	0	0	0	2	53366	0	18	18	15	25	160010	10	160000	10	160000	50	2349817	0	53373	53381	53399	33326	3	33378	160010	20	160000	20	160000	53482	53408	1	1	80021	10	9	10	10	80000	80000	0	10	160020	21	42	160019	1	0	0	59	160037	6	1	19	0	19	1	5020	7	16	16	8	17	53378	160019	0	9	2	160000	10	53382	53382	53409	53422	53402
160024	53399	400	1	1	1	0	0	0	0	22	0	1	0	1	53383	2	18	18	0	25	160010	10	160000	10	160000	50	2332997	0	53374	53381	53399	33326	3	33361	160010	20	160000	20	160000	53512	53400	1	1	80021	10	9	10	10	80000	80000	0	10	160020	19	0	160057	1	0	0	62	160038	0	1	19	0	19	1	5020	7	7	16	8	17	53378	160019	0	0	0	160000	10	53399	53400	53382	53382	53382
160024	53381	400	1	1	1	0	0	0	0	65	0	0	0	0	53384	2	0	18	15	25	160010	10	160000	10	160000	50	2329020	0	53356	53381	53381	33344	3	33361	160010	20	160000	20	160000	53530	53410	1	1	80021	10	9	10	10	80000	80000	0	10	160019	19	0	160057	2	0	0	21	160000	6	0	57	41	19	1	5020	6	5	16	17	17	53396	160057	9	9	0	160000	10	53399	53400	53399	53383	53382

LDNP (signed offset, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations