Firestorm: LDNP (signed offset, S) measurements

Code:

  ldnp s0, s1, [x6, #0x10]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2005	402	3	1	61	0	0	0	387	17	4	19	20	25	1000	1000	1000	15456	1	377	402	402	80	3	135	1000	2000	1000	402	382	1	1	1001	1000	1000	0	1000	59	1025	55	1025	6	1	55	44	73	1	16	1	1	399	1055	10	10	6	1000	1000	403	403	403	403	384
2004	402	2	0	61	1	0	1	387	18	0	19	20	25	1000	1000	1000	15546	1	357	402	383	100	3	116	1000	2000	1000	402	382	1	1	1001	1000	1000	0	1000	59	1055	55	1055	6	1	55	44	73	1	16	1	1	379	1055	10	10	6	1000	1000	384	403	384	384	403
2004	402	3	1	61	0	0	1	387	17	4	19	3	25	1000	1000	1000	14532	1	377	382	402	100	3	135	1000	2000	1000	402	402	1	1	1001	1000	1000	1	1000	59	1055	55	1055	6	1	55	44	73	1	16	1	1	380	1055	10	10	0	1000	1000	403	384	403	383	403
2004	383	3	1	61	1	0	0	387	17	0	19	20	25	1000	1000	1000	14453	1	377	402	383	83	3	135	1000	2000	1000	402	402	1	1	1001	1000	1000	0	1000	0	1025	55	1055	6	1	55	0	73	1	16	1	1	399	1055	10	0	6	1000	1000	403	384	384	403	403
2004	382	3	0	25	1	0	1	368	17	4	19	3	25	1000	1000	1000	14677	1	377	383	402	80	3	135	1000	2000	1000	402	383	1	1	1001	1000	1000	0	1000	59	1055	55	1025	6	1	55	0	73	1	16	1	1	399	1025	10	10	6	1000	1000	403	403	384	403	403
2004	402	3	0	25	1	0	1	387	17	0	19	3	25	1000	1000	1000	15481	1	377	402	402	80	3	135	1000	2000	1000	402	382	1	1	1001	1000	1000	0	1000	59	1056	25	1055	6	1	55	44	73	1	16	1	1	379	1055	10	10	6	1000	1000	403	383	403	403	403
2004	402	3	0	62	1	0	1	367	17	0	0	2	25	1000	1000	1000	14532	1	360	402	402	100	3	135	1000	2000	1000	402	402	1	1	1001	1000	1000	0	1000	59	1055	55	1055	6	1	25	44	73	1	16	1	1	399	1055	10	10	6	1000	1000	403	403	403	403	403
2004	402	3	0	61	1	0	1	387	17	4	19	20	25	1000	1000	1000	15456	1	377	402	383	100	3	116	1000	2000	1000	402	402	1	1	1001	1000	1000	0	1000	59	1025	55	1056	6	0	55	0	73	1	16	1	1	399	1055	0	10	6	1000	1000	403	403	403	403	383
2004	402	3	0	61	1	0	1	368	17	4	19	20	25	1000	1000	1000	14453	1	377	402	402	100	3	135	1000	2000	1000	382	383	1	1	1001	1000	1000	0	1000	59	1055	55	1055	6	1	55	44	73	1	16	1	1	399	1055	10	0	6	1000	1000	403	403	403	384	403
2004	402	3	0	61	0	0	1	387	17	4	0	20	25	1000	1000	1000	15499	1	377	383	402	100	3	135	1000	2000	1000	402	383	1	1	1001	1000	1000	0	1000	59	1055	55	1055	6	1	55	44	73	1	16	1	1	380	1055	10	10	6	1000	1000	384	403	403	403	403

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldnp s0, s1, [x6, #0x10]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120047	899	0	0	0	1	1	0	0	1	0	1	0	0	120020	119494	109458	25	60114	40100	10000	10000	30100	10000	10000	1079539	5736035	6117882	1	120023	0	120050	120050	111881	3	112374	50100	30200	20000	10000	60200	10000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	1	0	12	10001	1	0	0	0	3210	1	108	1	1	119646	10000	40002	6	6	8	10000	10000	40100	120051	120048	120048	120048	120051
60204	120047	899	0	0	0	0	0	0	0	0	0	0	0	0	120020	119494	109458	25	60100	40102	10001	10000	30100	10000	10000	1079539	5735293	6117882	0	120023	0	120035	120050	111881	3	112416	50100	30200	20000	10000	60200	10000	10000	120047	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	0	0	0	3210	1	108	1	1	119655	10000	40000	9	6	8	10000	10000	40100	120036	120051	120036	120051	120051
60204	120050	899	0	0	0	0	0	0	0	0	0	0	0	0	120035	119494	109443	25	60103	40102	10000	10000	30100	10000	10000	1079539	5736035	6117599	0	120026	0	120050	120035	111895	3	112374	50344	30200	20000	10000	60200	10000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	0	3210	1	108	1	1	119646	10000	40000	6	0	8	10000	10000	40100	120048	120048	120051	120051	120048
60204	120050	899	0	0	0	1	1	0	0	0	0	1	0	0	120020	119503	109458	25	60100	40102	10000	10000	30100	10000	10000	1079539	5735293	6117599	0	120011	0	120035	120035	111903	3	112421	50100	30200	20000	10000	60200	10000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	0	3210	1	100	1	1	119646	10000	40000	6	0	8	10000	10000	40100	120036	120048	120036	120051	120051
60204	120035	899	0	0	0	1	0	0	0	6	0	1	0	0	120032	119503	109443	25	60103	40100	10001	10000	30100	10000	10000	1079348	5735888	6117882	0	120011	0	120050	120035	111895	3	112421	50100	30200	20000	10000	60200	10000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10001	1	1	0	0	3210	1	108	1	1	119655	10000	40002	9	0	8	10000	10000	40100	120051	120036	120048	120036	120051
60204	120035	899	0	0	0	0	0	0	0	1	0	0	0	0	120020	119494	109458	25	60103	40102	10001	10000	30100	10000	10000	1079566	5735293	6117599	0	120026	0	120050	120047	111881	3	112421	50100	30200	20000	10000	60200	10000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	0	0	0	3210	1	135	1	1	119646	10000	40000	9	6	0	10000	10000	40100	120051	120036	120051	120051	120051
60204	120035	899	0	0	0	0	0	0	0	1	0	0	0	0	120035	119494	109458	25	60103	40100	10001	10000	30100	10000	10000	1079539	5735293	6117882	0	120011	0	120050	120035	111895	3	112416	50100	30200	20000	10000	60200	10000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	0	1	0	0	3210	1	108	0	1	119657	10000	40000	9	6	0	10000	10000	40100	120036	120036	120036	120048	120051
60204	120035	899	0	0	0	0	0	0	0	1	0	0	0	0	120035	119494	109443	25	60103	40102	10001	10000	30100	10000	10000	1079539	5736035	6117882	0	120026	0	120035	120047	111895	3	112421	50100	30200	20000	10000	60200	10000	10053	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	0	3210	1	135	1	1	119655	10000	40002	0	6	8	10000	10000	40100	120048	120036	120048	120036	120051
60204	120035	899	0	0	0	0	0	0	0	0	0	1	0	0	120035	119494	109458	25	60103	40102	10001	10000	30100	10000	10000	1079126	5736035	6117882	1	120011	0	120035	120050	111895	3	112416	50100	30200	20000	10000	60200	10000	10064	120083	120120	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	0	0	0	10000	1	1	0	0	3210	1	108	1	1	119655	10000	40000	9	6	8	10000	10000	40100	120036	120036	120051	120051	120036
60204	120050	899	0	0	0	1	0	0	0	1	0	1	0	0	120035	119494	109458	25	60103	40100	10001	10000	30100	10000	10000	1079539	5736035	6117599	1	120011	0	120050	120050	111903	3	112421	50100	30200	20126	10000	60200	10000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	1	10000	0	0	0	10000	1	1	0	0	3210	1	100	1	1	119655	10000	40002	0	0	8	10000	10000	40100	120051	120051	120048	120051	120051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120057	899	1	1	0	0	0	0	0	0	2	0	1	0	1	120042	119490	109464	25	60016	40014	10001	10000	30010	10000	10000	1079870	5736518	6126051	0	0	120036	120057	120041	111928	3	112454	50010	30020	20000	10000	60020	10000	10063	120057	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	3	1	10002	0	0	1	1	10000	1	1	1	1	1	0	3140	18	99	0	6	13	119675	10003	40002	10	10	9	10000	10000	40010	120061	120050	120058	120058	120042
60024	120057	900	1	0	0	1	0	0	0	0	2	0	1	0	0	120026	119484	109449	25	60016	40014	10002	10000	30010	10000	10000	1079870	5736518	6123500	0	1	120033	120057	120057	111925	3	112454	50010	30020	20000	10065	60020	10000	10000	120057	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10003	0	0	1	1	10000	1	1	1	1	0	0	3140	17	99	0	17	6	119675	10001	40002	10	10	9	10000	10000	40010	120061	120058	120042	120058	120058
60024	120041	899	1	0	0	1	0	0	0	0	2	0	0	0	1	120042	119484	109464	25	60016	40012	10002	10000	30010	10000	10000	1079915	5736374	6126051	0	0	120036	120057	120041	111925	3	112454	50010	30020	20000	10000	60020	10000	10000	120041	120057	1	1	50021	10	9	10	40010	10000	10000	1	10	10003	2	1	10003	0	1	1	1	10000	1	1	1	1	2	0	3140	13	99	0	17	17	119675	10001	40004	10	10	0	10000	10000	40010	120042	120058	120042	120058	120058
60024	120057	899	1	0	0	1	0	1	0	0	14	0	0	0	0	120026	119490	109449	25	60013	40014	10002	10000	30010	10000	10000	1079870	5736374	6126051	0	1	120033	120057	120057	111925	3	112438	50010	30020	20000	10108	60344	10000	10000	120057	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10002	0	0	1	4	10000	1	1	0	1	1	0	3140	18	99	7	15	6	119675	10001	40004	10	0	9	10000	10000	40010	120058	120058	120058	120058	120058
60024	120057	899	1	1	0	1	0	0	0	0	1	0	1	0	0	120042	119484	109464	25	60016	40014	10002	10000	30010	10000	10000	1079915	5735593	6126051	0	1	120033	120057	120057	111928	3	112454	50010	30020	20000	10000	60020	10000	10000	120041	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	3	1	10001	0	0	1	1	10000	1	1	1	1	0	0	3140	6	99	0	7	17	119675	10001	40002	10	10	9	10000	10000	40010	120058	120058	120042	120042	120058
60024	120041	899	1	1	0	1	0	0	0	0	2	0	0	0	0	120042	119490	109467	25	60013	40014	10002	10000	30010	10000	10000	1079870	5736374	6126051	0	1	120033	120057	120060	111925	3	112454	50010	30020	20000	10000	60020	10000	10000	120057	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	0	10001	0	0	2	4	10000	1	1	0	1	1	0	3140	17	99	0	7	17	119675	10001	40004	0	10	9	10000	10000	40010	120058	120042	120058	120058	120045
60024	120057	899	1	1	0	1	0	0	0	0	1	0	1	0	0	120026	119491	109464	25	60016	40014	10002	10000	30010	10000	10000	1079915	5736374	6126051	0	1	120036	120041	120057	111928	3	112438	50010	30020	20000	10000	60020	10000	10000	120060	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	3	1	10002	0	0	0	1	10000	0	1	1	1	2	0	3176	14	99	0	7	15	119675	10001	40004	10	10	0	10000	10000	40010	120058	120042	120059	120061	120058
60024	120060	900	1	1	0	0	0	0	0	0	2	0	1	0	0	120042	119490	109464	25	60016	40012	10002	10000	30010	10000	10000	1079870	5736374	6123605	0	1	120033	120057	120057	111925	3	112454	50010	30020	20000	10000	60020	10000	10000	120041	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	3	1	10002	0	0	1	1	10000	0	1	0	1	0	0	3140	17	99	0	17	17	119659	10001	40004	10	0	9	10000	10000	40010	120042	120058	120042	120061	120058
60024	120057	900	1	1	0	1	0	0	0	0	2	0	1	0	0	120042	119490	109464	86	60028	40014	10004	10000	30152	10210	10000	1091720	5748386	6126051	0	1	120039	120057	120057	111909	3	112454	50010	30180	20000	10000	60340	10000	10000	120057	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10001	0	0	1	1	10000	0	1	1	1	1	0	3304	17	99	0	18	7	119675	10001	40004	10	10	9	10000	10000	40010	120802	120564	120632	120584	120058
60024	120057	900	1	1	0	0	0	0	0	0	2	0	1	0	0	120042	119490	109464	25	60016	40012	10002	10000	30010	10000	10000	1079870	5736374	6126051	0	1	120020	120041	120057	111925	3	112457	50010	30020	20000	10000	60020	10000	10000	120041	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	0	10002	0	0	0	1	10000	1	1	1	1	0	0	3140	6	99	0	17	5	119675	10001	40004	10	10	12	10000	10000	40010	120058	120042	120058	120042	120042

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldnp s0, s1, [x6, #0x10]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0056

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120053	900	1	0	0	1	4	1	1	0	0	2	0	1	0	0	120142	119511	109453	25	60106	40104	10003	10000	30100	10061	10000	1079414	5738870	6119380	0	120100	120158	120143	111952	3	112417	50100	30200	20000	10000	60200	10000	10000	120056	120056	1	1	50201	100	99	100	40100	10000	10000	1	100	10001	1	1	10001	0	0	1	10000	1	0	0	0	0	3211	5	110	5	5	119665	10001	40004	9	6	8	10000	10000	40100	120057	120044	120045	120044	120057
60204	120058	899	1	0	1	1	0	1	0	0	4	2	0	1	0	1	120040	119511	109450	55	60115	40143	10004	10004	30100	10106	10050	1086947	5750029	6122456	0	120017	120041	120056	111897	3	112409	50100	30200	20000	10000	60200	10000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	1	100	10001	2	0	10003	0	2	4	10000	1	1	1	1	0	3210	5	121	5	5	119668	10001	40002	9	6	8	10000	10000	40100	120042	120054	120056	120057	120441
60204	120056	899	1	0	1	0	0	1	0	1	0	58	352	1	0	1	120418	119511	109466	25	60106	40102	10002	10000	30100	10000	10000	1079414	5735737	6121953	0	120017	120053	120054	111899	3	112415	50100	30200	20000	10000	60200	10000	10000	120053	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	0	10001	0	1	1	10000	1	1	1	1	0	3210	4	121	5	5	119651	10001	40004	6	6	8	10000	10000	40100	120057	120057	120054	120042	120042
60204	120041	899	1	0	0	1	0	1	0	0	0	7	0	1	0	1	120041	119497	109463	25	60103	40104	10002	10000	30100	10000	10000	1079368	5736182	6121192	0	120017	120057	120446	111902	3	112417	50100	30200	20000	10000	60200	10000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	1	100	10002	2	0	10002	1	0	1	10000	1	1	1	1	1	3210	4	121	5	5	119662	10001	40004	0	0	0	10000	10000	40100	120057	120042	120058	120057	120057
60204	120041	899	1	0	1	1	0	1	1	1	0	2	0	1	0	0	120038	119530	109463	25	60103	40104	10002	10000	30100	10000	10000	1079368	5736326	6120404	0	120029	120056	120041	111902	3	112415	50100	30200	20000	10000	60200	10000	10000	120041	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	0	10001	0	0	1	10000	1	1	0	1	1	3210	5	121	5	5	119668	10001	40002	0	0	8	10000	10000	40100	120057	120057	120054	120042	120042
60205	120056	900	1	0	0	1	0	0	1	0	0	2	0	0	0	0	120041	119497	109461	25	60106	40126	10001	10000	30100	10000	10000	1079414	5736182	6120050	0	120017	120056	120053	111897	3	112417	50100	30200	20000	10000	60200	10000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	2	1	10001	0	0	4	10000	0	1	1	1	1	3210	5	100	4	4	119668	10001	40004	0	6	5	10000	10000	40100	120057	120057	120057	120057	120222
60204	120059	899	1	0	0	1	0	1	0	0	0	5	0	1	0	0	120026	119511	109463	25	60106	40102	10001	10000	30100	10000	10000	1079368	5739686	6119422	0	120029	120056	120056	111897	3	112415	50100	30200	20000	10000	60200	10000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10001	0	2	1	10000	0	1	1	1	1	3210	5	110	5	5	119651	10001	40002	0	0	5	10000	10000	40100	120042	120057	120042	120057	120042
60204	120056	900	1	1	1	0	0	1	1	0	0	2	0	0	0	0	120038	119511	109463	25	60106	40104	10002	10000	30100	10000	10000	1079368	5739254	6119432	0	120032	120056	120056	111897	3	112415	50100	30200	20000	10000	60200	10000	10000	120041	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	0	10001	0	0	1	10000	1	1	0	1	1	3210	5	121	5	5	119651	10001	40002	9	6	0	10000	10000	40100	120057	120102	120057	120042	120057
60204	120056	899	1	0	1	0	0	1	0	1	0	2	0	0	1	0	120026	119530	109449	25	60106	40104	10002	10000	30100	10000	10000	1079414	5736182	6120561	0	120032	120041	120053	111899	3	112417	50100	30200	20000	10000	60200	10000	10000	120041	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10001	0	0	1	10000	1	1	1	1	2	3210	5	100	5	4	119668	10001	40004	9	6	8	10000	10000	40100	120057	120042	120042	120057	120042
60204	120062	900	1	0	1	0	1	1	1	0	0	413	0	0	1	0	120041	119511	109463	25	60106	40104	10002	10000	30100	10000	10000	1079414	5736182	6120824	0	120029	120056	120053	111902	3	112409	50100	30200	20000	10000	60200	10000	10000	120041	120106	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	1	0	3210	4	100	5	5	119668	10001	40004	6	0	8	10000	10000	40100	120058	120054	120054	120057	120042

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	0e	0f	18	19	1e	1f	22	23	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cd	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120051	899	0	1	1	0	0	0	1	0	0	0	0	120020	119489	109443	25	60013	40012	10000	10000	30010	10000	10000	1079888	5739012	6126518	0	120030	120054	120054	111922	3	112437	50010	30020	20000	10000	60020	10000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	4	0	27	10000	1	1	0	0	0	3140	0	5	99	4	3	119672	10000	40002	13	10	9	10000	10000	40010	120036	120055	120057	120061	120055
60024	120054	899	0	0	0	0	0	0	1	0	0	0	0	120020	119487	109461	25	60013	40012	10000	10000	30010	10000	10000	1079888	5736084	6128433	0	120030	120054	120054	111922	3	112448	50010	30020	20000	10000	60020	10000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	1	10000	0	0	0	10000	0	0	0	0	1	3140	0	4	99	3	4	119672	10000	40006	13	0	12	10000	10000	40010	120052	120052	120055	120055	120055
60024	120054	899	0	0	1	0	0	0	0	0	1	0	0	120039	119487	109443	25	60013	40010	10000	10000	30010	10000	10055	1079858	5741744	6127186	0	120030	120110	120084	111903	3	112437	50010	30020	20000	10000	60020	10063	10000	120062	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	243	10000	1	1	0	0	0	3140	0	4	94	4	3	119650	10000	40002	13	0	12	10000	10000	40010	120055	120036	120055	120055	120055
60024	120078	899	0	0	0	0	0	0	0	0	0	0	0	120020	119487	109461	25	60013	40010	10001	10000	30010	10000	10000	1079885	5736084	6125746	0	120011	120054	120054	111903	3	112437	50010	30020	20000	10000	60020	10000	10000	120035	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	204	10000	1	0	0	0	0	3140	0	5	99	4	3	119673	10000	40002	10	13	12	10000	10000	40010	120055	120055	120055	120055	120052
60024	120082	899	0	0	0	0	0	0	1	0	1	0	0	120020	119489	109443	25	60013	40012	10001	10000	30010	10000	10000	1079894	5735293	6125746	0	120027	120054	120054	111922	3	112437	50010	30020	20000	10000	60020	10000	10000	120054	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	237	10000	0	1	0	0	0	3140	0	4	99	3	5	119672	10000	40002	13	13	9	10000	10000	40010	120036	120036	120055	120036	120055
60024	120120	902	0	0	0	0	0	0	0	0	0	0	0	120039	119487	109443	25	60013	40012	10001	10000	30010	10000	10000	1079858	5736230	6124344	0	120011	120054	120054	111903	3	112451	50010	30020	20000	10000	60020	10000	10000	120054	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	207	10000	1	1	0	0	0	3140	0	5	94	4	3	119672	10000	40000	13	10	0	10000	10000	40010	120056	120052	120052	120055	120055
60024	120125	899	0	0	0	0	0	0	4	0	0	0	0	120036	119489	109461	25	60013	40012	10001	10000	30010	10000	10000	1079897	5735293	6125746	0	120027	120054	120051	111903	3	112437	50010	30020	20000	10000	60020	10000	10000	120054	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	255	10000	1	1	0	0	0	3140	0	3	99	5	4	119672	10000	40000	13	10	9	10000	10000	40010	120055	120055	120036	120055	120036
60024	120074	900	0	0	0	0	24	24	3318	2200	0	0	0	122400	120578	110148	792	60286	40189	10048	10052	33540	11419	11286	1141461	5791135	6180425	0	120401	122469	122426	112469	365	112586	50010	30020	20000	10000	60020	10000	10000	120054	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10028	0	1	10036	1	2	91911	10036	0	1	0	0	0	3943	0	6	340	5	6	121880	10040	40239	0	13	12	10000	10000	40010	123798	123244	123959	123335	123257
60024	123774	956	2	1	0	0	0	1	4	0	0	0	0	120039	119484	109459	25	60013	40012	10003	10000	30010	10000	10000	1079769	5745817	6179502	0	121905	121693	120054	111922	3	112451	50010	34073	22888	11554	72256	11922	11559	123026	122612	32	1	50021	10	9	10	40010	10000	10000	1	10	10046	2	0	10040	0	0	89807	10000	1	1	0	0	0	3363	0	7	345	4	8	122072	10040	40002	17	13	12	10000	10000	40010	120801	120058	120143	120061	120036
60024	120047	930	0	0	1	0	0	0	1	0	0	0	0	120039	119489	109443	25	60013	40012	10000	10000	30010	10000	10000	1079769	5736230	6125746	0	120030	120054	120054	111903	3	112451	50010	30020	20124	10000	60020	10000	10000	120055	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	168	10000	1	1	0	0	0	3140	0	4	99	4	3	119672	10000	40000	10	0	9	10000	10000	40010	120036	120036	120055	120055	120055

Test 4: throughput

Count: 8

Code:

  ldnp s0, s1, [x6, #0x10]
  ldnp s0, s1, [x6, #0x10]
  ldnp s0, s1, [x6, #0x10]
  ldnp s0, s1, [x6, #0x10]
  ldnp s0, s1, [x6, #0x10]
  ldnp s0, s1, [x6, #0x10]
  ldnp s0, s1, [x6, #0x10]
  ldnp s0, s1, [x6, #0x10]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	18	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160205	26734	201	1	1	0	0	0	45	1	0	1	26733	0	1	12	0	25	80100	100	80000	100	80000	500	1168140	0	26685	26707	26707	6650	3	6685	80100	200	160000	200	80000	26731	26727	1	1	80201	100	99	100	100	80000	80000	1	100	80000	43	80000	0	39	80039	6	1	0	44	5110	1	16	1	1	26704	80039	10	10	0	80000	80000	100	26876	26814	26741	26734	26870
160204	26731	200	0	0	0	2	2	45	0	0	1	26712	2	12	1	80	25	80100	100	80000	100	80178	500	1176344	1	26702	26731	26707	6650	3	6689	80100	200	160000	200	80000	26727	26727	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	80038	1	38	80039	6	1	39	43	5110	1	16	1	1	26728	80000	14	14	7	80000	80000	100	26720	26844	26718	26752	26737
160204	26731	200	0	0	0	0	0	0	0	0	0	26692	0	0	1	20	25	80100	100	80000	100	80000	500	1174628	1	26682	26731	26731	6630	3	6665	80100	200	160000	200	80000	26727	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	44	80038	0	38	80038	6	1	0	44	5110	1	16	1	1	26704	80038	0	0	7	80000	80000	100	26868	26804	26877	26744	26732
160204	26731	200	0	0	0	0	0	0	0	0	0	26712	2	1	1	27	25	80100	100	80000	100	80000	500	1174887	1	26706	26707	26731	6654	3	6689	80100	200	160000	200	80000	26707	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80038	0	0	80038	0	0	39	44	5110	1	16	1	1	26728	80039	10	14	0	80000	80000	100	26878	26817	26792	26741	26732
160204	26727	201	0	0	0	0	0	44	0	0	1	26716	2	1	0	4	25	80100	100	80000	100	80000	500	1168754	1	26706	26731	26727	6654	3	6685	80100	200	160000	200	80000	26727	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80000	0	38	80038	6	0	0	43	5110	1	16	1	1	26724	80038	14	14	7	80000	80000	100	26782	26859	26713	26736	26732
160204	26707	200	0	0	0	0	0	44	1	0	1	26716	2	12	12	3	25	80100	100	80000	100	80000	500	1168880	1	26706	26731	26707	6654	3	6689	80100	200	160000	200	80000	26731	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80038	0	38	80038	0	1	38	44	5110	1	16	1	1	26728	80038	0	14	7	80000	80000	100	26870	26796	26721	27373	26749
160204	26707	200	0	0	0	0	0	44	0	0	0	26716	2	1	1	31	25	80100	100	80000	100	80000	500	1174887	0	26706	26731	26731	6654	3	6689	80100	200	160000	200	80000	26731	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80038	0	38	80000	6	1	38	43	5110	1	16	1	1	26728	80000	14	10	4	80000	80000	100	26885	26782	26833	26717	26732
160204	26731	200	0	0	0	0	0	44	0	0	1	26712	0	1	1	36	25	80100	100	80000	100	80000	500	1174887	0	26682	26731	26707	6654	3	6689	80100	200	160000	200	80000	26707	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80038	0	38	80000	0	0	39	44	5110	1	16	1	1	26728	80038	14	14	0	80000	80000	100	26888	26755	26743	26708	26740
160204	26732	200	0	0	0	0	0	44	1	0	0	26719	2	12	1	5	25	80100	100	80000	100	80000	500	1169085	0	26702	26731	26731	6630	3	6665	80100	200	160000	200	80000	26731	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80000	0	41	80038	6	1	39	43	5110	1	16	1	1	26728	80038	14	14	0	80000	80000	100	26897	26788	26802	26740	26728
160204	26731	200	0	0	0	0	0	0	1	0	0	26716	2	1	1	10	25	80100	100	80000	100	80000	500	1174887	1	26706	26731	26731	6654	3	6689	80100	200	160000	200	80000	26707	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	43	80000	1	38	80038	6	0	39	0	5110	1	16	1	1	26728	80038	0	14	7	80000	80000	100	26820	26738	26728	26751	26714

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160025	27155	201	1	2	2	0	36	0	0	0	27138	3	7	0	12	61	80010	10	80000	10	80000	50	1169187	26750	26741	26741	6691	3	6722	80010	20	160000	20	80000	26719	26739	1	1	80021	10	9	4	10	10	80000	80000	1	10	80020	19	58	80073	1	0	2	61	80039	6	1	42	0	19	1	5020	5	16	5	5	26733	80074	10	0	5	80000	80000	10	26725	26992	26764	26748	26742
160024	26741	200	1	1	1	1	81	0	0	2	26728	2	7	7	24	25	80010	10	80000	10	80000	50	1172004	26717	26722	26741	6667	3	6725	80010	20	160000	20	80000	26741	26736	1	1	80021	10	9	0	10	10	80000	80000	0	10	80019	19	0	80073	0	0	1	75	80039	6	0	59	45	19	0	5020	4	16	4	4	26738	80034	10	10	0	80000	80000	10	26733	26749	26725	26910	26750
160024	26740	200	1	1	0	0	81	0	0	3	26727	2	7	20	6	25	80010	10	80000	10	80000	50	1169126	26694	26741	26719	6682	3	6699	80010	20	160000	20	80000	26736	26736	1	1	80021	10	9	4	10	10	80000	80000	0	10	80019	19	58	80073	1	0	1	75	80039	6	1	60	45	19	3	5020	5	16	5	5	26740	80073	11	10	5	80000	80000	10	26760	26750	26743	26742	26743
160024	26719	200	1	1	0	0	66	0	0	3	26727	23	7	7	19	25	80010	10	80000	10	80000	50	1183608	26711	26719	26736	6664	3	6716	80010	20	160000	20	80000	26719	26719	1	1	80021	10	9	0	10	10	80000	80000	0	10	80020	20	0	80073	1	0	1	75	80021	6	1	59	0	19	2	5020	3	16	5	3	26738	80073	10	10	0	80000	80000	10	26743	26984	26724	26728	26743
160024	26736	200	1	1	1	1	81	0	0	2	26705	3	7	7	23	25	80010	10	80000	10	80000	50	1167722	26711	26741	26724	6664	3	6699	80010	20	160000	20	80000	26736	26736	1	1	80021	10	9	0	10	10	80000	80000	0	10	80019	20	0	80041	1	0	1	60	80015	6	1	73	45	19	1	5020	5	16	3	3	26733	80061	0	13	0	80000	80000	10	26755	26720	26737	26737	26742
160024	26736	200	1	1	0	0	67	0	0	2	26721	15	7	9	5	25	80010	10	80000	10	80000	50	1170160	26694	26722	26722	6687	3	6716	80010	20	160000	20	80000	26719	26741	1	1	80021	10	9	0	10	10	80000	80000	0	10	80020	19	58	80058	0	0	1	64	80015	6	1	74	0	19	1	5020	3	16	5	5	26718	80074	10	10	5	80000	80000	10	26751	26751	26746	26756	26743
160024	26736	200	1	1	0	0	66	0	0	3	26726	15	0	7	140	25	80010	10	80000	10	80000	50	1168865	26695	26719	26741	6665	3	6721	80010	20	160000	20	80000	26739	26736	1	1	80021	10	9	0	10	10	80000	80000	0	10	80019	20	58	80033	0	0	1	44	80054	6	0	73	43	19	0	5020	4	16	4	4	26738	80034	10	13	5	80000	80000	10	26724	26724	26725	26796	26737
160024	26742	200	1	1	1	0	36	0	0	2	26726	3	7	0	7	25	80010	10	80000	10	80000	50	1168713	26716	26719	26736	6665	3	6699	80010	20	160000	20	80000	26736	26719	1	1	80021	10	9	0	10	10	80000	80000	0	10	80021	20	0	80059	2	0	1	75	80039	6	0	59	45	19	0	5020	5	16	5	5	26738	80058	13	13	5	80000	80000	10	26743	26737	26723	26743	26720
160024	26742	200	1	0	1	0	67	1	0	2	26721	16	7	20	25	25	80010	10	80000	10	80000	50	1169295	26711	26736	26736	6681	3	6716	80010	20	160000	20	80000	26736	26736	1	1	80021	10	9	0	10	10	80000	80000	0	10	80021	19	58	80034	0	0	1	36	80015	0	1	73	45	19	0	5020	4	16	2	3	26739	80034	0	13	5	80000	80000	10	26743	26729	26737	26756	26737
160024	26736	200	1	0	1	0	36	1	0	2	26726	3	7	20	22	25	80010	10	80000	10	80000	50	1172187	26711	26736	26719	6664	3	6722	80010	20	160000	20	80000	26736	26741	1	1	80021	10	9	4	10	10	80000	80000	1	10	80019	19	58	80073	0	0	1	60	80040	0	1	74	43	19	1	5020	4	16	3	4	26739	80060	0	10	5	80000	80000	10	26802	26744	26753	26742	26722

LDNP (signed offset, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations