Firestorm: LDP (D) measurements

Code:

  ldp d0, d1, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2005	403	3	1	1	46	1	1	379	2	12	12	16	25	1000	1000	1000	15053	1	369	394	394	92	3	127	1000	2000	1000	394	394	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	1	16	1	1	395	10	10	4	1000	1000	395	395	395	395	395
2004	394	3	0	0	44	0	1	383	2	1	1	19	25	1000	1000	1000	15284	1	373	398	398	96	3	131	1000	2000	1000	398	394	1	1	1001	1000	1000	0	1000	43	1038	1	38	1038	6	1	39	44	73	1	16	1	1	395	14	14	5	1000	1000	399	399	399	399	403
2004	394	3	1	1	44	0	1	383	2	1	1	19	25	1000	1000	1000	15284	1	373	398	398	96	3	131	1000	2000	1000	398	394	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	398	14	10	7	1000	1000	399	399	399	403	399
2004	398	3	0	0	44	0	1	383	2	1	1	19	25	1000	1000	1000	15014	0	373	398	398	96	3	131	1000	2000	1000	398	394	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	395	10	10	7	1000	1000	395	399	399	399	399
2004	398	3	0	0	44	0	1	383	0	1	1	19	25	1000	1000	1000	15284	1	373	398	398	96	3	131	1000	2000	1000	398	394	1	1	1001	1000	1000	0	1000	43	1039	0	38	1038	6	1	39	43	73	1	16	1	1	395	14	14	7	1000	1000	399	395	399	399	399
2004	398	3	0	0	44	0	1	383	2	1	1	19	25	1000	1000	1000	15284	0	373	398	398	96	3	131	1000	2000	1000	398	394	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	400	14	14	7	1000	1000	399	399	399	399	399
2004	398	2	0	0	44	1	1	383	2	1	1	19	25	1000	1000	1000	15288	1	369	394	398	96	3	131	1000	2000	1000	398	394	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	38	44	73	1	16	1	1	395	14	14	7	1000	1000	400	399	399	399	399
2004	398	3	0	0	44	1	1	383	2	1	1	17	25	1000	1000	1000	15288	1	373	398	442	96	3	131	1000	2000	1000	398	394	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	395	14	14	7	1000	1000	399	395	395	399	399
2004	398	3	0	0	44	0	1	383	2	1	12	16	25	1000	1000	1000	15288	0	369	398	394	96	3	131	1000	2000	1000	398	394	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	395	14	15	7	1000	1000	399	399	399	399	399
2004	398	3	1	1	44	0	1	383	2	1	1	19	25	1000	1000	1000	15284	0	373	398	398	92	3	131	1000	2000	1000	398	394	1	1	1001	1000	1000	0	1000	43	1038	0	658	1038	6	1	39	44	73	1	16	1	1	391	16	14	7	1000	1000	399	395	399	395	399

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp d0, d1, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120057	899	1	1	0	1	1	0	0	0	2	0	1	1	120042	119512	109449	25	60106	40104	10002	10000	30100	10000	10000	1079423	5736374	6119172	0	120033	0	120060	120057	111903	3	112410	50100	30200	20000	10000	60200	10000	10000	120057	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10003	0	0	1	10000	1	1	0	1	1	3210	2	121	1	1	119795	40002	10	10	9	10000	10000	40100	120042	120058	120058	120058	120058
60204	120057	899	1	1	1	0	0	0	0	0	10	0	0	1	120026	119512	109464	25	60106	40104	10002	10000	30100	10000	10000	1079368	5736374	6119172	0	120033	0	120057	120057	111903	3	112410	50100	30200	20000	10000	60200	10000	10000	120057	120058	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	0	10003	0	1	1	10000	1	1	1	1	1	3210	1	121	1	1	119669	40004	10	10	9	10000	10000	40100	120058	120058	120058	120058	120058
60204	120057	899	1	0	0	0	0	0	0	0	2	0	1	1	120042	119512	109449	25	60106	40104	10002	10000	30100	10000	10000	1079423	5736374	6117518	0	120020	0	120041	120105	111903	3	112424	50100	30200	20000	10000	60200	10000	10000	120057	120057	1	1	50201	100	99	100	40100	10000	10000	1	100	10001	2	1	10001	0	1	1	10000	1	1	0	1	2	3210	1	121	1	1	119669	40004	0	10	9	10000	10000	40100	120058	120058	120058	120059	120058
60204	120057	899	1	0	1	1	1	0	0	0	2	0	1	1	120042	119530	109464	25	60106	40104	10001	10000	30100	10000	10000	1079423	5736374	6119172	0	120066	0	120065	120057	111903	3	112410	50100	30200	20000	10000	60200	10000	10000	120057	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	3	1	10001	0	0	1	10000	1	1	0	1	2	3210	1	121	1	1	119669	40004	0	10	0	10000	10000	40100	120058	120058	120058	120058	120058
60204	120060	899	1	1	1	0	0	0	0	0	2	0	1	1	120042	119512	109464	25	60106	40104	10002	10000	30100	10000	10000	1079423	5736374	6119172	0	120651	0	120502	120900	111903	3	112410	50100	30200	20000	10321	60522	10000	10000	120786	120146	1	1	50201	100	99	100	40100	10000	10000	0	100	10008	2	0	10001	0	3	1	10000	0	1	1	1	3	3264	1	127	3	1	120217	40002	0	0	9	10000	10000	40100	120058	120058	120059	120058	120042
60204	120057	899	1	1	2	0	0	0	0	0	1	0	1	1	120453	119530	109464	25	60106	40104	10002	10000	30100	10000	10000	1079423	5736374	6119172	2	120033	0	120057	120057	111903	3	112410	50100	30200	20000	10000	60200	10000	10000	120057	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	2	1	10001	0	1	1	10000	1	1	1	1	0	3210	1	121	1	1	119669	40004	10	0	0	10000	10000	40100	120058	120058	120058	120058	120042
60204	120057	899	1	0	0	0	0	0	0	0	2	0	1	1	120042	119512	109464	25	60106	40104	10002	10000	30100	10000	10000	1079368	5736374	6118304	0	120033	0	120057	120057	111903	3	112410	50100	30200	20000	10000	60200	10000	10000	120057	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10002	0	1	1	10000	0	1	1	1	2	3210	1	100	1	2	119669	40004	10	10	9	10000	10000	40100	120058	120058	120042	120058	120058
60204	120057	900	1	1	0	1	0	0	0	0	11	0	1	1	120026	119512	109449	25	60103	40104	10002	10000	30247	10000	10000	1079423	5736374	6119172	1	120033	0	120057	120057	111903	3	112410	50100	30200	20000	10000	60200	10000	10000	120057	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10001	0	0	1	10000	1	1	1	1	2	3210	1	121	1	1	119669	40004	10	10	9	10000	10000	40100	120058	120058	120058	120058	120059
60204	120057	899	1	1	0	0	0	0	0	0	2	0	1	0	120042	119512	109464	45	60106	40104	10002	10000	30100	10000	10000	1079368	5736374	6119172	1	120033	0	120057	120057	111903	3	112410	50100	30200	20000	10000	60200	10000	10000	120041	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10003	0	1	1	10000	1	1	1	1	0	3210	1	121	1	1	119651	40004	0	10	9	10000	10000	40100	120042	120058	120058	120058	120042
60204	120041	899	1	0	0	1	1	1	0	0	2	0	1	1	120043	119514	109464	25	60103	40102	10002	10000	30100	10000	10000	1079368	5736374	6119172	0	120033	0	120041	120057	111903	3	112410	50100	30200	20000	10000	60200	10000	10000	120041	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10002	0	1	1	10000	1	1	1	1	0	3210	1	121	1	1	119669	40004	10	10	9	10000	10000	40100	120058	120058	120058	120058	120058

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120057	899	1	0	0	0	0	0	4	1	0	0	0	0	0	120079	119484	109459	25	60010	40012	10001	10000	30010	10000	10000	1079951	5736710	6133257	1	120027	120035	120037	111922	3	112448	50010	30020	20424	10000	60020	10000	10000	120035	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	1	1	2	0	0	3140	0	2	99	2	2	119669	40002	10	10	9	10000	10000	40010	120052	120058	120058	120052	120052
60024	120457	899	0	0	0	0	0	0	0	1	0	1	0	0	0	120059	119484	109459	25	60010	40012	10001	10000	30010	10000	10000	1079858	5736084	6124344	1	120027	120053	120051	111919	3	112651	50010	30020	20000	10000	60020	10000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	0	3140	0	2	99	2	2	119669	40002	10	10	9	10000	10000	40010	120036	120052	120036	120056	120036
60024	120051	899	0	0	0	0	0	0	0	1	0	1	0	0	0	120073	119484	109459	25	60013	40012	10001	10000	30010	10212	10000	1079858	5736084	6125746	0	120027	120051	120051	111919	3	112448	50010	30020	20000	10000	61296	10000	10000	120035	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	0	0	10000	1	0	0	0	0	0	0	3140	0	2	94	2	2	119669	40002	10	10	9	10000	10000	40010	120052	120056	120329	120054	120036
60024	120035	900	0	0	0	0	0	0	0	2	0	0	1	0	1	120043	119486	109449	25	60016	40014	10001	10000	30010	10000	10000	1079878	5736182	6123500	0	120032	120053	120053	111924	3	112450	50010	30020	20000	10000	60020	10000	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	3	1	10001	0	0	1	1	10000	1	1	1	1	1	0	0	3140	0	2	99	2	2	119671	40004	6	6	5	10000	10000	40010	120042	120054	120054	120054	120057
60024	120053	899	1	1	0	0	1	0	0	13	0	0	1	0	1	120041	119486	109449	25	60016	40014	10001	10000	30010	10000	10000	1079878	5736182	6125852	0	120029	120053	120053	111909	3	112450	50010	30020	20000	10000	60020	10000	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10002	0	0	1	1	10000	1	1	1	1	0	1	0	3140	0	2	99	2	2	119671	40004	6	6	5	10000	10000	40010	120054	120054	120042	120042	120042
60024	120041	899	1	1	0	0	1	0	0	2	0	0	1	0	1	120067	119486	109449	25	60016	40014	10002	10000	30010	10000	10000	1079878	5735593	6125852	0	120029	120053	120041	111921	3	112450	50010	30020	20000	10000	60020	10000	10107	120057	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	1	1	10012	0	0	1	1	10000	1	1	1	1	2	0	0	3140	0	2	129	2	2	119671	40004	6	6	5	10000	10000	40010	120042	120054	120054	120054	120042
60024	120053	899	1	1	1	0	0	0	0	1	0	0	1	0	1	120043	119486	109461	25	60016	40014	10002	10000	30010	10000	10197	1079887	5736278	6125983	0	120029	120053	120053	111921	3	112550	50010	30020	20000	10000	60020	10000	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10002	0	0	1	1	10000	1	1	1	1	0	0	0	3140	0	2	99	2	2	119671	40004	6	6	5	10000	10000	40010	120054	120042	120054	120054	120054
60024	120099	899	1	1	1	0	0	0	0	7	0	0	1	0	1	120077	119486	109462	25	60016	40014	10002	10000	30010	10000	10000	1079878	5736182	6125852	0	120029	120053	120042	111922	3	112452	50010	30020	20000	10000	60020	10000	10000	120056	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10008	3	1	10002	0	0	1	1	10000	1	1	1	1	1	0	0	3140	0	2	104	2	2	119671	40004	6	6	5	10000	10000	40010	120054	120055	120054	120042	120054
60024	120069	1089	1	0	1	0	0	0	0	56	0	0	0	0	1	120054	119486	109461	25	60016	40046	10001	10000	30010	10000	10000	1079878	5736278	6125852	0	120029	120053	120053	111912	3	112451	50010	30020	20000	10000	60658	10211	10053	120272	120054	5	1	50021	10	9	10	40010	10000	10000	0	10	10003	2	1	10002	0	0	0	10	10000	1	1	1	1	1	0	0	3140	0	2	99	2	2	119671	40004	6	6	5	10000	10000	40010	120054	120054	120064	120437	120055
60024	120053	899	1	1	1	0	0	0	0	14	0	0	1	0	1	120445	119486	109461	25	60016	40014	10001	10000	30572	10000	10000	1079878	5744615	6132706	0	120320	120053	120056	111921	60	112451	50010	30020	20000	10000	60020	10053	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10002	0	0	2	1	10000	0	1	1	1	0	0	0	3140	0	2	119	2	2	119671	40031	6	6	5	10000	10000	40010	120054	120054	120054	120054	120440

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp d0, d1, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120057	900	1	0	1	0	0	1	0	0	0	0	2	0	0	0	0	0	120042	119512	109464	25	60106	40102	10001	10000	30100	10000	10000	1079423	5735593	6119172	1	120017	0	120057	120057	111897	3	112410	50100	30200	20000	10000	60200	10000	10000	120057	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	4	1	10002	0	9	1	1	10000	1	1	1	1	1	0	3211	2	121	2	2	119669	40004	0	10	0	10000	10000	40100	120058	120058	120058	120058	120070
60204	120057	900	1	0	1	0	0	0	0	0	0	0	2	0	1	0	0	1	120042	119530	109464	25	60106	40104	10002	10000	30100	10000	10000	1079368	5736374	6117518	1	120033	0	120057	120041	111897	3	112410	50100	30200	20000	10000	60200	10000	10000	120057	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	3	0	10002	0	84	3	7	10000	1	1	0	1	2	0	3211	2	100	2	2	119669	40004	10	10	9	10000	10000	40100	120042	120058	120058	120042	120086
60204	120057	899	1	0	1	0	0	1	0	0	0	0	2	0	1	0	0	1	120042	119591	109464	25	60106	40104	10002	10000	30100	10000	10000	1079423	5735593	6119172	1	120033	0	120057	120057	111903	3	112415	50100	30200	20000	10000	60200	10000	10000	120057	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10001	0	80	0	1	10000	1	1	1	1	1	0	3211	2	121	1	2	119669	40004	10	10	9	10000	10000	40100	120058	120058	120058	120058	120070
60204	120035	899	0	0	0	0	0	0	1	0	0	0	1	0	1	0	0	0	120036	119495	109459	25	60103	40102	10000	10000	30100	10000	10000	1079552	5736084	6118285	1	120027	0	120051	120035	111896	3	112420	50100	30200	20000	10000	60200	10000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	3	1	1	10000	1	1	1	1	2	0	3211	2	17	2	2	119675	40002	10	10	9	10000	10000	40100	120058	120042	120058	120042	120083
60204	120057	899	1	0	1	0	0	1	0	0	0	0	2	0	0	0	0	1	120042	119512	109464	25	60106	40104	10002	10000	30100	10000	10000	1079368	5736374	6117518	1	120103	0	120057	120041	111897	3	112410	50100	30200	20000	10000	60200	10000	10000	120041	120057	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10001	0	59	0	0	10000	1	0	1	0	0	0	3211	2	108	2	2	119656	40000	10	10	9	10000	10000	40100	120052	120052	120052	120052	120080
60204	120051	899	0	0	0	0	0	0	0	0	0	0	1	0	1	0	0	0	120036	119503	109459	25	60103	40102	10001	10000	30100	10000	10000	1079552	5736084	6118336	1	120027	3	120051	120051	111881	3	112417	50100	30200	20000	10000	60200	10000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	21	10000	1	0	1	0	0	0	3211	2	108	2	2	119665	40002	0	0	9	10000	10000	40100	120052	120052	120052	120036	120101
60204	120051	899	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	120036	119495	109459	25	60103	40102	10001	10000	30100	10000	10000	1079552	5736084	6118285	1	120027	0	120051	120051	111900	3	112374	50100	30200	20000	10000	60200	10000	10000	120051	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	2	0	0	10000	0	0	1	0	0	0	3211	2	135	2	2	119656	40002	0	10	9	10000	10000	40100	120052	120052	120052	120052	120055
60204	120051	899	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	120036	119495	109459	25	60103	40102	10001	10000	30100	10000	10000	1079552	5736084	6118285	1	120027	0	120035	120035	111896	3	112374	50100	30200	20000	10000	60200	10000	10000	120051	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	3	0	0	10000	1	0	1	0	0	0	3211	2	108	2	2	119656	40002	0	10	9	10000	10000	40100	120052	120105	120052	120052	120076
60204	120051	899	0	0	0	0	0	0	0	0	0	0	1	0	1	0	0	0	120036	119495	109459	25	60100	40102	10001	10000	30100	10000	10000	1079552	5736084	6118441	1	120027	0	120051	120035	111896	3	112417	50100	30200	20000	10000	60200	10000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	10035	2	1	10035	0	35	0	89185	10031	1	0	1	0	0	0	3604	5	294	4	5	121637	40196	0	10	9	10000	10000	40100	122510	122444	122511	122538	120099
60204	120035	899	0	0	0	0	0	0	0	0	13	1	3	0	1	0	0	0	120037	120212	110244	855	60402	40326	10000	10000	30525	10157	10098	1091637	5736084	6120939	1	122306	0	122949	123155	112681	584	113966	58865	36328	23452	12108	72788	11756	12040	124295	124301	35	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	29	0	68288	10019	1	0	1	0	0	0	3818	3	315	2	2	119650	40036	10	10	9	10000	10000	40100	122224	123053	122803	122752	120076

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0090

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	0e	0f	19	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120052	899	1	0	0	0	0	0	1	1	0	0	120036	119484	109459	25	60013	40012	10001	10000	30010	10000	10000	1079921	5736084	6125746	1	120027	0	120051	120051	111919	3	112450	50010	30020	20000	10000	60020	10000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	246	10000	1	1	0	3140	6	99	8	8	119669	40002	10	10	9	10000	10000	40010	120052	120052	120052	120052	120052
60024	120072	899	0	0	0	0	0	0	1	0	0	0	120036	119484	109461	25	60013	40012	10001	10000	30010	10000	10000	1079858	5736084	6125746	0	120027	0	120051	120051	111919	3	112448	50010	30020	20000	10062	60020	10000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	219	10000	1	1	0	3140	7	19	7	9	119669	40002	10	10	0	10000	10000	40010	120062	120053	120052	120052	120052
60024	120113	900	0	0	0	0	0	0	1	1	0	0	120036	119484	109459	25	60013	40012	10001	10000	30010	10000	10000	1079858	5736084	6125746	0	120027	0	120051	120051	111919	3	112448	50010	30020	20000	10000	60020	10000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	255	10000	1	1	0	3140	7	99	9	7	119669	40002	10	10	9	10000	10000	40010	120052	120052	120052	120052	120052
60024	120083	900	0	0	0	0	0	0	1	1	0	0	120038	119484	109459	25	60013	40012	10001	10000	30010	10000	10000	1079858	5736084	6125746	0	120027	0	120051	120051	111919	3	112448	50010	30020	20000	10000	60020	10000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	237	10000	1	1	0	3140	7	99	7	8	119669	40002	10	0	9	10000	10000	40010	120052	120052	120052	120052	120052
60024	120073	899	0	0	0	0	0	0	1	0	0	0	120036	119484	109459	25	60013	40012	10001	10000	30010	10000	10000	1079885	5736084	6125746	0	120027	0	120051	120051	111919	3	112448	50010	30020	20000	10000	60020	10000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	15	10000	1	1	0	3140	8	99	7	7	119669	40002	10	10	9	10000	10000	40010	120052	120052	120052	120052	120052
60024	120097	900	0	0	0	0	0	0	1	0	0	0	120036	119484	109459	25	60013	40012	10001	10000	30010	10000	10000	1079885	5736084	6125746	0	120027	0	120051	120051	111919	3	112448	50010	30020	20000	10000	60020	10000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	45	10000	1	1	0	3140	7	99	9	10	119669	40002	10	10	9	10000	10000	40010	120052	120052	120052	120052	120052
60024	120122	899	0	0	0	0	0	0	1	1	0	0	120036	119484	109459	25	60013	40012	10001	10000	30010	10000	10000	1079894	5736084	6125746	0	120027	0	120051	120054	111919	3	112448	50010	30020	20000	10000	60020	10000	10000	120051	120139	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	264	10000	1	1	0	3140	9	99	7	8	119669	40002	10	10	9	10000	10000	40010	120052	120052	120052	120052	120052
60024	120090	900	0	0	0	1	0	0	19	0	0	0	120036	119484	109459	25	60013	40012	10001	10000	30010	10000	10000	1079858	5736084	6125746	0	120027	0	120051	120051	111919	3	112448	50010	30020	20000	10000	60020	10000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	225	10000	1	1	0	3140	8	99	8	9	119669	40002	10	10	9	10000	10000	40010	120052	120052	120052	120052	120052
60024	120100	899	0	0	1	0	0	0	1	1	0	0	120036	119484	109459	25	60013	40012	10001	10000	30010	10000	10000	1079903	5736276	6125746	0	120027	0	120051	120051	111925	3	112448	50010	30020	20000	10000	60020	10000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	3140	8	99	9	9	119669	40002	10	10	9	10000	10000	40010	120052	120052	120052	120052	120052
60024	120068	899	0	0	0	1	1	0	1	1	0	0	120036	119484	109459	25	60013	40012	10001	10000	30010	10000	10000	1079867	5736084	6125746	0	120027	0	120051	120051	111919	3	112449	50010	30020	20000	10000	60020	10000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	234	10000	1	1	0	3140	7	99	6	9	119669	40002	10	10	9	10000	10000	40010	120052	120052	120052	120052	120052

Test 4: throughput

Count: 8

Code:

  ldp d0, d1, [x6]
  ldp d0, d1, [x6]
  ldp d0, d1, [x6]
  ldp d0, d1, [x6]
  ldp d0, d1, [x6]
  ldp d0, d1, [x6]
  ldp d0, d1, [x6]
  ldp d0, d1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160205	26731	201	0	0	0	0	1	0	0	54	0	1	0	1	26712	0	12	0	19	25	80100	100	80000	100	80000	500	1174628	0	26821	26727	26745	6654	3	6685	80100	200	160000	200	80000	26731	26727	1	1	80202	100	99	100	100	80000	80000	0	100	80000	0	43	0	80038	0	0	0	38	80038	6	1	39	43	0	0	1	5110	2	16	2	2	26728	0	14	10	7	80000	80000	100	26732	26728	26732	26732	26708
160204	26727	200	0	0	0	0	1	0	0	44	0	1	0	1	26712	2	12	1	16	25	80100	100	80000	100	80000	500	1169085	0	26706	26711	26739	6630	3	6689	80100	200	160000	200	80000	26731	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	43	0	80038	0	0	0	38	80038	6	1	39	44	0	0	0	5110	2	16	2	2	26728	0	14	14	7	80000	80000	100	26732	26732	26732	26732	26708
160204	26731	200	0	0	0	0	1	0	0	0	0	0	0	1	26712	2	12	1	16	25	80100	100	80000	100	80000	500	1169085	0	26715	26731	26707	6650	3	6685	80100	200	160000	200	80000	26731	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	43	0	80038	0	0	0	38	80038	6	1	0	44	0	0	0	5110	2	16	2	2	26728	0	14	10	7	80000	80000	100	26728	26728	26708	26732	26728
160204	26934	200	0	0	0	0	1	0	0	45	0	0	0	1	26712	2	12	12	16	25	80100	100	80000	100	80000	500	1168754	1	26715	26727	26727	6650	3	6665	80100	200	160000	200	80000	26727	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	43	0	80039	0	0	0	39	80038	6	1	39	44	0	0	0	5110	2	16	2	2	26728	0	14	0	7	80000	80000	100	26732	26708	26732	26732	26732
160204	26731	201	0	0	0	0	1	0	0	44	0	1	0	1	26716	2	0	12	19	25	80100	100	80000	100	80000	500	1169085	0	26716	26731	26727	6630	3	6665	80100	200	160000	200	80000	26731	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	43	0	80039	0	0	0	38	80038	6	1	38	43	0	0	0	5110	2	16	2	2	26728	0	14	14	7	80000	80000	100	26732	26732	26732	26732	26708
160204	26736	207	0	0	0	0	1	0	0	344	0	0	0	1	26716	2	12	0	19	25	80100	100	80000	100	80000	500	1169085	0	26714	26731	26731	6654	3	6665	80100	200	160000	200	80000	26731	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	0	80000	0	0	0	38	80038	6	1	36	44	0	0	0	5110	2	16	2	2	26728	0	14	14	7	80000	80000	100	26732	26732	26732	26731	26732
160204	26727	201	0	0	0	0	1	0	0	44	0	0	0	1	26716	2	12	0	0	25	80100	100	80000	100	80000	500	1168627	0	26702	26727	26731	6654	3	6685	80100	200	160000	200	80000	26727	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	43	0	80039	0	0	0	188	80038	6	1	39	43	0	0	0	5110	2	16	2	2	26704	0	14	10	7	80000	80000	100	26728	26728	26732	26732	26732
160204	26727	200	0	0	1	0	1	0	0	67	0	1	0	1	26716	2	1	12	19	25	80100	100	80000	100	80000	500	1174887	0	26702	26749	26741	6660	3	6689	80100	200	160000	200	80000	26731	26707	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	43	0	80054	0	0	0	39	80000	0	1	39	44	0	0	0	5110	2	16	2	2	26728	0	0	0	7	80000	80000	100	26708	26732	26732	26732	26732
160204	26727	200	0	0	0	0	1	0	0	44	0	1	0	1	26813	2	1	1	19	25	80100	100	80000	100	80000	500	1174887	0	26713	26727	26731	6650	3	6689	80100	200	160000	200	80000	26731	26727	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	43	0	80000	0	0	0	0	80038	6	1	39	44	0	0	0	5110	2	16	2	2	26728	0	0	10	7	80000	80000	100	26732	26732	26732	26732	26728
160204	26731	201	0	0	0	0	1	0	0	44	0	1	0	1	26692	2	1	1	19	25	80100	100	80000	100	80000	500	1169085	0	26713	26731	26731	6650	3	6689	80100	200	160000	200	80000	26731	26727	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	43	0	80000	0	0	0	38	80038	6	0	38	44	0	0	0	5110	2	16	2	2	26724	0	14	14	4	80000	80000	100	26708	26732	26728	26732	26732

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160025	26745	200	0	0	0	1	0	0	1	0	0	45	0	1	0	0	26712	0	12	1	19	25	80010	10	80000	10	80000	50	1168754	1	26706	0	26727	26735	6682	3	6707	80010	20	160000	20	80000	26727	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	43	80039	0	0	0	39	80000	6	0	19	43	19	1	5021	1	14	16	0	17	17	26733	13	13	5	80000	80000	10	26741	26741	26719	26741	26719
160024	26736	201	1	1	1	2	1	0	1	0	0	45	0	1	0	1	26712	2	0	12	18	25	80010	10	80000	10	80000	50	1174628	0	26702	0	26828	26709	6672	3	6707	80010	20	160000	20	80000	26727	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	43	80040	0	0	0	39	80000	6	1	58	43	19	1	5021	1	16	16	0	17	17	26711	13	13	5	80000	80000	10	26737	26737	26719	26719	26741
160024	26736	200	1	1	0	2	1	0	1	0	0	0	0	0	0	0	26712	2	12	12	19	25	80010	10	80000	10	80000	50	1175162	1	26853	0	26740	26736	6684	3	6694	80010	20	160000	20	80000	26714	26742	1	1	80021	10	9	10	10	80000	80000	0	10	80152	20	0	80151	0	0	1	21	80000	6	1	39	43	0	0	5021	1	17	16	0	17	17	26724	14	10	0	80000	80000	10	26728	26916	26728	26708	26734
160024	26727	204	0	0	0	0	0	0	1	0	0	27	88	0	0	2	26859	0	0	12	20	25	80010	10	80000	10	80000	50	1168754	1	26702	0	26738	26735	6672	3	6711	80010	20	160000	20	80000	26727	26731	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	43	80000	0	0	0	0	80000	6	0	39	43	0	0	5021	1	16	16	0	17	17	26724	14	10	4	80000	80000	10	26732	26728	26732	26708	26708
160024	26727	200	1	0	0	1	0	0	1	0	4	91	0	0	0	3	26699	3	0	0	19	25	80010	10	80000	10	80000	50	1167722	1	26868	0	26731	26730	6672	3	6707	80010	20	160000	20	80000	26727	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	43	80039	0	1	0	42	80039	0	1	59	43	19	0	5021	1	16	16	0	13	16	26728	0	10	4	80000	80000	10	26708	26728	26728	26708	26728
160024	26731	200	1	0	0	1	0	0	0	0	0	45	0	1	0	1	26712	2	12	0	20	25	80010	10	80000	10	80000	50	1168754	1	26706	0	26727	26707	6673	3	6711	80010	20	160000	20	80000	26731	26707	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	43	80038	0	0	0	39	80039	6	0	39	43	0	0	5021	1	17	16	0	17	17	26704	10	10	4	80000	80000	10	26728	26732	26896	26742	26728
160024	26731	200	1	0	0	1	0	0	1	0	0	21	0	1	0	3	26721	2	7	7	19	25	80010	10	80000	10	80000	50	1169295	0	26707	0	26707	26727	6672	3	6707	80010	20	160000	20	80000	26727	26727	1	1	80022	10	9	10	10	80000	80000	0	10	80000	0	43	80000	0	1	0	45	80039	6	1	59	44	19	0	5021	1	17	16	0	17	17	26733	13	13	5	80000	80000	10	26715	26737	26737	26715	26738
160024	26714	200	1	1	0	1	1	0	1	0	0	0	0	0	0	1	26712	2	12	12	0	25	80010	10	80000	10	80000	50	1174628	0	26707	0	26727	26727	6653	3	6707	80010	20	160000	20	80000	26727	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	43	80039	0	0	0	0	80000	6	1	0	43	0	0	5021	1	17	16	0	16	17	26704	0	10	0	80000	80000	10	26728	26708	26728	26728	26728
160024	26707	200	1	0	0	1	0	0	1	0	0	67	0	1	0	3	26699	3	0	7	19	25	80010	10	80000	10	80000	50	1169295	1	26716	0	26707	26727	6653	3	6707	80010	20	160000	20	80000	26727	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	43	80000	0	0	0	42	80039	6	1	0	0	0	0	5021	1	17	16	0	17	17	26724	10	10	0	80000	80000	10	26708	26732	26732	26728	26728
160024	26727	200	1	0	0	1	0	0	1	0	0	93	0	0	0	2	26699	3	7	7	20	25	80010	10	80000	10	80000	50	1170179	0	26702	0	26801	26731	6672	3	6707	80010	20	160000	20	80000	26727	26727	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	43	80000	0	0	0	0	80039	6	1	39	43	0	0	5021	1	17	16	0	10	16	26724	10	10	4	80000	80000	10	26728	26728	26728	26728	26728

LDP (D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations