Firestorm: LDP (Q) measurements

Code:

  ldp q0, q1, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
2005	727	6	0	1	0	1	0	0	0	67	1	4	721	2	7	7	19	25	2000	2000	2000	30073	1	711	737	736	434	3	469	2000	2000	2000	736	736	1	1	1001	1000	1000	0	2020	19	43	2058	1	0	1	60	2040	6	1	58	42	18	0	75	5	16	6	6	733	13	13	5	2000	737	737	737	737	737
2004	736	5	1	1	0	1	0	1	1	67	1	4	721	2	7	7	19	25	2000	2000	2000	30134	1	711	736	736	434	3	469	2000	2000	2000	736	736	1	1	1001	1000	1000	0	2020	20	43	2058	0	0	1	61	2040	6	1	58	43	19	1	75	6	16	6	6	733	13	13	5	2000	737	737	737	737	737
2004	736	6	1	1	1	1	0	0	0	67	1	4	699	2	7	7	19	25	2000	2000	2000	30066	1	711	736	736	433	3	469	2000	2000	2000	736	736	1	1	1001	1000	1000	0	2020	20	43	2059	1	0	2	61	2039	6	1	59	43	19	1	75	6	16	6	6	733	13	13	5	2000	737	737	737	737	737
2004	736	6	1	1	1	1	1	0	1	66	1	3	721	3	7	7	18	25	2000	2000	2000	30095	0	711	736	736	434	3	470	2000	2000	2000	737	736	1	1	1001	1000	1000	0	2021	19	43	2060	1	0	2	60	2041	6	1	59	43	19	0	75	5	16	5	5	733	13	13	5	2000	737	737	737	737	737
2004	736	5	1	1	1	1	0	0	0	69	1	3	721	1	7	7	19	25	2000	2000	2000	30403	0	795	736	736	434	3	469	2000	2000	2000	736	736	1	1	1001	1000	1000	0	2019	19	43	2058	0	0	2	60	2040	6	1	59	43	19	1	75	6	16	6	6	733	13	13	5	2000	742	737	737	737	737
2004	736	6	1	1	1	1	1	1	0	70	1	4	721	2	7	7	19	25	2000	2000	2000	30170	1	711	736	736	434	3	469	2000	2000	2000	736	736	1	1	1001	1000	1000	0	2020	20	43	2059	1	0	1	61	2040	6	1	59	43	19	1	75	6	16	6	5	733	13	13	5	2000	737	737	737	737	737
2004	736	5	1	1	1	1	0	0	0	66	0	3	721	3	7	7	20	25	2000	2000	2000	30169	0	711	757	736	434	3	469	2000	2000	2000	736	736	1	1	1001	1000	1000	1	2019	19	43	2059	0	0	0	64	2039	6	1	59	43	19	2	75	5	16	5	5	733	13	13	5	2000	737	737	737	737	737
2004	736	5	1	1	0	1	0	0	0	66	1	4	721	3	7	7	18	25	2000	2000	2000	30095	1	711	736	736	433	3	469	2000	2000	2000	736	736	1	1	1001	1000	1000	0	2020	20	43	2059	1	0	1	64	2039	6	1	59	43	19	1	75	5	16	5	5	733	13	13	5	2000	737	737	737	737	738
2004	736	5	1	1	1	1	0	0	0	67	0	3	721	2	7	9	19	25	2000	2000	2000	30095	1	711	736	736	434	3	469	2000	2000	2000	736	736	1	1	1001	1000	1000	0	2020	20	43	2058	1	0	2	61	2040	6	1	58	43	19	1	75	5	16	5	5	733	13	13	5	2000	737	737	737	737	737
2004	736	5	1	1	1	1	0	0	0	67	1	4	721	2	7	7	19	25	2000	2000	2000	30170	1	711	736	737	434	3	469	2000	2000	2000	736	736	1	1	1001	1000	1000	0	2020	20	43	2060	0	6	1	61	2039	6	1	59	43	19	1	75	5	16	5	5	733	13	13	5	2000	737	737	737	737	737

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp q0, q1, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	0e	0f	19	1e	1f	22	23	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120057	899	0	0	0	0	2	0	1	0	0	120036	96716	109740	25	70100	40102	10001	20000	30100	10000	20000	10426743	5733436	3465626	1	120027	0	120055	120051	112123	3	112509	60100	30200	20000	10000	60966	20062	10000	120051	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	20000	2	2	3237	2	16	1	1	119824	40002	10	10	9	20000	40100	120038	120050	120052	120052	120036
60204	120051	899	1	0	0	0	2	0	1	0	0	120020	96716	109740	25	70103	40102	10000	20000	30100	10000	20000	10426743	5733724	3467648	0	120027	0	120051	120051	112139	3	112509	60100	30200	20000	10000	60200	20000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	20000	2	2	3210	1	16	1	1	119824	40002	0	10	9	20000	40100	120036	120052	120052	120052	120052
60204	120051	899	1	1	0	0	2	0	0	0	0	120036	96716	109740	25	70103	40102	10001	20000	30100	10000	20000	10426743	5733724	3467452	0	120027	0	120051	120051	112139	3	112509	60100	30200	20000	10000	60200	20000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	2	20000	0	0	20000	0	2	3210	1	16	0	1	119824	40002	10	0	9	20000	40100	120052	120052	120052	120052	120036
60204	120051	899	1	0	0	0	0	0	0	0	0	120036	96716	109740	25	70103	40102	10001	20000	30100	10000	20000	10426743	5733724	3467052	0	120027	3	120054	120051	112139	3	112509	60100	30200	20000	10000	60200	20000	10000	120035	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	20000	2	2	3210	1	16	1	1	119824	40002	10	0	9	20000	40100	120052	120052	120036	120052	120052
60204	120035	899	1	0	0	0	2	0	1	0	0	120036	96716	109748	25	70103	40102	10001	20000	30100	10000	20000	10426743	5735548	3466280	0	120027	0	120051	120051	112139	3	112509	60100	30200	20000	10000	60200	20000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	20000	2	2	3210	1	16	1	1	119824	40002	0	0	9	20000	40100	120052	120036	120052	120052	120052
60204	120051	899	1	0	0	0	0	0	0	0	0	120038	97403	109740	25	70103	40102	10001	20000	30100	10000	20000	10426743	5732956	3467195	0	120027	0	120051	120035	112139	3	112509	60100	30200	20000	10000	60200	20000	10000	120035	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	20000	2	0	3210	1	16	1	1	119824	40002	10	10	9	20000	40100	120052	120052	120053	120052	120052
60204	120035	899	1	0	0	0	2	0	1	0	0	120036	96716	109740	25	70103	40102	10001	20000	30100	10000	20000	10426743	5733724	3465800	0	120027	0	120051	120051	112139	3	112509	60100	30200	20000	10000	60200	20000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	20000	2	0	3210	1	16	1	1	119808	40002	10	10	9	20000	40100	120052	120052	120052	120036	120036
60204	120051	899	1	0	0	0	2	0	1	0	0	120036	96716	109740	25	70100	40102	10001	20000	30100	10000	20000	10426743	5733724	3467655	0	120027	0	120051	120051	112139	3	112509	60100	30200	20000	10000	60200	20000	10000	120051	120051	1	1	50202	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	20000	0	2	3210	1	16	1	1	119824	40000	10	10	9	20000	40100	120036	120052	120036	120052	120052
60204	120051	899	1	0	0	0	2	0	1	0	0	120020	96716	109740	25	70103	40102	10003	20000	30100	10000	20000	10425228	5733724	3467370	0	120027	0	120051	120051	112139	3	112509	60100	30200	20000	10000	60200	20000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	3	20000	2	2	3210	1	16	1	1	119824	40002	10	10	9	20000	40100	120052	120052	120052	120036	120052
60204	120035	899	1	0	0	0	2	0	0	0	0	120036	96716	109744	25	70103	40102	10001	20000	30100	10000	20000	10426743	5733724	3466730	0	120030	0	120035	120051	112139	3	112509	60277	30200	20000	10000	60200	20000	10000	120091	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	2	20000	0	0	20000	2	2	3210	1	16	1	1	119824	40002	10	10	9	20000	40100	120052	120036	120052	120052	120052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120051	899	0	0	0	0	0	0	0	2	0	0	0	0	0	120036	93975	109740	25	70013	40012	10001	20000	30010	10000	20000	10425374	5733436	3465350	0	120090	120051	120051	112162	3	112515	60010	30020	20000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	0	20000	2	2	0	3140	5	16	1	1	119826	40000	10	10	9	20000	40010	120052	120036	120052	120036	120052
60024	120051	899	0	0	0	0	0	0	0	2	0	1	0	0	0	120036	96641	109740	25	70013	40010	10001	20000	30010	10000	20000	10425374	5733436	3465350	0	120107	120051	120074	112162	3	112537	60190	30020	20000	10000	60020	20000	10000	120054	120053	1	1	50021	10	9	10	40010	10000	10000	1	10	20000	2	20000	0	0	0	20000	2	2	0	3140	1	16	1	1	119826	40002	10	10	9	20000	40010	120052	120052	120052	120052	120052
60024	120051	899	0	0	0	0	0	0	0	2	0	1	0	0	0	120036	96641	109740	25	70013	40012	10000	20000	30010	10000	20000	10425374	5733436	3465350	0	120027	120058	120051	112162	3	112531	60010	30020	20000	10000	60020	20000	10000	120051	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	0	20000	2	2	1	3140	1	16	1	1	119826	40002	10	10	9	20000	40010	120052	120052	120052	120052	120052
60024	120055	899	0	0	0	0	0	0	0	2	0	1	0	0	0	120036	96641	109740	25	70013	40012	10000	20000	30010	10000	20000	10425374	5733436	3465350	0	120028	120051	120051	112162	24	112548	60010	30020	20000	10000	60020	20000	10000	120051	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	0	20000	2	2	0	3140	1	16	1	1	119810	40002	10	10	0	20000	40010	120052	120052	120052	120052	120052
60024	120051	899	0	0	0	0	0	0	0	2	0	0	0	0	0	120020	96641	109724	25	70010	40012	10001	20000	30010	10000	20000	10426827	5733436	3465350	0	120011	120051	120051	112162	3	112515	60010	30020	20000	10000	60404	20062	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	0	20000	2	2	0	3140	1	16	1	1	119826	40000	10	10	9	20000	40010	120052	120052	120052	120052	120036
60024	120051	899	0	0	0	0	0	0	0	2	0	1	0	0	0	120020	93975	109724	25	70010	40012	10001	20000	30010	10000	20000	10425374	5734160	3465350	0	120027	120051	120051	112146	3	112531	60010	30020	20000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	0	20000	2	2	0	3140	1	16	1	1	119826	40000	10	10	9	20000	40010	120052	120052	120052	120036	120052
60024	120051	899	0	0	0	0	0	0	0	2	0	0	0	0	0	120036	96641	109740	25	70013	40012	10000	20002	30010	10000	20000	10425374	5732666	3465350	0	120027	120035	120051	112162	3	112531	60010	30020	20000	10000	60020	20000	10000	120055	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20004	1	0	0	20000	2	2	0	3140	1	16	1	1	119826	40002	10	0	9	20000	40010	120052	120052	120036	120036	120036
60024	120051	899	0	0	0	0	0	0	0	2	0	0	0	0	0	120038	96641	109740	25	70013	40012	10001	20000	30010	10000	20000	10425374	5733436	3465350	0	120011	120051	120051	112162	3	112531	60010	30020	20000	10000	60020	20000	10000	120051	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	0	20000	2	2	0	3140	1	16	1	1	119826	40002	0	10	9	20000	40010	120052	120052	120052	120052	120052
60024	120051	899	0	0	0	0	0	0	0	2	0	1	0	0	0	120036	96641	109740	25	70013	40010	10001	20000	30010	10000	20000	10425374	5733436	3465350	0	120027	120051	120051	112162	3	112531	60010	30020	20000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	0	20000	2	2	0	3140	1	16	1	1	119826	40002	10	10	9	20000	40010	120057	120052	120052	120052	120052
60024	120051	899	0	0	0	0	0	0	0	2	0	1	0	0	0	120036	96641	109740	25	70010	40012	10001	20000	30010	10000	20000	10425374	5733436	3465350	0	120027	120051	120051	112162	3	112531	60010	30112	20000	10000	60020	20000	10000	120051	120051	2	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	0	20000	2	2	0	3140	1	16	1	1	119826	40002	10	10	9	20000	40010	120052	120052	120056	120052	120052

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp q0, q1, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	aa	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120053	899	0	0	0	1	0	0	0	2	0	1	0	0	1	120036	96712	109740	25	70103	40102	10001	20000	30100	10000	20000	10426743	5733436	3465156	1	120023	120047	120047	112135	3	112505	60100	30200	20000	10000	60200	20000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	0	2	20000	0	0	0	0	20000	2	0	2	0	0	3210	2	16	2	1	119820	40002	0	6	9	20000	40100	120052	120052	120052	120048	120052
60204	120051	899	0	0	0	1	0	0	0	2	0	0	0	0	1	120036	96716	109736	25	70100	40102	10001	20000	30100	10000	20000	10426743	5733436	3465510	1	120011	120047	120047	112141	3	112505	60100	30200	20000	10000	60200	20000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	0	2	20000	0	0	0	0	20000	0	0	2	0	0	3210	2	16	1	1	119824	40002	10	6	9	20000	40100	120048	120052	120048	120048	120052
60204	120051	900	0	0	0	0	0	0	0	2	0	0	0	0	1	120036	96716	109740	25	70103	40102	10001	20000	30100	10000	20000	10426827	5733436	3465626	1	120027	120051	120047	112140	3	112509	60100	30200	20000	10000	60200	20000	10000	120051	120035	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	0	0	20000	0	0	0	0	20000	0	0	2	0	0	3210	2	16	1	2	119825	40002	10	6	0	20000	40100	120053	120052	120036	120052	120052
60204	120055	899	0	0	0	0	0	0	0	2	0	1	0	0	1	120036	96716	109740	25	70103	40102	10001	20000	30100	10000	20000	10426743	5733244	3465510	1	120027	120035	120047	112139	3	112509	60100	30200	20000	10000	60200	20000	10000	120055	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	0	20000	2	0	2	0	0	3210	2	16	1	1	119824	40002	10	0	9	20000	40100	120052	120052	120036	120048	120052
60204	120051	899	0	0	0	0	0	0	0	15	0	0	0	0	0	120020	96720	109740	25	70103	40102	10001	20000	30100	10000	20000	10426743	5733436	3465626	1	120027	120047	120047	112139	3	112505	60100	30200	20000	10000	60200	20000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	0	2	20000	0	0	0	0	20000	2	0	2	0	0	3210	2	16	2	2	119824	40002	10	6	9	20000	40100	120052	120052	120052	120052	120052
60204	120051	899	0	0	0	0	0	0	0	2	0	0	0	0	0	120036	96716	109740	25	70103	40102	10001	20000	30100	10000	20000	10426395	5733244	3465156	1	120027	120035	120051	112139	3	112493	60100	30200	20000	10000	60200	20000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	0	2	20000	0	0	0	3	20000	0	0	2	0	0	3210	2	16	2	1	119824	40002	10	0	5	20000	40100	120052	120052	120052	120052	120052
60204	120051	899	0	0	0	0	0	0	0	14	0	0	1	0	1	120036	96716	109736	25	70103	40102	10001	20000	30100	10000	20000	10425228	5734469	3465993	1	120011	120035	120035	112139	3	112513	60100	30200	20000	10000	60200	20000	10000	120051	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	3	0	6	20000	0	0	0	0	0	3210	2	16	2	2	119820	40002	6	0	5	20000	40100	120048	120052	120036	120052	120048
60204	120051	899	0	0	0	0	0	0	0	2	0	0	1	0	0	120036	96716	109740	25	70103	40102	10001	20000	30100	10000	20000	10425228	5733436	3465626	1	120011	120047	120047	112139	3	112509	60100	30200	20000	10000	60200	20000	10000	120051	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	0	20000	0	0	0	0	20000	2	0	2	0	0	3210	2	16	2	2	119824	40002	0	10	9	20000	40100	120048	120036	120052	120052	120048
60204	120072	899	0	0	0	0	0	0	0	2	0	0	1	0	1	120036	98085	110840	547	70492	40336	10077	20100	32492	10794	21304	10545030	5805520	3506495	1	120483	122336	122424	113178	166	113976	64607	32757	21636	10852	65332	21636	10823	122379	122397	28	1	50201	100	99	100	40100	10000	10000	0	100	20066	0	2	20060	1	1	0	59815	20000	2	0	2	0	0	3677	2	220	4	2	121540	40229	6	6	9	20000	40100	122624	122337	122473	122636	122333
60204	122893	919	1	1	1	1	1	41	34	6089	2464	0	1	0	0	122185	97726	111564	785	70681	40359	10115	20144	32785	11256	21854	10589849	5842820	3517767	1	120884	120047	120047	113150	40	113915	64774	32111	21444	10759	64372	21698	10571	122456	121992	25	1	50201	100	99	100	40100	10000	10000	1	100	20000	0	2	20006	0	0	30	69143	20044	2	0	2	1	1	3237	3	16	1	2	119820	40002	10	6	9	20000	40100	120052	120052	120048	120052	120048

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120054	899	0	0	1	0	14	1	0	0	120020	96646	109741	110	70013	40012	10003	20000	30010	10000	20000	10425626	5733484	3465350	1	120027	0	120051	120051	112162	3	112531	60010	30020	20000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	20000	2	2	0	0	0	3140	5	16	2	3	119816	40002	0	10	9	20000	40010	120052	120052	120052	120052	120052
60024	120051	899	0	0	0	0	2	0	0	0	120036	96641	109740	25	70013	40012	10001	20000	30010	10000	20000	10425374	5734662	3465350	0	120011	0	120051	120051	112162	3	112531	60010	30020	20000	10000	60020	20000	10000	120035	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20004	5	0	20000	2	2	0	0	0	3140	2	16	2	3	119826	40002	0	10	0	20000	40010	120036	120052	120052	120036	120052
60024	120051	899	0	0	0	0	0	0	0	0	120036	93975	109741	25	70013	40012	10001	20004	30010	10000	20000	10425374	5733436	3465350	1	120027	0	120051	120051	112146	3	112531	60010	30020	20000	10000	60020	20000	10000	120035	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	47	0	20000	2	2	0	0	0	3140	2	16	3	2	119826	40002	10	10	9	20000	40010	120052	120093	120058	120052	120052
60024	120051	899	0	0	0	0	11	0	0	0	120020	96641	109740	35	70013	40012	10001	20000	30010	10000	20000	10425374	5733436	3465350	0	120027	0	120051	120051	112162	3	112531	60010	30020	20000	10000	60020	20000	10000	120051	120096	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	20000	2	2	0	0	0	3140	2	16	3	3	119827	40000	10	10	9	20000	40010	120052	120052	120052	120052	120052
60024	120035	899	0	0	0	0	2	1	0	0	120036	96641	109724	25	70013	40012	10001	20000	30010	10000	20000	10425374	5733436	3465350	1	120011	0	120035	120051	112162	3	112531	60010	30020	20000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20002	4	0	20000	2	2	0	0	0	3140	3	16	3	3	119826	40000	10	10	9	20000	40010	120052	120057	120052	120052	120057
60024	120035	899	0	0	0	0	2	1	0	0	120036	96641	109740	25	70013	40012	10001	20000	30010	10000	20000	10425374	5733436	3465350	0	120011	0	120035	120051	112162	3	112515	60010	30020	20000	10000	60020	20000	10000	120053	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	0	20000	0	0	20000	0	0	0	0	0	3140	3	16	3	2	119826	40002	0	10	9	20000	40010	120052	120052	120052	120052	120052
60024	120035	899	0	0	0	0	2	1	0	0	120036	96641	109740	25	70013	40012	10001	20000	30010	10000	20050	10425374	5733436	3465350	0	120027	0	120035	120051	112162	3	112515	60010	30020	20000	10000	60020	20000	10000	120035	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	1	0	20000	0	2	0	0	0	3140	4	16	3	3	119810	40000	10	0	9	20000	40010	120052	120052	120052	120053	120052
60024	120035	900	0	0	0	1	2	1	0	0	120036	96641	109724	25	70013	40012	10001	20000	30010	10000	20000	10425374	5733436	3465350	0	120027	0	120051	120051	112146	3	112531	60010	30020	20000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	0	20000	1	0	20000	2	2	0	0	0	3140	3	16	4	4	119826	40002	10	10	9	20000	40010	120037	120052	120036	120052	120052
60024	120051	929	0	0	0	0	2	0	0	0	120036	96641	109740	25	70013	40012	10001	20000	30010	10000	20000	10425374	5732666	3465490	1	120011	0	120035	120051	112162	3	112576	60010	30020	20000	10000	60020	20000	10000	120051	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	20004	2	2	0	0	0	3140	3	16	3	3	119826	40002	0	10	0	20000	40010	120052	120052	120128	120037	120052
60024	120035	899	0	0	0	0	2	1	0	0	120036	96686	109740	25	70013	40012	10001	20000	30010	10000	20000	10425374	5732666	3464880	0	120011	0	120051	120051	112162	3	112531	60010	30020	20000	10000	60020	20000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	20000	2	2	0	0	0	3140	3	16	2	3	119826	40002	10	10	9	20000	40010	120052	120052	120097	120102	120052

Test 4: throughput

Count: 8

Code:

  ldp q0, q1, [x6]
  ldp q0, q1, [x6]
  ldp q0, q1, [x6]
  ldp q0, q1, [x6]
  ldp q0, q1, [x6]
  ldp q0, q1, [x6]
  ldp q0, q1, [x6]
  ldp q0, q1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6674

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	19	1e	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160205	53393	400	1	1	0	44	1	0	0	1	53374	2	18	18	12	25	160100	100	160000	100	160000	500	2325261	1	53364	53389	53394	33312	3	33347	160100	200	160000	200	160000	53394	53394	1	1	80201	100	99	100	100	80000	80000	1	100	160000	39	160035	0	1	0	41	160035	6	1	35	39	0	5110	1	16	1	1	53386	0	6	6	2	160000	100	53390	53390	53399	53676	53414
160204	53389	400	0	0	0	41	1	0	0	1	53374	2	18	18	169	25	160100	100	160000	100	160000	500	2325261	1	53364	53389	53389	33312	3	33347	160100	200	160000	200	160000	53389	53389	1	1	80201	100	99	100	100	80000	80000	0	100	160000	39	160035	0	2	0	41	160036	6	1	35	39	0	5110	1	16	1	1	53386	0	6	6	2	160000	100	53390	53390	53390	53390	53497
160204	53389	400	0	1	0	41	1	0	0	1	53374	2	18	18	12	25	160100	100	160000	100	160000	500	2325261	1	53364	53389	53389	33312	3	33361	160100	200	160000	200	160000	53394	53389	1	1	80201	100	99	100	100	80000	80000	0	100	160000	39	160035	0	1	0	35	160035	6	1	35	39	0	5110	1	16	1	1	53389	0	6	6	2	160000	100	53390	53390	53390	53678	53390
160204	53389	400	0	0	0	45	1	0	0	1	53374	2	18	18	80	25	160100	100	160000	100	160000	500	2325261	1	53364	53389	53389	33312	3	33347	160100	200	160000	200	160000	53389	53389	1	1	80201	100	99	100	100	80000	80000	0	100	160000	39	160035	0	3	0	35	160035	6	1	35	39	0	5110	1	16	1	1	53386	0	6	6	2	160000	100	53390	53390	53390	53390	53411
160204	53389	400	0	0	0	41	1	0	0	1	53374	2	18	18	116	25	160100	100	160000	100	160000	500	2325405	1	53364	53389	53389	33315	3	33347	160100	200	160000	200	160000	53393	53389	1	1	80201	100	99	100	100	80000	80000	0	100	160000	39	160035	0	29	0	38	160035	6	1	35	39	0	5110	1	16	1	1	53391	0	6	6	2	160000	100	53394	53394	53394	53394	53404
160204	53393	400	0	0	0	53	0	0	0	1	53374	2	18	18	14	25	160100	100	160000	100	160000	500	2325261	1	53371	53397	53397	33315	3	33360	160100	200	160000	200	160000	53393	53389	1	1	80201	100	99	100	100	80000	80000	0	100	160000	39	160035	0	2	0	38	160035	6	1	35	39	0	5110	1	16	1	1	53386	0	6	6	2	160000	100	53395	53393	53390	53393	53390
160204	53389	399	0	0	0	53	1	0	0	1	53385	2	18	18	152	25	160100	100	160000	100	160000	500	2325415	1	53415	53389	53389	33312	3	33351	160100	200	160216	200	160000	53389	53481	1	1	80201	100	99	100	100	80000	80000	0	100	160000	39	160558	0	3	0	35	160035	6	1	35	39	0	5126	1	16	1	1	53390	0	6	7	2	160000	100	53390	53390	53390	53390	53394
160204	53393	414	0	0	0	41	1	0	0	1	53374	2	18	18	187	25	160100	100	160000	100	160000	500	2340097	1	53364	53389	53389	33312	3	33347	160100	200	160000	200	160000	53389	53389	1	1	80201	100	99	100	100	80000	80000	0	100	160000	39	160035	0	0	0	3239	160035	6	1	35	39	0	5110	1	16	1	1	53386	0	6	6	2	160000	100	53395	53390	53390	53390	53390
160204	53389	399	0	0	0	41	0	0	0	1	53374	2	18	18	168	25	160100	100	160000	100	160000	500	2325261	1	53364	53389	53389	33312	3	33347	160100	200	160000	200	160000	53389	53389	1	1	80201	100	99	100	100	80000	80000	0	100	160000	39	160035	0	0	0	35	160035	6	1	35	39	0	5110	1	16	1	1	53386	0	6	6	2	160000	100	53390	53390	53390	53390	53497
160204	53389	400	0	0	0	41	1	0	0	1	53374	2	18	18	46	25	160100	100	160000	100	160000	500	2343394	1	53364	53389	53389	33312	3	33350	160100	200	160000	200	160000	53389	53389	1	1	80201	100	99	100	100	80000	80000	0	100	160000	39	160035	0	0	0	35	160035	6	1	35	39	0	5110	1	16	1	1	53386	0	6	6	2	160000	100	53390	53390	53390	53390	53404

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	0e	0f	19	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160025	53395	400	0	1	0	0	0	0	44	1	1	53383	2	1	12	19	25	160010	10	160000	10	160000	50	2339107	1	53373	53374	53398	33343	3	33354	160010	20	160000	20	160000	53398	53374	1	1	80021	10	9	10	10	80000	80000	10	160000	0	43	160038	1	1	38	160038	6	1	39	43	0	5022	10	16	0	6	5	53395	14	10	7	160000	10	53399	53375	53375	53395	53654
160024	53387	400	0	0	0	0	0	0	0	1	1	53383	2	1	12	19	25	160010	10	160000	10	160000	50	2332549	0	53373	53398	53398	33343	3	33378	160010	20	160000	20	160000	53374	53394	1	1	80021	10	9	10	10	80000	80000	10	160000	0	43	160000	0	78	9	160038	6	1	39	44	0	5020	3	16	0	2	3	53395	14	0	4	160000	10	53399	53399	53423	53400	53623
160024	53407	399	0	0	1	0	0	0	0	0	0	53774	2	1	1	0	25	160010	10	160000	10	160000	50	2330707	0	53369	53374	53394	33339	3	33378	160010	20	160000	20	160000	53398	53374	1	1	80021	10	9	10	10	80000	80000	10	160000	0	43	160038	0	75	44	160038	6	0	39	44	0	5020	3	16	0	3	3	53395	14	14	7	160000	10	53399	53395	53395	53375	53693
160024	53412	400	0	0	0	0	0	0	44	0	0	53383	0	1	1	19	25	160010	10	160000	10	160000	50	2332549	0	53349	53374	53374	33343	15	33422	160010	20	160000	20	160000	53398	53394	1	1	80021	10	9	10	10	80000	80000	10	160000	0	43	160038	1	58	47	160038	6	0	39	43	0	5020	3	16	0	3	3	53371	14	10	7	160000	10	53399	53375	53375	53375	53626
160024	53403	400	0	0	0	0	0	0	44	0	1	53383	0	1	1	19	25	160010	10	160000	10	160000	50	2339775	0	53349	53398	53398	33343	3	33354	160010	20	160000	20	160000	53398	53374	1	1	80021	10	9	10	10	80000	80000	10	160000	0	43	160038	0	75	47	160000	6	0	39	0	0	5020	3	16	0	3	3	53395	14	14	7	160000	10	53399	53399	53395	53375	53650
160024	53412	400	0	0	0	0	0	0	44	0	0	53383	0	1	1	16	25	160010	10	160000	10	160000	50	2339775	0	53349	53398	53398	33319	3	33378	160010	20	160000	20	160000	53374	53394	1	1	80021	10	9	10	10	80000	80000	10	160000	0	0	160000	0	70	41	160039	6	0	0	0	0	5020	3	16	0	3	3	53371	14	14	7	160000	10	53399	53375	53399	53399	53393
160024	53394	399	0	0	0	0	0	0	44	0	0	53383	2	0	12	0	25	160010	10	160000	10	160000	50	2332549	0	53373	53398	53398	33319	3	33354	160010	20	160000	20	160000	53398	53374	1	1	80021	10	9	10	10	80000	80000	10	160000	0	44	160038	0	23	42	160038	0	1	38	44	0	5020	3	16	0	3	3	53395	0	14	7	160000	10	53375	53399	53399	53375	53399
160024	53473	400	0	0	0	0	0	0	44	0	1	53383	2	0	1	16	25	160010	10	160000	10	160000	50	2335228	1	53376	53398	53400	33339	3	33357	160010	20	160000	20	160000	53628	53410	1	1	80021	10	9	10	10	80000	80000	10	160000	0	0	160038	0	73	48	160038	0	1	39	0	0	5020	3	16	0	3	3	53391	14	10	7	160000	10	53399	53375	53395	53399	53642
160024	53406	400	0	0	0	0	0	0	44	0	0	53383	0	1	12	16	25	160010	10	160000	10	160000	50	2330707	1	53374	53398	53398	33343	3	33354	160010	20	160000	20	160000	53398	53394	1	1	80021	10	9	10	10	80000	80000	10	160000	0	0	160038	0	75	41	160038	0	0	39	43	0	5020	3	16	0	3	3	53395	0	14	7	160000	10	53399	53375	53395	53375	53670
160024	53405	400	0	0	0	0	0	0	44	0	1	53383	2	1	1	19	25	160010	10	160000	10	160000	50	2339775	1	53349	53398	53394	33319	3	33354	160010	20	160000	20	160000	53398	53394	1	1	80021	10	9	10	10	80000	80000	10	160000	0	43	160039	0	82	48	160039	6	1	0	0	0	5020	3	16	0	3	3	53395	14	0	0	160000	10	53375	53375	53399	53399	53660

LDP (Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations