Firestorm: LDP (S) measurements

Code:

  ldp s0, s1, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2005	404	3	1	1	0	1	0	1	60	1	0	1	383	17	15	18	16	25	1000	1000	1000	15242	373	398	399	95	3	131	1000	2000	1000	399	389	1	1	1001	1000	1000	0	1021	20	56	1072	1	0	1	74	1053	6	1	71	44	19	1	73	1	16	1	1	395	6	6	3	1000	1000	399	405	399	418	399
2004	398	3	0	0	0	0	0	0	60	1	0	1	383	17	15	18	21	25	1000	1000	1000	15669	374	399	404	101	3	132	1000	2000	1000	398	399	1	1	1001	1000	1000	0	1000	0	58	1054	0	0	0	54	1054	6	1	54	43	0	0	73	1	16	1	1	395	6	6	3	1000	1000	399	401	399	402	399
2004	398	2	0	0	0	0	0	0	60	0	0	1	383	17	15	18	20	25	1000	1000	1000	15559	378	398	399	101	3	131	1000	2000	1000	404	404	1	1	1001	1000	1000	0	1000	0	58	1054	0	0	0	54	1054	6	1	54	43	0	0	73	1	16	1	1	395	6	6	3	1000	1000	402	399	401	401	399
2004	398	3	0	0	0	0	0	0	60	1	0	1	383	17	15	18	20	25	1000	1000	1000	15559	379	404	405	101	3	137	1000	2000	1000	405	404	1	1	1001	1000	1000	0	1000	0	58	1054	0	0	0	54	1054	6	1	54	43	0	0	73	1	16	1	1	395	6	6	3	1000	1000	397	399	399	399	399
2004	398	3	0	0	0	0	0	0	60	0	0	1	383	17	15	18	20	25	1000	1000	1000	15551	379	404	404	101	3	137	1000	2000	1000	404	404	1	1	1001	1000	1000	0	1000	0	58	1054	0	0	0	54	1054	6	1	54	43	0	0	73	1	16	1	1	395	6	6	3	1000	1000	399	400	399	402	399
2004	398	3	0	0	0	0	0	0	60	0	0	1	383	17	15	18	20	25	1000	1000	1000	15559	379	404	404	101	3	137	1000	2000	1000	404	404	1	1	1001	1000	1000	0	1000	0	58	1054	0	0	0	54	1035	6	1	35	43	0	0	73	1	16	1	1	395	6	6	2	1000	1000	390	401	399	405	399
2004	398	2	0	0	0	0	0	0	60	0	0	1	383	17	15	18	20	25	1000	1000	1000	15559	379	404	403	101	3	137	1000	2000	1000	403	404	1	1	1001	1000	1000	0	1000	0	58	1054	0	0	0	35	1054	6	1	54	43	0	0	73	1	16	1	1	395	6	6	3	1000	1000	399	399	399	399	399
2004	398	3	0	0	0	0	0	0	60	0	0	1	383	17	15	30	17	25	1000	1000	1000	15236	373	398	398	96	3	131	1000	2000	1000	398	398	1	1	1001	1000	1000	0	1020	20	57	1071	1	0	2	74	1053	6	1	72	44	19	0	73	1	16	1	1	401	6	6	2	1000	1000	390	399	399	399	399
2004	398	3	0	0	0	0	0	0	60	0	0	1	383	17	15	18	17	25	1000	1000	1000	15290	373	398	398	95	3	131	1000	2000	1000	398	398	1	1	1001	1000	1000	0	1020	20	57	1072	1	0	0	74	1053	6	1	72	44	19	1	73	1	16	1	1	401	6	6	2	1000	1000	381	399	399	399	399
2004	398	3	0	0	0	0	0	0	60	1	0	1	383	17	15	18	16	25	1000	1000	1000	15493	374	398	398	96	3	131	1000	2000	1000	398	398	1	1	1001	1000	1000	0	1020	19	56	1072	1	0	0	74	1053	6	1	72	44	19	1	73	1	16	1	1	401	6	6	2	1000	1000	391	393	409	390	399

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp s0, s1, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120201	900	0	0	0	0	0	0	0	34	0	1	0	0	0	120035	119538	109494	25	60103	40102	10001	10000	30100	10000	10000	1079566	5735888	6120869	1	120011	0	120050	120050	111897	3	112374	50100	30200	20000	10000	60200	10000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	0	0	10000	1	0	0	0	0	3210	1	135	1	1	119658	40002	9	6	8	10000	10000	40100	120048	120051	120048	120051	120048
60204	120047	899	0	0	0	1	0	0	0	1	0	0	0	0	0	120035	119494	109458	25	60100	40100	10001	10000	30100	10000	10000	1079539	5738816	6119144	1	120026	0	120050	120050	111895	3	112374	50100	30200	20000	10000	60200	10000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	3210	1	135	1	1	119655	40000	9	9	0	10000	10000	40100	120048	120048	120048	120090	120036
60204	120035	899	0	0	0	1	0	0	0	13	0	0	0	0	0	120074	119494	109443	25	60103	40102	10001	10000	30100	10062	10000	1079539	5737856	6118189	1	120026	0	120050	120047	111895	3	112374	50100	30200	20000	10000	60200	10000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	0	10000	0	0	0	0	0	3210	1	100	1	1	119655	40002	6	0	8	10000	10000	40100	120051	120036	120048	120051	120051
60204	120035	899	0	0	0	0	0	0	0	1	0	0	0	0	0	120032	119503	109455	25	60103	40102	10000	10000	30100	10000	10000	1079330	5738096	6119048	0	120026	0	120047	120035	111895	3	112416	50100	30200	20000	10000	60200	10000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	0	0	0	3210	1	135	0	1	119655	40002	6	0	0	10000	10000	40100	120051	120051	120036	120051	120051
60204	120050	899	0	0	0	1	0	0	0	1	0	0	1	0	0	120036	119503	109455	25	60100	40102	10001	10003	30100	10000	10000	1079557	5739152	6119067	1	120011	0	120035	120035	111895	3	112416	50100	30200	20000	10000	60200	10000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	3	10000	1	1	0	0	0	3210	1	135	1	1	119646	40002	0	9	8	10000	10000	40100	120051	120051	120036	120051	120051
60204	120050	899	0	0	0	1	0	0	0	0	0	0	0	0	0	120035	119494	109443	25	60100	40102	10001	10000	30100	10000	10000	1079126	5738960	6119191	0	120026	0	120050	120050	112251	3	112416	50100	30200	20000	10000	60200	10000	10000	120051	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10017	0	1	10034	0	0	91908	10029	1	1	0	0	0	3917	4	332	2	1	121661	40209	6	6	5	10000	10000	40100	122740	122546	122654	122613	122652
60204	122746	919	0	1	0	0	0	30	31	3961	2728	0	1	0	0	123012	120920	110387	1009	60463	40357	10063	10064	34780	11623	11628	1158822	5803932	6194819	1	122312	0	123029	123032	112562	445	113866	57657	35214	23296	10808	68900	11706	11672	123162	123224	35	1	50201	100	99	100	40100	10000	10000	0	100	10038	4	0	10042	0	4	117903	10048	1	1	2	0	0	3210	1	100	1	1	119655	40002	9	9	8	10000	10000	40100	123426	123527	123380	123289	123313
60204	122331	899	1	1	0	0	0	0	0	0	0	0	0	0	0	120020	119494	109443	25	60103	40102	10001	10000	30100	10000	10000	1084456	5736464	6118241	1	120026	0	120092	120053	111895	3	112416	50100	30390	20000	10000	60200	10000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	0	1	2	0	0	3210	1	135	1	1	119646	40000	9	0	5	10000	10000	40100	120036	120148	120048	120153	120036
60204	120050	899	0	0	0	0	0	0	0	1	0	0	0	0	0	120063	119494	109458	25	60100	40100	10001	10000	30100	10000	10000	1079539	5738528	6118216	1	120023	0	120035	120035	111903	3	112374	50100	30200	20000	10000	60200	10000	10000	120050	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	3210	1	108	1	1	119647	40000	9	0	0	10000	10000	40100	120051	120051	120036	120051	120036
60204	120050	899	0	0	0	1	1	0	0	1	0	0	0	0	0	120040	119494	109458	25	60103	40102	10001	10000	30100	10053	10050	1079539	5735888	6121668	1	120011	0	120035	120047	111895	3	112416	50100	30200	20000	10000	60200	10000	10000	120173	120047	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	3210	1	108	1	1	119655	40002	9	9	8	10000	10000	40100	120051	120051	120051	120036	120036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	23	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120047	899	0	1	0	1	1	0	0	120020	119480	109455	25	60013	40012	10001	10000	30010	10000	10000	1079809	5735888	6125581	0	0	120023	120047	120047	111915	3	112565	50010	30020	20000	10000	60020	10000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	0	3140	0	4	99	3	3	119665	40002	6	0	5	10000	10000	40010	120048	120097	120048	120048	120048
60024	120035	899	0	0	0	0	0	0	0	120032	119480	109443	25	60013	40012	10001	10000	30010	10000	10000	1079809	5735888	6125581	0	5	120023	120047	120047	111915	3	112444	50010	30020	20000	10062	60020	10000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	0	3140	0	4	99	3	3	119665	40002	6	0	5	10000	10000	40010	120036	120048	120048	120046	120048
60024	120047	899	0	1	1	1	0	0	0	120020	119480	109455	25	60013	40012	10001	10000	30010	10000	10000	1079809	5735293	6125581	0	5	120023	120047	120047	111903	3	112444	50010	30020	20000	10000	60020	10000	10000	120047	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	0	3140	0	2	94	3	3	119650	40002	6	6	0	10000	10000	40010	120036	120048	120048	120048	120036
60024	120047	899	0	0	1	1	0	0	0	120020	119489	109455	25	60013	40012	10001	10000	30010	10000	10000	1079809	5735293	6125581	0	5	120023	120047	120047	111915	3	112444	50010	30020	20000	10000	60020	10000	10000	120047	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	0	3140	0	3	99	2	3	119665	40002	6	6	5	10000	10000	40010	120048	120048	120036	120048	120048
60024	120035	899	0	1	1	0	0	0	0	120032	119480	109455	25	60013	40012	10001	10000	30010	10000	10000	1079809	5735888	6125581	1	5	120023	120047	120035	111915	3	112437	50010	30020	20000	10000	60020	10000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	0	0	0	0	0	0	3140	0	3	99	3	2	119650	40000	0	6	5	10000	10000	40010	120048	120048	120036	120048	120048
60024	120047	899	0	0	0	0	1	0	0	120032	119489	109455	25	60013	40012	10001	10000	30010	10000	10000	1079809	5735888	6125581	0	5	120023	120047	120047	111903	3	112444	50010	30020	20000	10000	60020	10000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	0	1	0	0	0	0	3140	0	3	99	4	4	119665	40002	6	6	5	10000	10000	40010	120048	120048	120048	120048	120048
60024	120047	900	0	0	0	0	0	0	0	120020	119480	109455	25	60013	40012	10001	10000	30010	10000	10000	1079809	5735293	6125581	0	5	120023	120035	120047	111915	3	112444	50010	30020	20000	10000	60020	10000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	1	0	0	10000	1	0	0	0	0	0	3140	0	2	99	3	3	119665	40002	6	6	0	10000	10000	40010	120048	120048	120048	120036	120048
60024	120047	899	0	0	0	1	0	0	0	120020	119480	109455	25	60013	40012	10001	10000	30010	10000	10000	1079809	5735888	6125581	0	5	120023	120047	120047	111915	3	112444	50010	30020	20000	10000	60020	10000	10000	120047	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	3	10000	1	1	0	0	0	0	3140	0	3	99	3	2	119665	40000	6	6	5	10000	10000	40010	120048	120036	120048	120036	120048
60025	120066	899	0	1	1	16	1	0	0	120032	119480	109455	25	60013	40012	10001	10000	30010	10000	10000	1079809	5735888	6124344	0	5	120023	120035	120035	111903	3	112444	50010	30020	20000	10000	60020	10000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	0	10000	1	1	0	0	0	0	3140	0	3	94	3	2	119665	40002	6	6	5	10000	10000	40010	120048	120052	120048	120048	120048
60024	120047	899	0	0	0	1	0	0	0	120032	119480	109455	25	60013	40010	10001	10000	30010	10000	10000	1079769	5735293	6125581	0	5	120023	120047	120047	111915	3	112444	50010	30020	20000	10000	60020	10000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	0	10000	1	1	0	0	1	0	3140	0	3	99	3	2	119665	40002	6	6	5	10000	10000	40010	120048	120048	120048	120048	120048

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp s0, s1, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120061	1111	0	1	1	1	1	0	0	6	1	0	0	120034	119494	109455	25	60103	40102	10000	10000	30100	10000	10000	1079539	5735888	6121387	1	120026	120047	120051	111895	3	112375	50100	30200	20000	10000	60200	10000	10000	120056	120038	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	2	1	10000	10	0	10000	1	1	1	0	0	3249	4	108	4	5	119655	40002	9	0	8	10000	10000	40100	120036	120048	120048	120051	120051
60204	120050	1039	0	0	0	0	0	1	1	1	0	0	0	120020	119494	109458	25	60103	40100	10001	10000	30100	10000	10000	1079126	5736035	6120646	0	120026	120048	120050	111895	3	112421	50100	30200	20000	10000	60200	10063	10000	120052	120048	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	0	1	0	0	0	3210	4	135	4	4	119646	40000	6	6	8	10000	10000	40100	120050	120049	120048	120048	120048
60204	120035	964	0	0	0	0	0	0	1	1	0	0	0	120035	119538	109505	25	60100	40102	10001	10000	30100	10000	10000	1079330	5735888	6120605	0	120023	120047	120035	111909	3	112508	50100	30200	20000	10000	60200	10000	10000	120047	120035	2	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	10000	1	0	0	0	0	3210	4	108	4	4	119646	40002	6	6	5	10000	10000	40100	120051	120051	120048	120051	120036
60204	120047	931	0	0	0	0	0	0	0	1	0	0	0	120032	119494	109443	25	60100	40102	10000	10000	30100	10000	10000	1079126	5735888	6121652	1	120082	120053	120035	111903	3	112421	50100	30200	20000	10000	60200	10000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	0	1	0	0	0	3210	4	108	4	4	119657	40002	9	6	8	10000	10000	40100	120051	120085	120090	120041	120051
60204	120035	899	0	0	0	0	0	0	1	1	0	0	0	120035	119538	109458	25	60103	40100	10001	10000	30100	10000	10000	1079539	5737856	6120238	1	120026	120050	120050	111895	3	112416	50100	30200	20128	10000	60200	10000	10000	120052	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	4	0	10000	0	1	0	0	0	3238	4	100	4	4	119657	40002	9	6	8	10000	10000	40100	120051	120051	120036	120051	120051
60204	120088	899	0	0	0	0	0	0	0	0	0	1	0	120035	119494	109458	25	60103	40102	10001	10000	30100	10000	10000	1079330	5738864	6119714	1	120026	120050	120050	111881	3	112374	50100	30200	20128	10000	60200	10000	10000	120050	120047	2	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	1	0	0	0	0	3210	4	100	4	4	119655	40002	9	6	0	10000	10000	40100	120051	120036	120036	120051	120051
60204	120050	899	0	0	0	0	0	0	0	10	0	0	0	120035	119539	109483	25	60100	40102	10001	10000	30100	10000	10000	1079126	5739491	6118373	0	120026	120050	120050	111895	3	112416	50100	30200	20000	10000	60200	10000	10000	120050	120096	1	1	50202	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	10000	0	0	0	0	0	3210	4	135	4	4	119655	40002	0	6	0	10000	10000	40100	120051	120051	120036	120051	120051
60204	120050	899	0	0	0	0	0	0	0	1	0	1	0	120035	119494	109455	25	60100	40100	10001	10000	30100	10000	10000	1079539	5735293	6120747	0	120026	120035	120035	111895	3	112416	50100	30200	20000	10064	60200	10000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10002	46	3	10000	0	0	0	0	0	3210	4	108	4	4	119646	40000	6	6	5	10000	10000	40100	120058	120051	120051	120038	120050
60204	120050	899	0	0	0	0	0	0	0	1	0	1	0	120020	119503	109455	25	60103	40102	10001	10000	30100	10000	10000	1079539	5739395	6119044	0	120023	120050	120035	111895	3	112416	50100	30200	20000	10000	60200	10000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	3	10000	0	1	0	0	1	3210	4	100	4	4	119655	40002	9	6	8	10000	10000	40100	120051	120051	120036	120051	120051
60204	120047	899	0	0	0	0	0	0	0	1	0	0	0	120035	119538	109458	25	60103	40102	10001	10000	30100	10000	10000	1079539	5735293	6121339	0	120026	120050	120050	111895	3	112374	50100	30200	20000	10000	60200	10000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	0	10000	0	0	10000	0	1	0	0	0	3210	4	135	4	4	119657	40000	6	6	0	10000	10000	40100	120036	120049	120048	120054	120051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120057	900	1	0	1	1	0	1	1	1	0	0	367	0	1	0	0	1	120042	119484	109449	25	60016	40014	10002	10000	30010	10000	10000	1079870	5735593	6123500	0	120033	0	120041	120057	111925	0	33	112488	50010	30020	20000	10000	60020	10000	10000	120041	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	3	0	10001	0	0	2	1	10000	1	1	1	1	1	0	3140	9	99	9	4	119678	40004	10	10	9	10000	10000	40010	120058	120058	120061	120058	120058
60024	120041	899	1	0	0	1	0	1	0	1	0	0	904	0	1	0	0	0	120026	119490	109464	25	60013	40014	10002	10000	30010	10000	10000	1079915	5736518	6123500	1	120033	0	120057	120057	111928	0	3	112454	50010	30020	20000	10000	60020	10000	10000	120060	120041	1	1	50021	10	9	10	40010	10000	10000	1	10	10001	1	0	10001	0	0	1	1	10000	0	1	1	1	1	0	3140	5	99	5	7	119659	40002	10	10	0	10000	10000	40010	120058	120058	120042	120042	120061
60024	120057	899	1	0	0	1	0	0	0	0	0	0	257	0	1	0	0	1	120026	119493	109464	25	60013	40014	10002	10000	30010	10000	10000	1079942	5736374	6126051	0	120036	0	120060	120060	111928	0	3	112454	50010	30020	20000	10000	60020	10000	10000	120057	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10001	0	0	0	1	10000	1	1	1	1	1	0	3140	5	99	8	6	119681	40004	10	0	9	10000	10000	40010	120058	120058	120061	120061	120058
60024	120057	899	1	0	1	1	0	0	0	0	0	0	470	0	1	0	0	1	120045	119493	109464	25	60016	40012	10002	10000	30010	10000	10000	1079870	5736374	6126051	1	120017	0	120057	120041	111925	0	3	112454	50010	30020	20000	10000	60020	10000	10000	120057	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10001	0	1	1	1	10000	1	1	1	1	1	0	3140	5	99	6	5	119675	40004	0	10	12	10000	10000	40010	120058	120058	120058	120058	120058
60024	120041	900	1	0	0	0	0	0	1	1	0	0	223	0	1	0	0	1	120042	119490	109449	25	60016	40014	10002	10000	30010	10000	10000	1079915	5736374	6126051	0	120033	0	120041	120041	111925	0	3	112454	50010	30020	20000	10000	60020	10000	10000	120057	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10002	0	0	1	1	10000	1	1	1	1	0	0	3140	5	99	7	5	119675	40004	10	10	0	10000	10000	40010	120058	120061	120058	120058	120061
60024	120057	899	1	0	0	0	0	0	0	0	0	0	256	0	1	0	0	0	120026	119490	109467	25	60016	40014	10002	10000	30010	10000	10000	1079942	5736518	6126051	1	120017	0	120057	120057	111925	0	3	112438	50010	30020	20000	10000	60020	10000	10000	120057	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	1	1	10002	0	0	0	10	10000	1	1	1	1	1	0	3140	4	99	5	4	119659	40004	10	10	9	10000	10000	40010	120058	120058	120061	120058	120061
60024	120057	899	1	0	1	1	0	1	0	0	0	0	473	0	1	0	0	0	120042	119490	109467	25	60016	40014	10002	10000	30010	10000	10000	1079942	5736518	6126051	0	120017	0	120057	120057	111909	0	3	112438	50010	30020	20000	10000	60020	10000	10000	120057	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	0	10001	0	0	0	1	10000	1	1	1	1	1	0	3140	6	99	4	5	119675	40002	10	0	0	10000	10000	40010	120044	120058	120058	120058	120042
60024	120074	900	1	0	1	0	0	1	0	0	0	0	1	0	0	0	0	1	120042	119490	109464	25	60016	40014	10001	10000	30010	10000	10000	1079915	5736374	6126051	0	120033	0	120057	120041	111909	0	3	112454	50010	30020	20000	10000	60020	10000	10000	120041	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10002	0	1	2	1	10000	1	1	1	1	0	0	3140	4	99	6	5	119675	40004	0	10	0	10000	10000	40010	120042	120042	120058	120042	120058
60025	120041	899	1	0	1	0	0	1	0	0	0	0	2	0	0	0	0	1	120042	119490	109467	25	60013	40012	10002	10000	30010	10000	10000	1079870	5736374	6126051	0	120017	0	120057	120057	111925	0	3	112454	50010	30020	20000	10000	60020	10000	10000	120057	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10001	0	49	2	1	10000	0	1	1	1	0	0	3140	4	108	6	5	119675	40004	10	10	0	10000	10000	40010	120058	120058	120058	120042	120058
60024	120057	900	1	0	1	0	0	0	0	0	0	0	2	0	1	0	0	1	120042	119484	109449	25	60016	40014	10002	10000	30010	10000	10000	1079942	5736518	6126051	0	120017	0	120057	120041	111925	0	3	112438	50010	30020	20000	10000	60020	10000	10000	120057	120057	1	1	50021	10	9	10	40010	10000	10000	1	10	10002	2	1	10002	0	0	1	1	10000	1	1	1	1	1	0	3140	3	99	5	5	119659	40004	0	10	9	10000	10000	40010	120061	120058	120058	120061	120042

Test 4: throughput

Count: 8

Code:

  ldp s0, s1, [x6]
  ldp s0, s1, [x6]
  ldp s0, s1, [x6]
  ldp s0, s1, [x6]
  ldp s0, s1, [x6]
  ldp s0, s1, [x6]
  ldp s0, s1, [x6]
  ldp s0, s1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160205	26733	200	0	0	0	0	0	41	1	0	1	26707	2	18	18	11	25	80100	100	80000	100	80000	500	1173183	0	26697	26722	26722	6645	3	6665	80100	200	160000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	0	80000	0	0	39	80035	6	0	35	43	0	5110	2	16	2	2	26724	10	6	4	80000	80000	100	26728	26728	26728	26723	26723
160204	26727	200	0	0	0	0	1	41	0	0	0	26712	2	12	18	18	25	80100	100	80000	100	80000	500	1168880	0	26702	26707	26727	6650	3	6801	80100	200	160000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	43	80039	0	0	35	80035	6	1	35	43	0	5110	2	16	2	2	26724	0	6	4	80000	80000	100	26723	26728	26723	26723	26728
160204	26707	200	0	0	0	0	0	0	0	0	2	26716	2	0	12	16	25	80100	100	80000	100	80000	500	1174628	0	26702	26727	26727	6630	3	6685	80100	200	160000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80039	0	0	39	80039	6	0	35	43	0	5110	2	16	2	2	26724	0	6	4	80000	80000	100	26728	26728	26728	26723	26723
160204	26727	200	0	0	0	0	0	41	0	0	1	26822	2	0	12	12	25	80100	100	80000	100	80000	500	1173183	0	26702	26707	26707	6650	3	6685	80100	200	160000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80039	0	0	0	80039	6	1	35	39	0	5110	2	16	2	2	26719	10	6	4	80000	80000	100	26723	26728	26728	26723	26728
160204	26728	200	0	0	0	0	0	45	0	0	1	26701	2	12	12	16	25	80100	100	80000	100	80000	500	1168880	1	26702	26722	26727	6650	3	6665	80100	200	160000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80039	0	0	0	80039	6	0	35	0	0	5110	2	16	2	2	26723	10	10	4	80000	80000	100	26731	26708	26708	26723	26723
160204	26710	200	0	0	0	0	0	41	0	0	2	26702	0	12	12	12	25	80100	100	80000	100	80000	500	1174628	0	26682	26727	26707	6650	3	6680	80100	200	160000	200	80000	26707	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80039	0	0	0	80035	6	0	0	43	0	5110	2	17	2	2	26724	8	6	4	80000	80000	100	26728	26708	26728	26728	26728
160204	26727	200	0	0	0	0	0	45	1	0	0	26725	2	12	0	16	25	80100	100	80000	100	80000	500	1168880	0	26682	26707	26727	6645	3	6680	80100	200	160000	200	80000	26707	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80035	0	0	39	80039	6	1	0	42	0	5110	2	16	2	2	26724	0	6	2	80000	80000	100	26728	26728	26723	26723	26708
160204	26707	200	0	0	0	0	0	41	1	0	1	26720	2	0	18	16	25	80100	100	80000	100	80000	500	1170529	0	26689	26732	26732	6654	3	6690	80100	200	160000	200	80000	26732	26732	1	1	80201	100	99	100	100	80000	80000	0	100	80021	19	42	80058	0	1	59	80038	6	1	57	42	19	5110	2	16	2	2	26729	6	0	2	80000	80000	100	26723	26728	26728	26728	26728
160204	26722	200	0	0	0	0	0	41	0	0	2	26716	2	18	18	16	25	80100	100	80000	100	80000	500	1174628	0	26702	26722	26727	6650	3	6685	80100	200	160000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	39	80039	0	0	39	80039	6	1	36	43	0	5110	2	16	2	2	26724	9	0	2	80000	80000	100	26715	26733	26733	26715	26733
160204	26732	200	1	1	1	0	0	65	0	0	2	26724	2	18	18	16	25	80100	100	80000	100	80000	500	1167371	0	26707	26732	26732	6654	3	6690	80100	200	160000	200	80000	26732	26732	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	42	80035	0	0	0	80035	6	0	35	39	0	5110	2	16	2	2	26724	10	10	2	80000	80000	100	26723	26708	26728	26723	26728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160025	26735	200	0	0	41	1	0	1	26721	2	18	0	12	25	80010	10	80000	10	80000	50	1175837	1	0	26685	26722	26707	6668	0	3	6687	80010	20	160000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	80035	0	0	0	35	80035	6	1	35	39	0	0	5020	0	0	4	16	0	4	5	26719	6	6	2	80000	80000	10	26723	26723	26723	26723	26723
160024	26722	200	0	0	41	0	0	1	26833	2	18	18	12	25	80010	10	80000	10	80000	50	1170107	1	0	26682	26722	26722	6668	0	3	6702	80010	20	160000	20	80000	26722	26707	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80035	0	0	0	36	80035	0	1	35	39	0	0	5020	0	0	7	16	0	5	5	26704	0	6	2	80000	80000	10	26723	26723	26723	26723	26723
160024	26722	200	0	0	41	1	0	1	26721	0	18	0	2	25	80010	10	80000	10	80000	50	1170107	1	0	26684	26890	26722	6668	0	3	6702	80010	20	160000	20	80000	26722	26707	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	80000	0	0	0	35	80035	6	1	35	39	0	0	5020	0	0	5	16	0	5	5	26719	6	6	2	80000	80000	10	26723	26723	26723	26723	26723
160024	26722	200	0	0	41	1	0	1	26838	2	18	18	12	25	80010	10	80000	10	80000	50	1170107	1	0	26697	26707	26722	6668	0	3	6702	80010	20	160000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	80035	0	0	0	35	80000	6	1	35	39	0	0	5020	0	0	5	16	0	4	5	26704	6	6	2	80000	80000	10	26723	26723	26723	26723	26723
160024	26722	199	0	0	0	0	0	0	26787	2	18	18	0	25	80010	10	80000	10	80000	50	1168754	1	0	26682	26722	26722	6668	0	3	6702	80010	20	160000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	80000	0	0	0	35	80035	6	1	35	39	0	0	5020	0	0	6	16	0	3	5	26719	0	6	2	80000	80000	10	26723	26723	26723	26723	26723
160024	26722	200	0	0	0	1	0	0	26692	2	18	18	12	25	80010	10	80000	10	80000	50	1168880	1	0	26697	26722	26722	6653	0	3	6702	80010	20	160000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	1	10	80000	0	39	80035	0	0	0	35	80035	6	1	35	39	0	0	5020	0	0	5	16	0	5	5	26719	6	6	2	80000	80000	10	26723	26708	26723	26723	26723
160024	26722	200	0	0	41	0	0	1	26779	2	0	18	12	25	80010	10	80000	10	80000	50	1170107	1	0	26697	26722	26722	6668	0	3	6702	80010	20	160000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	80035	0	0	0	35	80035	0	0	0	0	0	0	5020	0	0	6	16	0	5	4	26704	6	6	2	80000	80000	10	26723	26723	26723	26723	26723
160024	26722	200	0	0	0	0	0	1	26707	2	18	18	0	25	80010	10	80000	10	80000	50	1170107	1	0	26697	26722	26707	6668	0	3	6687	80010	20	160000	20	80000	26722	26707	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	80035	0	0	0	0	80000	6	1	35	39	0	0	5020	0	0	5	16	0	5	4	26704	6	6	2	80000	80000	10	26723	26723	26723	26723	26708
160024	26707	200	0	0	41	1	0	0	26693	0	18	18	12	25	80010	10	80000	10	80000	50	1175837	1	0	26697	26722	26725	6668	0	3	6702	80010	20	160000	20	80000	26707	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80035	0	0	0	0	80035	6	1	35	39	0	0	5020	0	0	6	16	0	6	5	26719	6	0	2	80000	80000	10	26723	26723	26708	26821	26708
160024	26722	200	0	0	41	1	0	0	26713	2	0	0	12	25	80010	10	80000	10	80000	50	1170107	1	0	26697	26722	26722	6668	0	3	6702	80010	20	160000	20	80000	26722	26722	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	39	80035	0	0	0	38	80035	6	1	35	39	1	0	5020	0	0	5	16	0	5	4	26720	6	0	2	80000	80000	10	26723	26723	26723	26708	26723

LDP (S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations