Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDP (post-index, D)

Test 1: uops

Code:

  ldp d0, d1, [x6], #0x10
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0f1e202223243a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb5b6bbl1d cache miss ld nonspec (bf)c2c3cfd5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
200510528000073401000161025007315252000100010001000100052828458241101510401040699377320002000200010401040111001100010000102401661027412016001005640140647321611103701000222210001000100010411041104110411041
20041040800004325100112102513135132520001000100010001000528324582411015104010406993773200020002000104010401110011000100011043005410261013616001035520344347311611103701000182710001000100010411041104110411041
200410408000045371000121025180001325200010001000100010005282445824010151040104069937732000200020001040104011100110001000110408027103250230001007480048007311611103701000181410001000100010411041104110411041
2004104080000462610000102500657252000100010001000100052832458241101510401040699377320002000200010401040111001100010000103403521031203401441034440544037311611103701000262110001000100010411041104110411041
2004104080000422510001210252143713252000100010001000100052828458241101510401040699377320002000200010401040111001100010000103500391030703201641033450552047311611103701000352710001000100010411041104110411041
200410408000046351000010251307417252000100010001000100052824458241101510401040699377320002000200010401040111001100010000103501451021513402031031460052037311611103701000192010001000100010411041104110411041
2004104070000513200011210252110410252000100010001000100052816458240101510401040699377320002000200010401040111001100010000103501441023703501481034441148347311611103701000262110001000100010411041104110411041
20041040800003712000001025000016252000100010001000100052828458241101510401040699377320002000200010401040111001100010000103502621027603201231036410040037311611103701000222610001000100010411041104110411041
20041040701004514000116102570039252000100010001000100052820458241101510401040699377320002000200010401040111001100010000103501511028803501481036480056047311611103701000282310001000100010411041104110411041
20041040700017340100141025350031725200010001000100010005283245824110151040104069937732000200020001040104011100110001000010260134104712046014111058530452047311611103701000252310001000100010411041104110411041

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp d0, d1, [x6], #0x10
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1574

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f202224293a3e3f404d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3cfd5map dispatch bubble (d6)daddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
6021412118591310001000213802238101224146812171022021212862570442502301012010000401001000010000107290446316074628250112160701213101218471136543114093601003020020000100006020020000100001215051213985150201100991004010010000100000100124268377211812049403112241718631212411961112015321018301112113250182404760341100001000050100121550121492121487121907121545
60204121644910100000002393022571011201328121766221112130725703675029410125100004010010000100001078576461360246312341121389012147512203811364331141026010030200200001000060200200001000012175712175311502011009910040100100001000001001240693722057120434021122394623301240211701140033210183011121449502061018786779100001000050100121471121621121731121911121940
602041214909101000000023600225310133611561215442203121364257047850306101251000040100100001000010768284599573463297411216780121780121748113812311382660100302002000010000602002000010000121743121875115020110099100401001000010000010012401837820631204939810324322363121242296195002321018301112145150172937887703100001000050100121436121577121473121970121792
6020412197591110001140270902245101376129612182622291214572570391503041008410000401001000010000107757946180934640347112144201217751218541137113113924601003020020000100006020020000100001217171216761150201100991004010010000100000100124148377210112068395110242078324124001170124000321028301212119850200892906725100001000050100121613121263121613121649121714
60204121680909100000003102022621015681132121720227512108725704485030010123100004010010000100001075264461146446378961121442012154212154211353631145516010030200200001000060200200001000012133212159511502011009910040100100001000001001240383772063120693986824112443121241870052000321018301112148150248894995906100001000050100121534121568121716121646121549
60204121574913110010202718023051013281232120797219112090425704245032610098100004010010000101581075556461081846421301121768012146412097911336443114211601003020020000100006020020000100001219791218621150201100991004010010000100000100124108376211412024387111243426630012428930111001325518301212139150252830896745100001000050100121924122113121709121468122022
60204121733908100000002803022211014321124121748220212131425704125033010114100004010010000100001077542460346946423651121683012181812172011360231140206010030200200001000061184200001000012153712177411502011009910040100100001000011001240983772041120813961092408118313412400115099010321018301112114350250483797724100001000050100121885121289122125121810121961
602041217749101000000029710224510142414241217692204121412257038850316101141000040100100001000010739754604917463606111216930121591121812113803311416660100302002000010000606902000010000121218121776115020110099100401001000010000010012422933520961206940011224312901149612442101087030321018301112115550196839911800100001000050100121617121704121404121479121733
6020412155191010000000231802249101272130812135022271214522570346503221010910000401001000010000107712945993674648679112177501215011217351135683113820609853020020000100006020020000100001215271214294150201100991004010010000100000100124288331207812014368110242156330124121110106000321018301112126650234789981678100001000050100121619121725121691121633121592
6020412157191310010000214335222561014481116121417220512105425704425031610109100004010010000100001075937460902746376391121642012146812175211356031139706010030200200001000060200200001000012145912157511502011009910040100100001000001001239783612062120173971092424188315124289211140003210183011121150502448771008655100001000050100121697121520121555121582121622

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1655

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f1e2022293a3e3f4043494d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
6003412100691020020018312256114004216121787218400121270257031950222101101000040010100001000010781124613024463364701121471012176712189511365731137956001030020200001000060020200001000012176412146511500211091040010100001000001012489163782051119914031082413232330124361190830200031400578022121400502141024893659100001000050010121601121690121514121720121516
60024121617911330000254322721140833361217172189001214192570232502141013410000400101000010000107511546129084649936001215280121788121860113453311414660010300202000010000603162000010000121574121480115002110910400101000010000010124272438120661208336010624346031512396107298034003142027802212116950222886749646100001000050010121707121737121569121363121891
6002412182891122000025372216114643300121519225900121132257031650216101311000040010100001000010749984608949464236500121856012136112159711393831140026001030020200001000060020200001000012161012144311500211091040010100001000001012432173732063120223601142425186317124181081125100003140027802212152450234876929634100001000050010121734121643121690121496121779
600241215669113300012305225711416414012161122070012150025703615025410130100004001010000100001075853461152246477060012187401217581217491137763114044600103002020000100006002020000100001217061218311150021109104001010000100001101242540341211412005407110242860319124041000107000003140027802212110450226930686662100001000050010121535121418121510121591121554
60024121600911303301249422841128832881214892216001213664970292502041010410000400101000010000107870646088244634087001215250121625121486113762311405760010300202000010000600202000010000121625121609115002110910400101000010000010124221737020711207740610924142926241239510301360360003140027803412130750268882934821100001000050010121542121945121565121684121919
6002412181191250000125782257112245264121549220300121063257035250286101401000040010100001000010794354624185464232411121435012174012180911368731142296001030020200001000060020200001000012157212187211500211091040010100001000001012419333932053121034031102426523181240711901262102003140027802212115350244958702702100001000050010121594121650121700121624121606
600241220229155500012356225611368596121941226100121737257035850278101191000040010100001000010777254604433463949101121928012180412194511385731139556001030020200001000060020200001000012196312162611500211091040010100001000011012423343782069120993621442435246321124091150114100003140027802212139550210806848738100001000050010121757121761121617122155122005
6002412179991460000125072258112163220121722223540121343257037050218100921000040010100001000010779144604288462948801121667012140612168111374931139106001030020200001000060020200001000012165312170111500211091040010100001000001012414203852113120543551042422745461239813011130000031401427812212137850192856644659100001000050010121591121712121815121353121767
6002412165591222200022502260113842220121875225500121478257040950216101281000040010100001000010763304608618462797901121470012156312144411359631141226025830020200001000060020200001000012141412167311500211091040010100001000001012436243482106120844021862424244321124171040108000003140047802212133550222919802765100001000050010121543121543121520121560121717
6002412154191233000021472251114242180121453227500121282257036450094101111000040010100001000010763394606252464730700121566312136412157111367431137756001030020200001000060020200001000012159312142711500211091040010100001000001012444938620981199436818524305431812416960109001003140027802212144950238854818739100001000050010121438121819121571121739121720

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp d0, d1, [x6], #0x10
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1693

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f20222324293a3e3f4043494d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9e9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
60214121354910110011002169022361001240130012183122210012131725704935034410100100004010010000100001075055460627846284880121636012170712184511355431144576010030200200001000060200200001000012181412182411502011009910040100100001000000100124001395203612014401115237954233012399943820000032101831112151950224944992759100001000050100121980121805121940121996121943
602041217929123000010022760226010011683284121869225500121548257037650328100991000040100100001000010802934613027464154111214610121532121815113794311428560100302002000010000602002000010000121912121593115020110099100401001000010000001001241217388209412007407109241650832112391116212000000321018311121371502247951006764100001000050100121728121777121490121756121734
6020412187491120000100234002241100139211001215862193101212782570448503581011410000401001000010000107811145957534637126012199801217411219041138893114151601003020020000100006020020000100001216301219063150201100991004010010000100000010012412938920511202442111124145063361240511109900000321018311121454502441004899730100001000050100121824121846121640121710121587
6020412152990810100100240202215100142404281219382212101210142570379503181011110000401001000010000107641945979604630913012171401215641217031136653114161601003020020000100006020020000100001214511218621150201100991004010010000100000010012430137920561199044510924066203051243610801150020032101831112121450228844878577100001000050100121678121446121859121733121493
60204121493910100001002149022291001416011212148722091012129325703975032410107100004010010000100001076682460926846500480121690012189412171811361831132376010030200200001000060200200001000012178612172711502011009910040100100001000000100124041386210012010413110241650431912414811960000032101831112137550200856975570100001000050100121646121597121705121627121511
6020412164691310000100241502234100136012881215582194001213382570418502921011010000401001000010000107520346081474637060012160001214751215071133013114110601003020020000100006020020000100001218631216301150201100991004010010000100000010012432134620461198840411324084943211241612411200200032101831112124150222812733747100001000050100121879121677121415121544121728
602041217469111010010023690226710014080192121799219410121229257044550292101191000040100100001000010763624615810464464201216470121572121416113624311383660343302002000010000602002000010000121848121606115020110099100401001000010000001001240813922048120154191072414504318124158641040100032101831112156750216917707650100001000050100121920121589121407121597121638
602041219689132200010025300222710014241280121692218710121360257046050354101151000040100100001000010768914610469463842201219773121423121716113385311402260100302002000010000602002000010042121355121663115020110099100401001000010000001001239924052040119864081092420524319123909901180000032103309221228205053510851110903100001000050100124765125118125041124766124394
602041246939331100012928726125522166100165602521212302201101236365307085750542102181004344111111491090111445714675816469465801244170125146123450114826268115315649613377022260109426730422346109751250071237662915020110099100401001000010000001001240810554189511811569110239852216857123981500152040003848283161235425045211241250911100001000050100124737121665121575122015121657
6020412301891822000100242002205100218411881218482202101218612570479503341009610000401001000010000107908746079714626161112209501218591217711135653114175601003020020000100006020020000100001216011220471150201100991004010010000100000010012424944520591201040211124402923251241912641091200032101831112123150252829778783100001000050100121608121792121776121470121735

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1583

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f191e2022293a3e3f4043494d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3cfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
600341211889141001002395224411624115212160022011312139625702775022410104100004001010000100001077348460992846493930121541012153412156011372603114199600103002020000100006002020000100001212941217841150021109104001010000100000101238913352052119394061102422562307124321154105000314102782212108650210825757820100001000050010121622121524122079121696121790
60024121536911101000239822361146402281214482164401214712570394502681011410000400101000010000107850046159264632469012143901218531214181138310311398460010300202000010000600202000010000121662121573115002110910400101000010000010124083395206112012411105241453831912424115094010314102782212121050104699481862100001000050010121852121564121532121619121482
6002412137091210000024532232113921676121622221003121353257035550240101191000040010100001000010767364607358464740601216570121638121497113675031141686001030020200001000060020200001000012159012170811500211091040010100001000001012416139120581192647410924044943061240812141150103141022722121397500404221003645100001000050010121668121491121645121344121441
60024120859911101000243321991136012481210302272401213162570274502601008010000400101000010000107331646154964602663012164701207631214601134280311439860010300202000010000600202000010000121372121826115002110910400101000010000010124193394205212008411118239748833012411572119040314102782212142650194814904648100001000050010121842121423121996121583120725
60024121609913100000236123791125601881216962258001214082570328502341012010000400101000010000107763646167654641249012137401218361210681127330311393960010300202000010000600202000010000121536121496115002110910400101000010000010124152441205012054465107242254231412475950129020314102782212042950244321808704100001000050010121052121502121828121643121688
600241217119111010002557230911456025212145421924312131525703615019010057100004001010000100001070760461886746255610120903012180912178711362503113958600103002020000100006002020000100001208791217251150021109104001010000100000101241813822044119904101102409508303124131141106010314102782212138750084785853626100001000050010121840120974121720121851121386
600241220029101100002421224811616021612161421890012113125703735012410111100004001010000100001077204460652746530480121690012161312147511399203113316600103002020000100006026420000100001217921215531150021109104001010000100000101242394212073120124161082384494332124191181101010314103782212119150098700783327100001000050010121547120861120721121651121259
60024121827913101000242022311143202161214972185101204382570352502301004810000400101000010000107575946160524635513012184601213641214261134570311332660010300202000010000600202000010000121435121757115002110910400101000010000010123872382205712004413103247251030412423105094020314102782212129250218374360728100001000050010121346120596121599121748121581
60024121553911101000239022381137601521216482256201212242570346502121011710000400101000010000107872546131824634536012077201212181216031133760311377360010300202000010000600202000010000120786121527115002110910400101000010000010123911383204412007406109242273431612429941112000314102782212118150200837899643100001000050010121718121530121677121424122016
60024121497913110000243921931128801681215352223301212202570319502481010610000400101000010000107775346016724644905012088301208191210111133700311390560010300202000010000600202000010000121656121760115002110910400101000010000010124229448197711941491108242425829912428107058000314122782212163850266789835849100001000050010121077121557121805121580121930

Test 4: throughput

Count: 8

Code:

  ldp d0, d1, [x6], #0x10
  ldp d0, d1, [x7], #0x10
  ldp d0, d1, [x8], #0x10
  ldp d0, d1, [x9], #0x10
  ldp d0, d1, [x10], #0x10
  ldp d0, d1, [x11], #0x10
  ldp d0, d1, [x12], #0x10
  ldp d0, d1, [x13], #0x10
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3768

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f2022293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3cfd5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16021430085225202000098680227221424578403023222601769988162077251602148022880000801008000040088513360511136301443009029995100840310173160100200160000200160000302263008711802011009981001008000080000010082418412250349282943234910823903743402847897481272783335519035110216223032927801233413411038000080000801003014730197304003043130202
16020430281225500000010392022602117670852302752156197919825184325160225802188000080100800004009861350408011930260302453026910163031011016010020016000020016000030288302241180201100991510010080000800000100824194322513153826992372113241861632928470470595262429933702511021622302202780124315298768000080000801003028529999301073016730127
160204302172263100000100240232421112828803022821781537187991846251602098023680000801008000040109613350430122300923012730113102050310052160100200160000200160000302272999911802011009914100100800008000001008242132222631698249923261102411642288984636676104260729561902511021622300971880148298364938000080000801003014430107302723006030143
160204301282264001000100070228421144806003023822371557977911783251602278022580000801008000040096713373420128301103017830164101661731001616010020016000020016000030266302121180201100999100100800008000001008243729225431568216423511132396348312984552618104230515561902511021622302751580136259331778000080000801003006930346308503033230410
1602043023022633000009847021932132877988300262190122853792188425160228802358000080100800004010491331494013130147301263018099210310023160100200160000200160000302023003511802011009912100100800008000001008242029223229778273523731122432344308784785719128125728841934511021622302212080108348272778000080000801003036430101302683013930253
160204300282263000000904902202214488610763012323341567847061818251602198023480000801008000040107413322070140300983014830169101440310203160100200160000200160000301803027111802011009910100100800008000001008244229227027788226723541162396608261884864713104230427501902511021622302041980103290338898000080000801003028030195302343005630166
16020430200227303000010112022172112065624301592284151723778198625160223802158000080100800004009501334578013330020302913014410102031016516010020016000020016000030292302081180201100994100100800008000001008244229225233648231823361112420580309185091735133247432481902511021622302031780121355275868000080000801003025430087300643022030049
16020430065226300100098990224821088717763013022311548777951895251602278023080000801008000040098213431380104302563025230217101890310180160100200160000200160000301393013711802011009910100100800008000001008245332223032338208223321132396600285484395581107231229211902511021622301891180122361346758000080000801003014830231302022987030127
16020430165226303000098430229221440105816300692273117718826178525160206802318000080100800004009651333037013230086300933022810180031012716010020016000020016000030182303841180201100995100100800008000001008294337227829098271823311102400366313084917693110286732711903511021622300822180105363335788000080000801003021430257297833007630070
160204301212263330000960902267210567258030105221014985261817162516020180220800008010080000401027132914601423010730171300099937031013716010020016000020016000030197300871180201100999100100800008000001008242929226429928217423521112390590293284455647122245828683732511021622300802980127284327938000080000801003031630094300093025530322

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3760

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f20222324293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f6067696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a5ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3cfd0d5map dispatch bubble (d6)dadbddfetch restart (de)dfe0e7? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160034301752261010000094030220810014646821630144218713671666016532516012280144800008001080000400551133316301133300492993030067996703100911600102016000020160000299323021811800211091110108000080000010824531923122512082207235111524065062745843626711081836247519025025031600235299952480111328334718000080000800103010930002300773004829959
1600243013122510010000950002257100135258124300612199925737231865251601118013580000800108000040049213241290111930103299673012599280310025160010201600002016000030190300191180021109111010800008000001082409192239279708232823541142436506270184629546872194266518065024021500235300702580112332349718000080000800103009230112299012964929987
1600242997522611000000998702202100140877256300502206124718820173025160126801528000080010800004005591332845011033004930088296351003303100721600102016000020160000300673000711800211091010108000080000010824292322932800082411236611124205102727845405841062068234319325024341600525301511080123257330628000080000800103017830056300853008530025
1600243010122510000000950302228100134469264300562283158724686169425160134801308000080010800004004931307792011193006230016301231005403100571600102016000020160000301293009711800211093101080000800000108240802284239108218423501132404984246684748493101101520500025024031600345299361580106353277868000080000800102995129989301263004830057
16002429979226000000009784022301001464581042992122071125307381858251601228014480000800108000040048613094180111030033301283003899550310302160010201600002016000029967300231180021109310108000080000010824331922812701082067237011824027302838844774611012197242519025025041600435300512280112354304858000080000800102965730008300353007630021
16002430162226100000009702022311001480641322987121881375815291765251601498012480000800108000040062913341870195298952995229971993103997916001020160000201600002997229971118002110951010800008000011082437192264218008256723381122406758266084393669110233026270025024021600334300622480134269265438000080000800102997029976301943020830112
16002430077224000000009848022171001384792403024821561107316901826251601228033280000800108000040053313317820110930032300813002410074031004316001020160000201600003010530059118002110941010800008000001082428422672596082421234111724037622844846856351041936119200250240316005243012022801082252681058000080000800103018630027299773010030151
16002430178227100000009624022341001440732523004522121136537611530251601248012880000800108000040058213313070111830011300633023610105031019216001020160000201600003022730097118002110961010800008000011082429232242307508195223591132435628282384383669942240206919025024041600424301292280114313304808000080000800103006230021300513011530077
160024300402261100000091700221910015206827630026220613246871518702516010780119800008001080000400521132994501110300103010230022100810310215160010201600002016000030168301802180021109410108000080000010824053226728240820692356116242376429658455859498218828280125025041600134301542180127313264808000080000800103003330066301093024630083
16002430083226100000009967022311001416732643005521961307428001772251601268012980000800108000040059713252050112730134300613013610037031006416001020160000201600003005430063118002110971010800008000001082439212269313608195223111152440510273284643696106203725333602502403150031430088980105314288578000080000800102997930222299693009730054