Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDP (post-index, S)

Test 1: uops

Code:

  ldp s0, s1, [x6], #0x10
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f1e2022293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
2005104081111003134101010251501110252000100010001000100052828458241101510401040699377320002000200010401040111001100010000102390211022001221671052360724610732161110371000312910001000100010411041104110411041
200410408101200411600101025901310252000100010001000100052844458241101510401040699377320002000200010401040111001100010000103280301027101161681015160720710731161110371000231910001000100010411041104110411041
2004104071110003824101121025000011252000100010001000100052828458241101510401040699377320002000200010401040111001100010000103380281045001100101024280724710731161110371000211710001000100010411041104110411041
20041040811110031160011610250055725200010001000100010005284845824110151040104069937732000200020001040104011100110001000010071302910532011316101041360732701731161110371000282210001000100010411041104110411041
20041040713121039000101025000082520001000100010001000528444582411015104010406993773200020002000104010401110011000100001032703010236010701010302001124710731161110371000332210001000100010411094104110411041
20041040811010034241012010252802510252000100010001000100052852458241101510401040699377320002000200010401040111001100010000104180301029183104241210303201340700731161110371000361310001000100010411041104110411041
20041040811111043261010102521031102520001000100010001000528564582411015104010406993773200020002000104010401110011000100001032813410461010616710362401120720731161110371000293210001000100010411041104110411041
200410408111100384040101025000082520001000100010001000528284582511015104010406993773200020002000104010401110011000100001031702510311010024121032240616600731161110371000182210001000100010411041104110411041
20041040810100138000101025000011252000100010001000100052852458241101510401040699377320002000200010401040111001100010000103180401006009201110003207327110731161110371000232510001000100010411041104110411041
20041040812110035521022010251500092520001000100010001000528484582411015104010406993773200020002000104010401110011000100001009703610060070071056361632711731161110371000202010001000100010411041104110411041

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp s0, s1, [x6], #0x10
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1607

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f1e202223293a3e3f4043494d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
60214121012911100100250122422012560252121185219431121066257042450304101161000040100100001000010756644599489464118111217370121406121835113561311403160100302002000010000602002000010000121654121698115020110099100401001000010000010012404240020401199441411324245083351241511469500000321002831112160150236910816738100001000050100121464121502121518121771121554
602041216969111000112877227110141601641215912192109121390257040350296101291000040100100001000010812444598972463906601214680122165121523113743311403860100302002000010000604822000010000121867121359115020110099100401001000010000010012415139320501201741611324005063341240498612300000321001831112114250200896824705100001000050100121291121745121481121403121526
602041216489121000102796222710121602081212882205111207972570379503081010610000401001000010000107630946056224598639012184101217071218151133623114053601003020020000100006020020000100001217241216801150201100991004010010000100000100123901395202212003405115242649434412423107110900000321001832112169550252796852609100001000050100121734121752121507121607121687
6020412195291410020026632237101584024812156122201221210212570448503481010710000401001000010000107422746070054645093012155601219411217241137383114434601003020020000100006020020000100001219891218111150201100991004010010000100000100123981399204012006417114241653833712403124312300000321001831112130750228798714786100001000050100121695121913121478121549121570
60204121668914110010256022071014400240121559219421121459257041550314101331000040100100001000010768934611291464501401215120121637121653113407311396460100302002000010000602002000010000121655121437115020110099100401001000010000010012432139320461203246711224294943391241311969500000321001831112122050214912866734100001000050100121243121407121783121885121759
602041208389121001002617222110141602121217522202101209732570433503121008110000401001000010049107569146030914638318012176101216201215531136093114259601003020020000100006020020000100001217741216001150201100991004010010000100000100124201403210312017414111241250434312414114610601200321001831112130050086718912753100001000050100121297121557121579121565121578
60204121788911110000254122491014161264121282219655120887257038250304101111000040100100001000010741494606190463443701216500121372121950113720311412560100302002000010000602002000010000121524121556115020110099100401001000010000010012423239220611199538611524265023491242311449200000321001831112144950226838704727100001000050100121390121614121595121251121601
602041217139101100102508224010136002841215462193241211962570421503041011210000401001000010000107705146122474631224012145801215201218391134623113998601003020020000100006020020000100001218331219221150201100991004010010000100000100124282394205512031399115241648832712406101112401000321001831112120450258926662607100001000050100121559121813121589121340121742
60204121654912110010251322241014000128121258220151121153257040350308101041000040100100001000010745244613270462586001214520121632121425113415311405960100302002000010000602002000010000121557121823115020110099100401001000010000010012392238820501201241611324167423331242111248000000321001831112102550214814858623100001000050100121558121667121326121476121530
6020412089590810010026322253101352122812154621982112118725703795028210120100004010010000100001077837461171646437060121583012153612154611361831139766010030200200001000060200200001000012163812178111502011009910040100100001000001001241034022047120104231132428494332123859548401000321001831112145450228872756660100001000050100121538121684121496121839121309

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1549

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f20222324293a3e3f4043494d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)6061696b6d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
60034121780912300000000243102252100118421321216452197201211442570334502161008910000400101000010000107556645976194624331051213740121503121747113465031142866001030020200001000060020200001000012139912156611500211091040010100001000001012428163892062120113661112428643101243210701000000003165006784512130050218941897704100001000050010121901121572121904121984121390
60024121744910100000000240502272100141622441214682247101210662570337502261007910000400101000010000107526046092334644985051216050121558121576113437031141866001030140200001008260262200001000012176712111611500211091040010100001000001012426033120811207336189243518234012398100010410700035210093278612139550271919708775100001000050010121526121944122287125012121549
600241213909131000010002933022591001144359212498421683012402010537103350709102351007545736115841066711794124701676473198600125569012649712577211538004251166506927233197233911172870318233841164712592212559545150021109104001010000100000101242416563188911850572103237252120291124261381148002000408600718179125384507148971155990100001000050010127853122953127484121898121544
60024121793940000000000219202215001135212001215792207011215002570337501981013110000400101000010000107506246130454635386001216340121275121402113745031137546001030020200001000060020200001005012189912160611500211091040010100001000001012416838120881206036211124392143321239313231300300003163002784212139650180626894552100001000050010121577121984121795121823121604
60024121627911200000000228302280010124803041216062221011211682570376502181010710000400101000010000107481946021194636135001213800121315121665113842031142096001030020200001000060020200001000012188312184311500211091040010100001000001012432134620691203141911024272303241242211621140000003140007785612154550190806780780100001000050010121731121631122015121683121184
600241213979101000001002414022590101392013612133721910112109525703855018610106100004001010000100451077429460576146251660012166401216261213951137570311400360010300202000010000600202000010000121513121814115002110910400101000010000010124280345205612010400107242862327124298211150400003140006786612119550208947871661100001000050010120871121303122189121594121583
600241212309090200010002548022650011456025212126822070312137625703195023010109100004001010000100001076996460976946423701012143901216961218281134510311360360010300202000010000600202000010000121393121485115002110910400101000010000010124091838020871202340311324202303361244412501130000003140003784512135350248782818734100001000050010121647121749121542121411121531
6002412200891120000000025800222800113843100121590221221121084257034350304101291000040010100001000010712454598343464816110121805012139512159911359703113922600103002020000100006002020000100001215061215241150021109104001010000100000101241093752057120103531132418643391238511801080000003140007783512121850184806804812100001000050010121497121444121622121579121602
600241215499111000000002408022730011320013212139122041012131425703255022410103100004001010000100001074575459524046339851012136901215171215681134660311414960010300202000010000600202000010000121641121565115002110910400101000010000010124220385204212012404114242023832112428791900000013140553786612120450206818862636100001000050010121569121356121524121507121448
6002412120691200000000025110227800113840108121551219801121446257031350244100771000040010100001000010741164618334464139810121697012154512141211334903114055600103002020000100006002020000100001215661216801150021109104001010000100000101241503372061120244011162407252346124291042870000003140555785312160150226810698710100001000050010121684121490121875121593121527

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp s0, s1, [x6], #0x10
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1719

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f181e2022293a3e3f40494d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3branch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
60214121367913500000024752224112324212121860220701214052570466503361012910000401001000010000107961845998314638378112198501216451215701139303113892601003020020000100006020020000100001218201217301150201100991004010010000100000100124132938220491200541711124272463301240911909600000321018311121547502328021038670100001000050100121810121432121723121791121675
602041210599125500000256422401152042081218192217012119425704485034810116100004010010000100001076192460821946393010121821012193012177011375031142756010030200200001000060200200001000012169112130811502011009910040100100001000001001242825400205112005413116241223232512399132011110000321018311121403502801012878832100001000050100121791121640120995121863121852
602041217409145050000248422371146432361218062197012134125704155037410125100004010010000100001076501461196446404870121874012178812190111350831141246010030200200001000060200200001000012161412174511502011009910040100100001000011001242533392204812031418115242424634012387133011700001321018311121534502261038950851100001000050100121815121722121821121667121855
60204121922911500000025762238114003328121573217301212142570457503601013010000401001000010000107827746192134646602012206901220641216061135013113792601003020020000100006020020000100001216791220551150201100991004010010000100000100124251837720661199840011724142483381240911101101000032101831112131350240774890825100001000050100121732121344121427121487121713
60204121749914400000025342247114003280121781221201211732570457503721012310000401001000010000107622546098274637768012174901216981218291139383114045601003020020000100006020020000100001218171217961150201100991004010010000100000100124302638820521200841111624242223271239712611261000032101831112160250218870920724100001000050100121575121566121650121654121903
602041217849114000000258722291139232521218222209012150125705025029810099100004010010000100001075853461355246311120121750012192512164211379731139156010030200200001000060200200001000012156312168611502011009910040100100001000001001243733355204812068362116240836633112392108112513000387213154112406750608119612981028100001000050100124854124886124772124527124329
60204124465932400100025352241116645368124894213811233246077087450651102051004944100111061086111454864683479469507601251330126450125367115502421117016698593020020000100006020020000100001215561220722315020110099100401001000010000010012417263902002120074151112418238355124091451129252003210111221122174502409861014824100001000050100122829121659121810121639124276
60204122412980420000025832240114163256122008219101212582570472503661012310004401001000010000107678946125814648018112161501217591219261130873114098601003020020000100506020020098100001218051209151150202100991004010010000100000100124254035719961202141111524162503341238110621172010032101831112167050196926838692100001000050100121727121881121798121623121759
60204121814911600000026022270114003200121740220101215102570478503721012610000401001000010000107871546052294635995112158601212991215201138593113971601003020020000100006020020000100001217331217521150201100991004010010000100000100124242942420551201242511424281083521241712111181000032101831112137750250992914667100001000050100121761121641121662121985121756
60204121803912400001024242235115284240121592221601213582570442503481012110000401001000010000107613846097624639913112193801217451215901134893114144601003020020000100006020020000100001216941217901150201100991004010010000100000100124212938920871200041811624322383321240110921170000032101831112145850264852804824100001000050100121629121833121647121798121654

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1500

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f1e2022293a3e3f40434d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3branch mispred nonspec (cb)cfd2d5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
60034120907910100000219222351145619212145022181120787257031650202101011000040010100001000010745534600185462586601214001216431214901136300311411560010300202000010000600202000010000121138121508115002110910400101000010000010124421639421061199338810524382363151241593050046031401157809812112850204695822800100001000050010121506121371121425121448121495
60024121495910100110222322381124812001217312216112125925703465021810112100004001010000100001076835460516946343950121555121519121795113845031140816001030020200981000060020200001000012165712156211500211091040010100001000001012440833820801202841510624257632112415121110410003140097808812135050198921737740100001000050010121471121516121252121604121559
600241213989081001002343227911408118412145022050121246257032250174100861000040010100001000010723354613867464238501215521215061214261131100311374660010300202000010000600202000010000121375121673115002110910400101000010000010124198382205112065402108241450330124069108800003140087807712113050174816737824100001000050010121714121414121589121667121510
600241215299091100002309227111296139612130122290121124257028950186100911000040010100001000010764034603466462941401213211215461216821137830311375160010300202000010000600202000010000121655121493115002110910400101000010000010124161375205712067355107242512632212430106010000003140077808812107050202744789816100001000050010121426121518121700121547121357
600241213539121000002339228511384119612079822110121222257030150210100991000040161100001000010764214591189463828501213661213211215241126530311414960010300202000010000600202016010000121377121521215002110910400101000010000010124298377205112061357111243876318124251011107001031400878091112126750168784694684100001000050010121552121483121477121659121482
600241215009131000002394224711352115212172422161121043257038850210100991000040010100001000010759894599966462741701214571217061217541135780311390660010300202000010000600202000010000121528121433115002110910400101000010000010124348339211612057368109242922831912419105095100031402978011912113950234730814704100001000050010121361121435121662121455121608
600241213509091000002328225411224120812149722131121053257024150216101031000040010100001000010772134611016464038601214351214301218211135510311386860010300202000010000600202000010000121812121375115002110910400101000010000010124249350204812122371111242868324124169407500003140077807812110950190954761675100001000050010121695121606121440121460121551
60024121429911100100232222901133611881213182209012121325703615021210096100004001010000100001075971460175746319390120970121328121634113610031138906001030020200001000060020200001000012151312130711500211091040010100001000001012445833321231204436810524241903311241479092000031400978010712128750194817787707100001000050010121361121346121525121367121327
60024121805910100001218722441139219612125322231121391257034950238100901000040010100001000010760884607958464032901213431213841215401134380311388160010300202000010000600202000010000121703121252115002110910400101000010000010124238368205912061372109241470303124141140114000031400978012912100250216785855685100001000050010121298121087121412121369121523
60024121203912100000239322431141622201216782243112085525702895020410107100004001010000100001076790460566946333250121285121118121453113607031137476001030020200001000061000200001000012151312162011500211091040010100001000001012448837220561201537410824442003211243511109100203140087807712137950158954648524100001000050010121440121399121471121696121491

Test 4: throughput

Count: 8

Code:

  ldp s0, s1, [x6], #0x10
  ldp s0, s1, [x7], #0x10
  ldp s0, s1, [x8], #0x10
  ldp s0, s1, [x9], #0x10
  ldp s0, s1, [x10], #0x10
  ldp s0, s1, [x11], #0x10
  ldp s0, s1, [x12], #0x10
  ldp s0, s1, [x13], #0x10
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3766

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f1e1f2022293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)606267696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5b6bbl1d cache miss ld nonspec (bf)c2c3cfd5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16021430146225111109659022121160072484301442173129692624202525160219802048000080100800004009921336561001062992830261302369986031023516010020016000020016000030343302481180201100991510010080000800001100824092224827128245123051112407506296284914680125222432853451102162230110158013429586538000080000801003014429998302363014830176
1602043015022600001979002223113606944830142219212150957515192516020580226800008010080000400969133153100108300033007430176101120310099160100200160000200160000299862967611802011009911100100800008000011008248802427250782182229311723989542461847677151132136271034511021622301081980110318290758000080000801002999130033300662995730091
160204302052260000095380223811448851843003321821166687691753251602188019780000801008000040100213321120011230170300363025310095031013816010020016000020016000029972302041180201100991510010080000800001100824060226324608227923561112434816264884582661982167274834511021722301811080111359303798000080000801003005030183306783024030051
16020430130225000009723022291146450120299392247136669542182925160209802158013080288800004010471331786001183003530148302359901039969160100200160000200160000300143012411802011009915100100800008000011008243002269232482439231011524007522236845587241031884267034511021622301312880131277322728000080000801003003330100301843034130212
160204299722260000092710221111312752523011821741456537061766251602058021580000801008000040097213391230098301333021930111999103101461601002001600002001600002998230265118020110099151001008000080000010082392222122609822752281109241050627988450170810222952649345110216223013325801032913541038000080000801003016530129302183016030212
16020430158226000009859022141145663300299502206107704657179625160213802228000080100800004009371337100011033017230076300181004403996316010020016000020016000030132300851180201100998100100800008000001008241602208271682120239211423987522835842756271311880241533511021622301741880126325284998000080000801003013530173301203033930020
1602043017922200000970302242114086120030032221014572256814222516020480219800008010080000400996133148800115301883015430031997603101421601002001600002001600002993330008118020110099410010080000800000100824080225927138196223211132420788260584708653941966287634511021622302141880102340310808000080000801003024430019301273021030058
1602042976022600000942102219116406425230225219111457355018392516021580222800008010080000400923133186900103300083014830176101170310013160100200160000200160000300393023311802011009926100100800008000001008239802219255382061236411224467542498846645871322163226344511021622301812480090335330908000080000801002999830618301523019930116
160204300902240000093890224711424644323012621741065703351845251602008022380000801008000040099013284320010630026300613028999550310181160100200160000200160000300233018811802011009926100100800008000001008239922240330082505238611424027502654848616911071940259534511021622302242680098381398898000080000801003011730238302903018230014
160204300842270000095290221411400511203000122181345508931926251602218022980000801008000040096413332240010730076301053034798980310135160100200160000200160000301973006111802011009919100100800008000001008240402241291982172233311424085083002845317431021896239934511021622301501780119322363788000080000801003016230146302252972730218

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3784

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e2022293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f6067696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a5ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3cdcfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)dbddfetch restart (de)e0e7? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16003430269226400100010433216811864802563029620951701033822200025160110801168000080010800004005061337197119430291030196302011040731033216001020160000201600003026530312118002110911010800008000001082400262187396408323122611072400246363385336677133254427430020502000031601273024422800993693221218000080000800103051629898303223047930270
160024303892282200000102682155118805924830301212412495411071909251601088010980000800108000040044113385470098302350304013031210297310464160010201600002016000030276304831180021109810108000080000010824122621903146083313226910823962463903854388431393182319800205020000416046304551980083300146998000080000800103020330227303253016030450
160024304812262000000976121431160878260302062168165847105620242516013280133800008001080000400536133871701108304250303203025310256310272160010201600002016000030353305511180021109310108000080000010824081622593219082330229299240824840058462366311427892867024050200004160463019720801112682831008000080000800103017730278302433037930256
16002430229227200000010367218611608772563025520959598198119252516010980107800008001080000400479134222000983016103036130429102443102341600102016000020160000303703017611800211093101080000800000108239214216031210833252366102237225436278472879113525672953002050200005160533026629800993433291148000080000800103026129749301143038930337
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160024304282262001000102162169118166048830363211320297478318972516012380124800008001080000400526134347300103300940303973015910101310116160010201600002016000030150301421180021109510108000080000010823943221835270832562281102238525453568545276712026313244002050200006160453029933801142152631098000080000800103010330186301133042630251
160024303282282201000102882144116485626030120211018680210142018251600938012280000800108000040052613220910011130034030317302631030431004816001020160000201600003038730130118002110911101080000800000108242410221133240831752290100237125428358502082513031763283002050200006150463038120801062713581138000080000800103009830252302243033730322
160024302472252200000996721421162486492301042122176860822194525160118801098000080010800004005261345257001003031303031530473102823103241600102016000020160000302843005911800211095101080000800000108242018221130750831262316101241825441948508573414329483289180205020000516049301852180099353339838000080000800103001529839301933026030329
160024303462252200011103442166116246549230337215216478097718772516011580101800008001080000400458134353400112302410300403032910197310329160010201600002016000030179300991180021109610108000080000010824041622033887082505229310723822543760851348591363098310800205020000515076300371980110394329998000080000800103029630129304823023230337