Firestorm: LDP (pre-index, D) measurements

Code:

  ldp d0, d1, [x6, #0x10]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1040	7	0	0	1	0	0	0	48	37	1	0	0	1	0	1025	43	0	0	0	10	25	2000	1000	1000	1000	1000	51356	45825	1	1015	1040	1040	699	3	773	2000	2000	2000	1040	1040	1	1	1001	1000	1000	0	1050	8	0	38	1040	6	0	40	0	7	1000	27	0	7	27	7	1	1	73	2	16	2	2	1037	1000	41	40	1000	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	0	0	0	0	25	26	1	0	0	1	12	1025	21	0	1	0	7	25	2000	1000	1000	1000	1000	52852	45825	1	1015	1040	1040	699	3	773	2000	2000	2000	1040	1040	1	1	1001	1000	1000	0	1036	7	0	29	1014	0	0	28	22	7	1047	27	0	7	39	7	1	0	73	2	16	2	2	1077	1000	25	23	1000	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	0	0	0	0	0	41	28	1	0	0	1	0	1025	16	0	0	3	11	25	2000	1000	1000	1000	1000	52860	45824	1	1015	1040	1040	699	3	773	2000	2000	2000	1040	1040	1	1	1001	1000	1000	0	1030	8	0	19	1009	6	1	16	8	6	1004	23	0	7	19	6	1	60	73	2	16	2	2	1037	1000	36	31	1000	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	0	0	0	0	26	24	1	0	0	2	0	1025	15	0	1	1	6	25	2000	1000	1000	1000	1000	52860	45824	1	1015	1040	1040	699	3	773	2000	2000	2000	1040	1040	1	1	1001	1000	1000	0	1047	8	0	20	1022	8	0	39	0	7	1024	15	0	7	27	7	1	0	73	2	16	2	2	1037	1000	23	23	1000	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	0	0	1	0	0	25	38	1	0	0	2	0	1025	38	0	1	1	7	25	2000	1000	1000	1000	1000	52864	45824	1	1015	1040	1040	699	3	773	2000	2000	2000	1040	1040	1	1	1001	1000	1000	0	1023	7	0	23	1023	0	0	13	0	8	1000	39	0	7	23	7	1	0	73	2	16	2	2	1037	1000	34	31	1000	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	0	1	0	0	25	22	1	0	0	1	0	1025	9	0	1	1	5	25	2000	1000	1000	1000	1000	52852	45824	1	1015	1040	1040	699	3	773	2000	2000	2000	1040	1040	1	1	1001	1000	1000	0	1023	7	0	16	1025	0	0	17	8	7	1024	31	1	6	15	7	2	0	73	2	16	2	2	1037	1000	25	21	1000	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	0	3	0	0	29	16	1	0	0	1	0	1025	9	0	1	2	4	25	2000	1000	1000	1000	1000	52852	45825	1	1015	1040	1040	699	3	773	2000	2000	2000	1040	1040	1	1	1001	1000	1000	0	1025	7	0	25	1024	0	0	17	18	7	1016	27	0	7	19	7	1	0	73	2	16	2	2	1037	1000	25	23	1000	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	2	0	1	0	0	26	16	1	0	2	2	0	1025	14	0	2	1	7	25	2000	1000	1000	1000	1000	52864	45824	1	1015	1040	1040	699	3	773	2000	2000	2000	1040	1040	1	1	1001	1000	1000	0	1052	8	0	25	1038	8	0	21	30	7	1020	35	0	7	19	7	1	0	73	2	16	2	2	1037	1000	27	23	1000	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	0	0	0	0	29	24	0	0	0	1	0	1025	10	0	1	0	7	25	2000	1000	1000	1000	1000	52856	45825	1	1015	1040	1040	699	3	773	2000	2000	2000	1040	1040	1	1	1001	1000	1000	1	1031	8	0	24	1023	1	0	17	8	7	1000	26	0	7	23	7	0	0	73	2	16	2	2	1037	1000	43	34	1000	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	0	1	0	0	26	16	1	0	0	0	0	1025	17	0	0	0	14	25	2000	1000	1000	1000	1000	52848	45824	1	1015	1040	1040	699	3	773	2000	2000	2000	1040	1040	1	1	1001	1000	1000	1	1036	7	1	42	1032	2	0	29	22	7	1038	15	0	7	27	7	1	0	73	2	16	2	2	1037	1000	38	36	1000	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp d0, d1, [x6, #0x10]!
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1619

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	24	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60214	121371	910	4	0	0	0	0	0	0	0	2631	0	2183	1	0	1656	2	260	121944	2175	0	1	121025	25	70454	50276	10081	10000	40100	10000	10000	1073487	4597772	4629533	0	121481	0	121585	121635	113394	3	113890	60100	30200	20000	10000	60200	20000	10000	121664	121520	1	1	50201	100	99	100	40100	10000	10000	0	100	12409	2	401	2056	12004	355	114	2390	246	334	12399	75	3	98	1	0	0	3210	1	83	1	1	121187	50212	998	773	619	10000	10000	50100	121370	121583	121318	121614	121410
60204	121674	910	2	0	0	0	0	0	0	0	2401	0	2253	1	0	1488	1	188	121452	2217	0	0	121156	25	70439	50292	10103	10000	40100	10000	10000	1080642	4601436	4629657	0	121807	0	121720	121636	113709	3	114063	60100	30200	20160	10000	60444	20000	10000	121789	121478	4	1	50201	100	99	100	40100	10000	10000	0	100	12423	2	386	2062	12010	411	113	2408	234	304	12427	117	2	100	1	0	1	3233	1	83	1	1	121440	50202	774	759	781	10000	10000	50100	121281	121310	121623	121636	121515
60204	121229	911	2	0	2	0	0	0	0	0	2453	0	2232	1	0	1360	1	292	121546	2192	2	0	121186	25	70448	50334	10097	10000	40100	10000	10000	1076146	4594315	4626186	0	121905	0	121828	121947	113463	25	114080	60543	30200	20000	10121	61184	20000	10049	121911	121582	1	1	50201	100	99	100	40100	10000	10000	0	100	12410	2	390	2067	12001	417	110	2440	232	323	12417	114	1	91	1	0	0	3210	1	83	1	1	121273	50180	847	550	675	10000	10000	50100	121694	121711	121793	121774	121657
60204	121470	908	2	0	0	0	0	0	0	0	2621	0	2234	1	0	1448	1	176	121876	2136	1	0	121696	25	70358	50324	10101	10000	40100	10000	10000	1077008	4610342	4629003	0	121397	0	121588	121646	113617	24	113709	60100	30200	20000	10000	60200	20000	10000	121498	121726	1	1	50201	100	99	100	40100	10000	10000	0	100	12419	4	431	2042	12001	371	112	2418	112	322	12437	110	1	105	1	0	0	3210	1	83	1	1	121386	50208	740	724	820	10000	10000	50100	121528	121614	121284	121629	122008
60204	121817	912	3	0	0	3	0	0	0	0	2451	0	2234	1	0	1640	1	244	121703	2197	0	0	120845	25	70367	50332	10097	10000	40100	10000	10000	1076585	4603905	4640644	0	121646	0	121789	121974	113804	3	113722	60100	30200	20000	10000	60200	20000	10000	121447	121599	1	1	50201	100	99	100	40100	10000	10000	0	100	12432	2	405	2059	12011	401	109	2425	250	326	12421	94	1	108	1	0	0	3210	1	83	1	2	121203	50200	907	729	866	10000	10000	50100	121761	121371	121810	121459	121429
60204	121541	912	2	2	0	0	0	0	0	0	2247	0	2222	1	0	1424	1	312	121473	2206	0	1	121446	25	70427	50318	10105	10000	40100	10000	10000	1076990	4602065	4625744	0	121451	0	121504	121678	113523	3	113820	60100	30200	20000	10000	60200	20000	10000	121803	121382	1	1	50201	100	99	100	40100	10000	10000	0	100	12407	2	389	2044	12029	419	109	2422	252	320	12424	98	1	117	1	0	0	3210	1	83	1	1	121350	50230	832	805	831	10000	10000	50100	121680	121560	121689	121462	121619
60204	121626	911	2	0	0	2	0	0	0	0	2664	0	2211	1	0	1656	1	188	121624	2224	0	0	121057	25	70385	50290	10108	10000	40100	10000	10000	1072877	4594345	4630743	0	121656	0	121590	121565	113327	3	114280	60100	30200	20000	10000	60200	20000	10000	121680	121802	1	1	50201	100	99	100	40100	10000	10000	0	100	12405	2	368	2041	11995	404	111	2416	232	313	12427	111	2	72	1	0	0	3210	1	83	1	1	121194	50204	760	968	654	10000	10000	50100	121504	121663	121294	121566	121528
60204	121577	911	2	2	0	0	0	0	0	0	2378	0	2237	1	0	1392	1	268	121738	2178	0	1	121132	25	70445	50340	10110	10000	40100	10000	10000	1075244	4615308	4629339	0	121586	0	121743	121783	113817	3	114123	60100	30200	20000	10000	60200	20000	10000	121425	121504	1	1	50201	100	99	100	40100	10000	10000	0	100	12429	2	384	2046	11993	414	107	2396	246	305	12418	93	1	117	1	0	0	3210	1	83	1	1	121526	50176	652	952	906	10000	10000	50100	121503	121554	121487	121546	121778
60204	121786	911	2	0	2	0	0	0	0	0	2396	0	2274	1	0	1472	1	180	121452	2214	0	1	121045	25	70487	50276	10110	10000	40100	10000	10000	1077152	4605666	4644421	0	121698	0	121809	121470	113750	3	113843	60100	30200	20000	10000	60200	20000	10000	121417	121703	1	1	50201	100	99	100	40100	10000	10000	0	100	12435	2	384	2051	12018	412	111	2412	248	316	12409	91	2	103	1	0	0	3210	1	83	1	1	121374	50238	658	896	625	10000	10000	50100	121726	121648	121524	121794	121632
60204	121517	912	2	0	0	2	0	0	0	0	2547	0	2233	1	0	1472	1	312	121464	2224	1	0	121510	25	70427	50338	10096	10000	40100	10000	10000	1077449	4607575	4625485	0	121670	0	121763	121418	113718	3	114065	60100	30200	20000	10000	60200	20000	10000	121865	121649	1	1	50201	100	99	100	40100	10000	10000	0	100	12425	2	393	2032	12004	413	110	2422	284	12354	12413	104	2	109	1	0	3	3210	1	83	1	1	121484	50198	671	761	913	10000	10000	50100	121457	121852	121648	121831	121710

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1476

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60034	121151	908	1	0	0	0	0	0	0	0	2367	0	2301	1	1456	0	236	121587	2211	0	0	121109	25	70295	50176	10106	10000	40010	10000	10000	1075863	4601611	4634638	0	120767	0	121593	121554	113731	3	114071	60256	30020	20000	10000	60020	20000	10000	120672	121330	1	1	50021	10	9	10	40010	10000	10000	0	10	12418	0	378	2136	12083	384	115	2406	50	642	12402	35	0	85	0	0	0	3140	2	78	1	1	120412	50194	653	797	240	10000	10000	50010	120669	121554	121358	121441	121695
60024	121518	912	0	0	0	0	0	0	0	0	2359	0	2249	1	1456	0	180	121666	2242	0	0	120269	25	70268	50232	10103	10000	40010	10000	10000	1075728	4610124	4625794	1	121286	3	121464	121331	112661	3	113924	60010	30020	20000	10000	60020	20000	10000	121430	121498	1	1	50021	10	9	10	40010	10000	10000	0	10	12447	0	376	2123	12034	395	109	2422	70	541	12391	102	0	113	0	0	0	3140	1	78	1	1	121144	50190	777	799	645	10000	10000	50010	121348	121314	121404	121638	121417
60024	121605	906	0	0	0	0	0	0	0	0	2417	0	2243	1	1184	0	200	121332	2275	0	0	120456	25	70304	50240	10086	10000	40010	10000	10000	1077663	4602362	4632109	1	121807	0	121419	121219	113650	3	113838	60010	30020	20000	10000	60020	20000	10000	121687	121601	1	1	50021	10	9	10	40010	10000	10000	0	10	12486	0	368	2130	12083	386	113	2407	56	570	12416	77	0	82	0	0	0	3140	1	78	1	1	121304	50208	694	881	643	10000	10000	50010	121556	121677	121763	121731	121800
60024	121341	909	0	0	0	0	1	0	0	0	2332	0	2254	1	1360	1	100	121684	2209	0	0	121279	25	70316	50226	10115	10000	40010	10000	10000	1074549	4615415	4625237	1	121532	0	121750	121410	113627	3	113945	60010	30020	20000	10000	60020	20000	10000	121852	121375	1	1	50021	10	9	10	40010	10000	10000	0	10	12426	0	383	2061	12003	402	110	2419	232	628	12436	100	0	108	0	36	0	3140	1	78	1	1	121126	50250	987	849	734	10000	10000	50010	121424	121396	121509	121337	121951
60024	121329	910	1	0	0	0	1	0	0	0	2392	0	2236	1	1248	0	140	121364	2198	0	0	120909	25	70277	50216	10101	10000	40010	10000	10000	1076079	4595248	4630404	1	121339	0	121632	121542	113591	3	113965	60010	30020	20000	10000	60020	20000	10000	121815	121204	1	1	50021	10	9	10	40010	10000	10000	0	10	12436	0	373	2116	12020	363	113	2447	242	558	12448	88	0	92	0	0	0	3140	1	78	1	1	121292	50182	879	761	595	10000	10000	50010	121788	121341	121647	121382	121285
60024	121353	910	1	0	0	0	1	0	0	0	2208	0	2243	1	1256	0	144	121476	2255	0	0	121154	25	70382	50184	10096	10000	40010	10000	10000	1076808	4599689	4629488	0	121584	0	121717	121714	113340	3	113916	60010	30164	20000	10000	60020	20000	10000	121700	120799	1	1	50021	10	9	10	40010	10000	10000	0	10	12416	0	381	2105	12114	384	113	2442	234	747	12422	104	0	98	0	0	0	3140	1	78	1	1	121373	50194	303	455	181	10000	10000	50010	121350	121626	121399	121432	121555
60024	121342	910	0	0	0	0	0	0	0	0	2179	0	2277	1	1416	0	108	121508	2281	0	1	120411	25	70274	50208	10037	10000	40010	10000	10000	1075890	4600423	4635898	0	121659	0	121613	120566	113549	3	113767	60010	30168	20000	10000	60020	20000	10000	121247	121547	1	1	50022	10	9	10	40010	10000	10000	0	10	12384	0	382	2054	12075	353	111	2446	168	648	12412	87	0	80	0	0	1	3140	1	78	1	1	120404	50174	863	757	321	10000	10000	50010	121586	121410	121497	120608	121484
60024	121351	906	0	0	0	0	0	0	0	0	2215	0	2272	1	1176	0	232	121346	2240	0	0	121071	25	70268	50210	10107	10000	40010	10000	10000	1076394	4609937	4628836	0	121647	0	121320	121472	113669	3	113871	60010	30020	20000	10000	60020	20000	10000	121518	121374	1	1	50021	10	9	10	40010	10000	10000	0	10	12415	0	384	2104	12019	400	112	2410	56	546	12395	106	0	100	0	0	5	3140	1	78	1	1	121211	50192	748	810	752	10000	10000	50010	121321	121367	121239	121562	120842
60024	121325	903	0	0	0	0	1	0	0	0	2150	0	2287	1	1248	0	132	121511	2206	0	0	120808	25	70184	50174	10119	10000	40010	10000	10000	1073190	4611558	4636505	1	120723	0	121696	121366	113243	3	113633	60010	30020	20000	10000	60020	20000	10000	121768	121464	1	1	50021	10	9	10	40010	10000	10000	0	10	12426	0	382	2117	12054	371	110	2438	64	555	12426	92	0	93	0	0	0	3140	1	78	1	1	121164	50208	831	708	523	10000	10000	50010	121748	121697	121533	120813	121628
60024	121576	911	0	0	0	0	1	0	0	0	2297	0	2274	1	1440	0	124	121403	2234	0	0	121324	25	70304	50194	10091	10000	40010	10000	10000	1075341	4613658	4630095	0	121506	0	121712	121609	113352	3	114051	60010	30020	20000	10000	60020	20000	10000	120682	121829	1	1	50021	10	9	10	40010	10000	10000	0	10	12435	0	376	2065	12017	405	114	2420	256	558	12442	91	0	102	0	0	0	3140	1	78	1	1	121595	50202	774	766	680	10000	10000	50010	121882	121169	121755	121244	121606

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp d0, d1, [x6, #0x10]!
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1715

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	24	29	3a	3e	3f	40	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60214	121475	911	1	0	0	0	0	0	0	0	2243	0	2262	1	0	1272	1	216	121551	2253	120263	25	70457	50292	10129	10000	40100	10000	10000	1072994	4601879	4633222	0	121301	0	121933	121573	113522	3	114171	60100	30200	20000	10000	60200	20000	10000	121769	121343	1	1	50201	100	99	100	40100	10000	10000	0	100	12408	9	397	2181	12013	413	113	2408	500	318	12473	96	0	44	0	0	0	0	0	3210	2	83	2	2	120650	50244	373	406	327	10000	10000	50100	120894	121518	121570	121381	120938
60204	121761	910	2	0	0	1	0	0	0	0	2302	0	2251	1	0	1216	1	272	120973	2225	121130	25	70466	50300	10102	10000	40100	10000	10000	1077438	4611685	4641086	1	121972	0	122087	121605	113642	3	114379	60100	30200	20000	10000	60200	20000	10000	121763	121089	1	1	50201	100	99	100	40100	10000	10000	0	100	12430	24	359	2091	12032	356	111	2430	246	330	12418	123	1	57	0	0	0	0	0	3210	2	83	2	2	120797	50206	1035	367	755	10000	10000	50100	120824	120763	121699	120908	121652
60204	120647	911	2	2	0	0	0	0	0	0	2154	0	2321	1	0	1256	2	184	120961	2315	120615	25	70412	50326	10123	10000	40100	10000	10000	1077735	4612203	4609103	0	121852	0	120933	121519	113869	3	113208	60100	30200	20000	10000	60200	20104	10000	121000	121777	1	1	50201	100	99	100	40100	10000	10000	0	100	12496	8	334	2056	12010	348	112	2444	466	333	12474	55	0	93	0	0	0	0	0	3210	2	17	2	2	121173	50184	348	759	348	10000	10000	50100	121711	121706	121726	121653	121236
60204	121805	906	1	1	0	0	0	0	0	0	2118	0	2229	1	0	1208	1	220	121487	2292	121212	25	70256	50304	10051	10000	40100	10000	10000	1077519	4599245	4631469	0	120823	0	121839	121415	113601	3	114063	60100	30200	20000	10000	60200	20000	10000	121461	121842	1	1	50201	100	99	100	40100	10000	10000	0	100	12438	8	358	2141	12022	369	113	2491	202	333	12424	112	0	105	0	0	5	0	0	3210	2	83	2	2	121508	50102	884	878	398	10000	10000	50100	121418	121510	121705	121605	121415
60204	121521	913	1	1	0	0	0	0	0	0	2331	0	2255	1	0	1400	2	192	121614	2225	121262	25	70406	50330	10093	10000	40100	10000	10000	1075892	4605742	4640941	0	121778	0	121554	121611	113542	3	113984	60100	30200	20000	10000	60200	20000	10000	121794	121085	2	1	50201	100	99	100	40100	10000	10000	0	100	12450	8	377	2106	12133	350	111	2482	122	322	12407	96	0	64	0	0	0	0	0	3210	2	83	2	2	121228	50214	757	971	531	10000	10000	50100	121727	121360	121642	121762	121592
60204	121945	911	2	0	0	0	0	0	0	0	2165	0	2255	1	0	1248	1	192	121584	2206	120881	25	70376	50324	10103	10000	40100	10000	10000	1078160	4607558	4638196	0	121448	0	121668	121602	113462	3	114013	60100	30200	20000	10000	60200	20000	10000	121594	121602	1	1	50201	100	99	100	40100	10000	10000	0	100	12416	8	365	2053	12071	407	109	2429	202	312	12406	117	0	96	0	0	0	1	0	3210	2	83	2	2	121676	50274	958	835	638	10000	10000	50100	121443	121752	121519	121598	121722
60204	121781	910	1	0	0	0	0	0	0	0	2337	0	2272	1	0	1256	1	228	121704	2196	120853	25	70394	50312	10112	10000	40100	10000	10000	1076720	4610777	4633421	0	121725	0	121694	121420	113794	3	113711	60100	30200	20000	10000	60200	20000	10000	121371	121631	1	1	50201	100	99	100	40100	10000	10000	0	100	12412	8	318	2044	12081	338	110	2428	300	309	12414	98	0	91	0	0	0	0	0	3210	2	83	2	2	120998	50172	932	833	839	10000	10000	50100	121660	121668	121607	121495	121488
60204	121848	913	1	0	1	0	0	0	0	0	2253	0	2264	1	0	1416	1	104	121363	2232	121060	25	70250	50200	10109	10000	40100	10000	10000	1080275	4610093	4639828	0	121601	0	121619	121466	113494	3	113211	60100	30200	20000	10000	60200	20000	10000	121513	120836	1	1	50201	100	99	100	40100	10000	10000	0	100	12429	8	330	2053	11845	582	112	2379	82	77608	12403	132	0	168	0	0	1	0	0	3886	3	308	3	2	123961	50515	1056	999	988	10000	10000	50100	125154	124815	124978	124759	121498
60204	121755	910	2	1	0	0	0	0	26	26	5405	2024	2191	1	0	1416	1	272	124214	2142	122969	886	70858	50727	10221	10069	44896	11153	11334	1157622	4680326	4725377	0	124681	0	121555	121439	112704	3	114013	62537	35255	23554	10043	70988	23392	11764	121558	121495	7	1	50201	100	99	100	40100	10000	10000	0	100	12400	8	347	2061	12055	360	116	2394	64	23243	12436	141	0	115	0	0	3	0	0	3744	3	326	6	4	122047	50216	847	761	776	10000	10000	50100	121719	121488	121851	121717	121742
60204	121939	949	3	0	0	0	0	0	0	0	2409	0	2275	1	0	1320	3	124	121445	2208	121387	25	70412	50332	10112	10000	40100	10000	10000	1076855	4616759	4628467	0	121921	0	121512	121645	113757	3	114248	60100	30200	20000	10000	60200	20000	10000	121673	121746	1	1	50201	100	99	100	40100	10000	10000	0	100	12404	17	333	2063	12037	414	115	2422	264	315	12407	111	0	89	1	2	0	0	0	3210	2	83	2	2	121245	50250	722	776	656	10000	10000	50100	121849	121641	121691	121913	121646

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1439

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	1e	20	22	24	29	3a	3e	3f	40	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60034	121582	909	1	0	0	0	1	2534	2243	1	0	1408	1	252	121262	2233	121092	25	70337	50192	10092	10000	40010	10000	10000	1074729	4604824	4628334	121420	0	121525	121577	113633	3	113980	60010	30020	20000	10000	60020	20000	10000	121335	121484	1	1	50021	10	9	10	40010	10000	10000	0	10	12409	1	350	2087	12087	401	115	2437	264	331	12427	87	1	107	1	0	0	0	3140	8	3	3	78	4	3	121324	50150	632	710	704	10000	10000	50010	121246	121513	121401	121287	121400
60024	121443	912	1	1	0	0	0	2634	2219	1	0	1416	1	132	121490	2211	121083	25	70277	50204	10108	10000	40010	10000	10039	1075827	4603748	4630794	121386	0	121475	121262	113346	3	114023	60010	30020	20000	10000	60020	20000	10000	121348	121265	1	1	50021	10	9	10	40010	10000	10000	0	10	12431	1	375	2047	12019	387	114	2444	54	334	12416	85	1	78	1	0	0	0	3140	5	0	3	78	2	4	121037	50220	692	824	800	10000	10000	50010	121508	121593	121509	121244	121587
60024	121284	908	1	1	1	0	0	2361	2249	1	0	1208	1	356	121735	2210	121004	25	70307	50204	10094	10000	40010	10000	10000	1075008	4592898	4642705	121315	0	121421	121345	113406	3	113798	60010	30020	20000	10000	60020	20000	10000	121512	121485	1	1	50021	10	9	10	40010	10000	10000	0	10	12398	1	388	2072	12116	269	162	2418	52	343	12436	115	1	101	1	2	0	0	3140	8	0	2	78	4	3	121223	50186	924	697	491	10000	10000	50010	121379	121447	121402	121348	121541
60024	121554	910	1	0	0	0	0	2580	2243	1	0	1368	1	136	121345	2241	121282	25	70286	50198	10101	10000	40010	10000	10000	1074567	4597468	4638931	121312	0	121430	121395	113255	3	113675	60010	30020	20000	10000	60020	20000	10000	121094	121390	1	1	50021	10	9	10	40010	10000	10000	0	10	12429	1	383	2100	12023	402	113	2388	308	340	12448	91	1	124	1	0	1	0	3140	5	0	5	78	4	2	121181	50190	772	865	738	10000	10000	50010	121403	121029	121471	121339	121234
60024	121412	912	1	0	1	1	0	2677	2295	1	0	1432	1	108	120729	2205	120929	25	70319	50208	10051	10000	40010	10000	10000	1078500	4609926	4610122	121417	0	121492	121555	113338	3	113957	60010	30020	20000	10000	60020	20000	10000	121442	121105	1	1	50021	10	9	10	40010	10000	10000	0	10	12437	1	386	2047	12031	410	116	2450	236	349	12424	84	1	71	1	0	0	0	3140	5	0	4	78	4	2	120862	50206	562	754	633	10000	10000	50010	121647	121561	121318	121358	121266
60024	121413	911	1	1	0	0	0	2604	2239	2	0	1248	1	236	121358	2194	121263	25	70283	50260	10116	10000	40010	10000	10000	1071192	4598658	4628963	121370	0	121443	121279	113547	3	113742	60010	30020	20000	10000	60020	20000	10000	121656	121227	1	1	50021	10	9	10	40010	10000	10000	0	10	12414	1	328	2110	12018	397	112	2407	64	325	12428	111	1	81	1	22	0	0	3140	5	0	4	78	4	4	121133	50212	647	657	753	10000	10000	50010	121555	121820	121557	121702	120594
60024	121533	912	1	1	0	1	0	2589	2228	1	0	1296	1	236	121542	2228	120799	25	70310	50230	10086	10000	40010	10000	10000	1074495	4586694	4629435	121276	0	121370	121525	113436	3	113963	60010	30020	20000	10000	60020	20000	10000	120702	121524	1	1	50021	10	9	10	40010	10000	10000	0	10	12434	2	380	2095	12019	400	117	2443	56	337	12437	94	1	101	1	0	5	0	3140	5	0	2	78	5	2	121263	50208	833	760	431	10000	10000	50010	121628	121208	121336	121242	121206
60024	121439	909	1	0	0	1	0	2507	2263	1	0	1488	1	216	121778	2256	121064	25	70271	50218	10102	10000	40010	10000	10000	1076475	4596421	4625227	121604	3	121343	121498	113319	3	114232	60010	30020	20000	10000	60020	20000	10000	121486	121595	1	1	50021	10	9	10	40010	10000	10000	0	10	12434	1	385	2045	12072	413	114	2424	184	322	12434	85	1	86	1	0	0	0	3140	5	0	5	78	5	2	121338	50186	746	676	646	10000	10000	50010	121522	121287	121365	121592	121338
60024	121158	909	1	1	0	1	0	2348	2235	1	0	1144	1	256	121365	2259	121098	25	70250	50242	10084	10000	40010	10000	10000	1074081	4603992	4627814	121299	0	121526	121688	113367	3	114011	60010	30020	20000	10000	60020	20000	10000	121782	121252	1	1	50021	10	9	10	40010	10000	10000	0	10	12421	2	345	2104	12068	399	111	2420	90	340	12412	98	1	79	1	0	0	0	3140	5	0	4	78	5	5	121088	50224	685	682	532	10000	10000	50010	121310	121363	121550	121429	121448
60024	121161	909	1	1	0	1	0	2557	2255	1	0	1352	1	92	121241	2246	121286	25	70316	50224	10114	10000	40161	10000	10000	1076493	4602509	4631502	121457	0	121215	121228	113376	3	113935	60010	30020	20000	10000	60020	20000	10000	121672	121466	1	1	50021	10	9	10	40010	10000	10000	0	10	12412	1	378	2082	12011	403	112	2425	196	325	12420	83	1	76	1	0	0	0	3140	8	0	6	78	2	5	121191	50194	730	693	711	10000	10000	50010	121339	121459	121421	121586	121495

Test 4: throughput

Count: 8

Code:

  ldp d0, d1, [x6, #0x10]!
  ldp d0, d1, [x7, #0x10]!
  ldp d0, d1, [x8, #0x10]!
  ldp d0, d1, [x9, #0x10]!
  ldp d0, d1, [x10, #0x10]!
  ldp d0, d1, [x11, #0x10]!
  ldp d0, d1, [x12, #0x10]!
  ldp d0, d1, [x13, #0x10]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3765

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	1f	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160214	30145	225	0	0	0	0	0	0	9367	0	2229	1	1360	67	176	30195	2185	123	734	588	1794	25	160230	80224	80000	80120	80014	401109	1332868	1	120	30148	30026	29988	10025	7	9942	160132	200	160048	200	160048	30260	30090	1	1	80201	100	99	14	100	100	80000	80000	1	100	82487	27	2229	3216	0	82070	2371	110	2404	790	2370	84602	489	121	2328	2764	19	3	4	1	1	1	5117	0	16	0	0	29956	31	80145	120	320	72	80000	80000	80100	30071	30158	30112	30177	30188
160204	30182	225	0	0	0	0	0	0	9456	0	2226	1	1440	46	168	30145	2190	132	648	811	1861	25	160233	80246	80000	80120	80015	401068	1335332	1	126	29997	30192	30241	10118	6	10060	160133	200	160048	200	160040	30058	30160	1	1	80201	100	99	14	100	100	80000	80000	0	100	82411	0	2220	3057	0	82472	2360	108	2392	736	3138	84508	618	116	2228	2994	18	3	4	1	1	1	5117	0	16	0	0	30052	19	80136	381	262	81	80000	80000	80100	30106	30040	30107	30204	30210
160204	30074	226	0	0	0	0	0	0	9729	0	2249	1	1352	62	276	30159	2182	140	636	587	1867	25	160216	80245	80000	80120	80012	400999	1333344	1	138	30120	30090	29748	9725	7	9976	160141	200	160040	200	160048	30145	30132	1	1	80201	100	99	11	100	100	80000	80000	0	100	82447	19	2263	2814	0	81160	2344	109	2400	736	2859	84581	678	120	2215	3140	0	3	4	1	1	1	5118	0	16	0	0	29996	24	80133	324	370	82	80000	80000	80100	30186	29699	30113	30196	30191
160204	30188	225	1	0	1	0	0	0	9910	0	2231	1	1640	46	280	30073	2216	116	596	721	1792	25	160223	80236	80000	80124	80016	401067	1340191	1	128	30203	30296	30174	10038	6	10091	160132	200	160040	200	160048	30089	30209	1	1	80201	100	99	18	100	100	80000	80000	0	100	82396	0	2274	3092	0	82364	2323	109	2425	750	2748	84792	630	110	2113	2429	0	3	4	1	1	1	5118	0	16	0	0	30195	21	80125	294	292	113	80000	80000	80100	30199	30256	30061	30163	30209
160204	30146	227	0	0	0	0	0	0	9637	0	2251	1	1640	61	180	30025	2189	123	477	646	1702	25	160235	80244	80000	80120	80015	401069	1326892	1	102	30027	30191	30016	10100	7	10122	160133	200	160048	200	160000	30026	30168	1	1	80201	100	99	14	100	100	80000	80000	0	100	82415	19	2254	2813	0	82143	2336	108	2427	752	3021	84695	650	111	2128	2668	0	3	4	0	0	0	5110	1	17	1	1	30164	30	80108	256	179	86	80000	80000	80100	30183	30221	29907	30017	30170
160204	30109	225	0	0	0	0	0	0	9806	0	2231	1	1512	58	204	29791	2191	76	591	555	1663	25	160199	80219	80000	80100	80000	401013	1326277	1	89	30173	30015	30063	10158	3	10202	160100	200	160000	200	160000	30039	30236	1	1	80201	100	99	3	100	100	80000	80000	0	100	82411	19	2228	2932	0	82192	2341	107	2432	738	2628	84609	682	95	2384	2600	19	3	4	0	0	0	5110	1	16	1	1	30110	19	80130	395	318	75	80000	80000	80100	29741	29990	30264	30140	29985
160204	30099	225	1	0	1	0	0	0	9856	0	2211	1	1352	61	236	30092	2196	131	596	527	1746	25	160204	80199	80000	80100	80000	400971	1333932	1	96	30231	30192	30106	10017	3	10163	160100	200	160000	200	160000	30171	30088	1	1	80201	100	99	12	100	100	80000	80000	0	100	82402	0	2300	2565	0	82333	2320	104	2416	792	2854	84616	676	96	2070	3009	0	3	4	0	0	0	5110	1	16	1	1	30149	31	80079	318	279	75	80000	80000	80100	30149	30293	30208	29775	30262
160204	29976	225	0	0	0	0	0	0	9322	0	2203	1	1672	63	172	30249	2170	120	655	606	1875	25	160188	80196	80000	80100	80000	401026	1328320	1	132	30103	30076	30268	9975	3	10241	160100	200	160000	200	160000	30148	30211	1	1	80201	100	99	7	100	100	80000	80000	0	100	82421	19	2269	3055	0	82509	2364	107	2431	752	2575	84772	619	100	2016	2724	19	3	4	0	0	0	5110	1	16	1	1	30056	18	80111	332	308	74	80000	80000	80100	30155	30170	30186	30084	30048
160204	30110	225	1	0	1	0	0	0	9941	0	2228	1	1648	59	180	29961	2207	169	486	516	1885	25	160204	80205	80000	80100	80000	401039	1335293	1	127	30044	30219	30120	9595	3	10106	160100	200	160000	200	160000	30250	30148	1	1	80201	100	99	15	100	100	80000	80000	0	100	82453	27	2204	2528	0	82285	2354	107	2424	516	2985	84750	611	108	2200	2562	19	3	4	0	0	0	5110	1	16	1	1	30121	12	80093	385	274	94	80000	80000	80100	30193	30111	30109	30141	30127
160204	29978	226	0	0	0	0	0	0	9443	0	2226	1	1480	61	136	30145	2176	155	514	650	1698	25	160217	80200	80000	80100	80000	401025	1325323	1	110	30070	30120	30100	10091	3	9812	160100	200	160000	200	160000	30109	30160	1	1	80201	100	99	15	100	100	80000	80000	0	100	82453	27	2221	2774	0	81868	2361	107	2406	770	3286	85020	573	127	1767	2620	19	3	4	0	0	0	5110	1	16	1	1	30152	18	80114	386	330	68	80000	80000	80100	29995	30120	30226	30156	30096

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3764

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	67	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160034	29787	226	1	0	0	0	0	9879	2245	1	1232	73	224	30160	2230	94	470	685	1867	25	160120	80152	80000	80010	80000	400558	1335665	0	1	107	30311	29992	29994	10102	0	3	10114	160010	20	160000	20	160000	30116	29902	1	1	80021	10	9	11	10	10	80000	80000	1	10	82444	19	2286	2811	0	82324	2310	112	2419	734	2799	84261	703	106	2210	2768	19	3	4	0	5020	0	13	16	0	0	3	12	10	30114	26	80104	404	276	73	80000	80000	80010	30164	30189	30267	30175	29895
160024	30055	225	2	0	0	0	0	9756	2249	1	1456	76	212	30132	2184	101	646	580	1975	25	160114	80122	80000	80010	80000	400528	1336662	0	1	110	29918	30214	29991	10041	0	3	10297	160010	20	160000	20	160000	30232	30016	1	1	80021	10	9	24	10	10	80000	80000	0	10	82417	19	2308	2615	0	82490	2353	105	2420	744	2753	84868	600	110	1994	2134	19	6	4	0	5020	0	9	16	0	0	3	11	10	30209	19	80137	388	346	76	80000	80000	80010	30291	30226	30072	29976	30087
160024	30063	225	1	1	1	0	0	8540	2252	1	1464	71	184	29679	2210	127	263	307	1853	25	160135	80135	80000	80010	80000	400502	1329488	0	1	107	29992	30156	30191	9909	0	3	10029	160010	20	160000	20	160000	30113	29929	1	1	80021	10	9	20	10	10	80000	80000	0	10	82430	19	2220	2833	0	81928	2349	110	2405	746	3119	84523	619	49	2368	2712	19	3	4	0	5020	0	9	16	0	0	3	9	9	30052	21	80126	376	258	41	80000	80000	80010	30033	29948	30203	29694	30241
160024	29930	225	1	0	1	0	0	9797	2254	1	1448	77	280	30087	2225	106	735	550	1982	25	160142	80125	80000	80010	80000	400518	1328744	0	1	102	30009	29697	30094	10073	0	3	10022	160010	20	160000	20	160000	30144	30203	1	1	80021	10	9	15	10	10	80000	80000	0	10	82428	19	2299	2555	0	81884	2348	107	2429	752	3122	84604	632	104	2414	2310	19	3	4	0	5020	0	8	16	0	0	3	12	12	30219	20	80112	364	319	35	80000	80000	80010	30106	30182	29991	30006	29653
160024	30152	226	1	1	0	0	0	9966	2227	1	1400	54	256	29975	2246	128	481	509	1760	25	160129	80120	80000	80010	80000	400490	1332083	1	1	113	30026	30013	30217	10001	0	3	10206	160010	20	160000	20	160000	30222	29863	1	1	80021	10	9	14	10	10	80000	80000	0	10	82418	19	2275	2864	0	82293	2321	108	2478	734	2224	84323	581	106	965	2727	19	4	4	0	5020	0	11	16	0	0	3	9	11	30161	27	80107	360	322	108	80000	80000	80010	30128	30156	30013	29753	30177
160024	30082	223	1	1	0	0	0	9925	2243	1	1608	62	256	30138	2207	119	715	626	1845	25	160137	80128	80000	80010	80000	400672	1341050	1	1	97	29760	30261	30194	9806	0	3	10059	160010	20	160000	20	160000	30111	30028	1	1	80021	10	9	6	10	10	80000	80000	0	10	82439	19	2286	2410	0	82273	2314	109	2393	752	2744	84413	677	87	2060	2734	19	3	4	0	5020	0	7	16	0	0	3	10	10	29950	17	80115	279	327	97	80000	80000	80010	30074	30151	30219	30084	30166
160024	29990	224	1	1	1	0	0	9579	2248	1	1424	58	180	29942	2179	113	669	604	1869	25	160114	80130	80000	80010	80000	400462	1330561	0	1	111	30347	30153	30019	9907	0	3	10162	160010	20	160000	20	160000	29742	29929	1	1	80021	10	9	9	10	10	80000	80000	0	10	82464	19	2300	2330	0	81802	2332	107	2403	1044	2870	84585	481	93	1953	2290	19	40	4	0	5020	0	8	16	0	0	3	10	9	29819	23	80100	388	266	98	80000	80000	80010	29962	30020	30195	30059	30260
160024	30071	225	1	0	1	0	0	9831	2260	1	1384	64	268	30264	2209	99	480	643	1741	25	160130	80119	80000	80010	80000	400521	1336621	0	1	90	30200	30027	30077	10064	0	3	10039	160010	20	160000	20	160000	30035	30197	1	1	80021	10	9	21	10	10	80000	80000	0	10	82424	19	2320	2349	0	82442	2345	103	2409	754	2710	84474	646	97	2483	2453	19	5	4	0	5020	0	8	16	0	0	3	11	10	30191	20	80122	281	329	94	80000	80000	80010	30077	30058	30147	30061	30157
160024	30012	226	1	1	0	0	0	9460	2242	1	1416	56	184	30045	2214	110	557	610	1536	25	160132	80145	80000	80010	80000	400508	1333361	0	1	85	29974	30309	30127	9996	0	3	10070	160010	20	160000	20	160000	30213	30013	1	1	80021	10	9	6	10	10	80000	80000	0	10	82431	19	2236	3118	0	82379	2323	104	2418	752	2808	84671	640	119	2284	2644	19	0	4	0	5020	0	7	16	0	0	3	11	10	30098	18	80133	330	307	117	80000	80000	80010	30125	29966	30253	30162	30029
160024	29935	222	1	1	1	0	0	8922	2273	1	1400	53	212	30066	2205	133	493	594	1693	25	160122	80131	80000	80010	80000	400499	1326984	0	0	117	30133	30155	30197	9956	0	3	10190	160010	20	160000	20	160000	30081	29850	1	1	80021	10	9	15	10	10	80000	80000	0	10	82428	19	2315	3216	0	82663	2347	108	2414	790	2789	84445	482	119	2048	3003	19	3	4	0	5020	0	9	16	0	0	3	11	9	30316	22	80112	395	339	95	80000	80000	80010	30072	30234	29846	30128	30215

LDP (pre-index, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations