Firestorm: LDP (pre-index, Q) measurements

Code:

  ldp q0, q1, [x6, #0x10]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	1e	20	22	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1041	8	0	0	0	0	79	20	1	0	8	1025	0	0	0	1	12	25	3000	1000	2000	1000	2000	24724	45128	1	1015	1040	1041	728	3	773	3000	2000	2000	1040	1040	1	1	1001	1000	1000	0	2025	0	0	54	2027	30	0	24	0	30	27	2049	86	7	13	53	0	4	73	2	16	1	1	1037	2	1000	31	27	2000	1000	1041	1042	1041	1041	1042
2004	1041	8	0	0	0	0	46	15	1	3	0	1025	9	0	2	0	17	25	3000	1000	2000	1000	2000	24672	45206	1	1016	1041	1041	729	3	773	3000	2000	2000	1040	1040	1	1	1001	1000	1000	0	2016	0	0	53	2029	24	0	24	0	20	10	2028	28	6	14	61	0	1	73	1	16	1	1	1037	1	1000	26	30	2000	1000	1042	1041	1041	1041	1041
2004	1040	7	0	0	0	0	73	28	1	1	40	1025	30	0	8	0	17	25	3000	1000	2000	1000	2000	24628	45234	1	1015	1041	1041	729	3	773	3000	2000	2000	1040	1040	1	1	1001	1000	1000	0	2028	0	1	66	2041	10	0	23	0	18	24	2027	28	4	19	37	0	0	73	1	16	1	1	1038	0	1000	25	29	2000	1000	1041	1041	1041	1041	1067
2004	1144	8	0	0	0	0	61	56	1	2	0	1025	9	10	6	2	15	25	3000	1000	2000	1000	2000	24264	45212	1	1015	1040	1040	728	3	773	3000	2000	2000	1040	1040	1	1	1001	1000	1000	0	2023	0	2	45	2041	10	0	20	0	16	15	2029	40	6	9	69	0	0	73	1	16	1	1	1037	1	1000	28	19	2000	1000	1042	1042	1041	1041	1041
2004	1040	8	0	0	0	0	103	22	1	0	0	1025	9	8	0	6	15	25	3000	1000	2000	1000	2000	24592	45188	1	1016	1041	1040	728	3	773	3000	2000	2000	1040	1041	1	1	1001	1000	1000	0	2052	0	1	85	2041	32	0	41	0	16	28	2054	57	9	19	77	0	1	73	1	16	1	1	1037	0	1000	29	31	2000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	0	60	25	1	3	0	1025	21	0	1	2	11	25	3000	1000	2000	1000	2000	24644	45121	1	1015	1041	1041	728	3	774	3000	2000	2000	1040	1040	1	1	1001	1000	1000	0	2026	0	1	77	2020	16	0	26	0	14	16	2061	52	6	31	53	0	0	73	1	16	1	1	1037	0	1000	16	17	2000	1000	1041	1042	1041	1041	1041
2004	1040	8	0	0	0	0	38	15	1	1	0	1026	13	0	0	1	12	25	3000	1000	2000	1000	2000	24860	45204	1	1015	1040	1040	729	3	773	3000	2000	2000	1040	1040	1	1	1001	1000	1000	0	2034	0	5	77	2025	16	1	38	0	0	13	2022	34	6	13	61	0	0	73	1	16	1	1	1038	1	1000	19	22	2000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	0	0	0	51	15	1	2	0	1025	10	16	3	10	15	25	3000	1000	2000	1000	2000	24624	45173	1	1016	1040	1040	729	3	773	3000	2000	2000	1040	1040	1	1	1001	1000	1000	0	2026	0	1	95	2044	21	0	16	0	16	46	2034	34	6	20	37	0	0	73	1	16	1	1	1038	1	1000	20	17	2000	1000	1041	1041	1041	1042	1041
2004	1040	7	0	0	0	0	53	16	1	7	0	1025	0	0	0	5	16	25	3000	1000	2000	1000	2000	24388	45280	1	1016	1040	1040	728	3	773	3000	2000	2000	1040	1040	1	1	1001	1000	1000	0	2016	0	0	78	2039	11	0	29	0	18	39	2043	38	6	23	29	0	0	73	1	16	1	1	1038	0	1000	22	20	2000	1000	1041	1041	1042	1041	1041
2004	1040	8	0	0	0	1	47	13	1	2	0	1026	6	0	0	0	12	25	3000	1000	2000	1000	2000	24852	45198	1	1015	1040	1040	728	3	773	3000	2000	2000	1041	1040	1	1	1001	1000	1000	0	2014	0	3	62	2027	22	0	20	0	20	9	2033	34	6	9	29	0	0	73	1	16	1	1	1038	0	1000	17	22	2000	1000	1041	1041	1041	1041	1042

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp q0, q1, [x6, #0x10]!
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1300

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3a	3e	3f	40	43	46	49	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60223	121247	903	1	0	1	1	1	0	0	0	2564	2223	1	1416	0	212	121484	2191	0	232	200	99916	110907	25	80430	50308	10108	20000	40100	10000	20000	13991652	5794636	3503488	1	121119	0	121175	121255	113598	3	113791	70100	30200	20000	10000	60200	20000	10000	121539	121314	1	1	50201	100	99	100	40100	10000	10000	0	100	22404	0	387	2282	22244	393	116	2449	76	500	22612	93	174	257	0	0	0	0	0	3210	2	16	1	1	121059	50208	713	514	323	20000	50100	121296	121234	121537	121326	121336
60204	120508	908	0	0	0	0	0	0	0	0	2789	2226	1	1272	0	140	121471	2217	0	218	190	99901	110937	25	80448	50344	10112	20000	40100	10000	20000	13987892	5783980	3505347	0	121129	0	121201	121103	113259	3	113582	70100	30200	20000	10000	60200	20000	10000	121325	121061	1	1	50201	100	99	100	40100	10000	10000	0	100	22404	0	330	2277	22208	355	115	2438	74	482	22598	109	202	272	0	0	0	0	0	3210	1	16	1	1	121061	50182	603	628	275	20000	50100	121180	121297	121233	121394	121316
60204	121362	909	0	0	0	0	0	0	0	0	2551	2262	1	1224	0	172	121172	2264	0	186	232	99968	110900	25	80430	50316	10117	20000	40100	10000	20000	13980557	5783068	3501467	0	121402	0	121574	121154	113563	3	113717	70100	30200	20000	10000	60200	20000	10000	121122	121258	1	1	50201	100	99	100	40100	10000	10000	0	100	22412	0	334	2268	22239	403	114	2416	242	524	22642	99	190	299	0	0	3	0	0	3210	1	16	1	1	121250	50242	688	586	310	20000	50100	121313	121405	121394	121197	121298
60204	121318	907	0	0	0	0	0	0	0	0	2762	2257	1	1224	0	224	121066	2221	0	256	212	99767	111075	25	80394	50344	10101	20000	40100	10000	20000	13976934	5791852	3498917	0	121295	0	121170	121146	113488	3	113863	70100	30296	20000	10000	60200	20000	10000	121307	121377	1	1	50201	100	99	100	40100	10000	10000	0	100	22408	0	360	2276	22380	421	115	2422	216	510	22598	106	220	302	0	0	0	0	0	3210	1	16	1	1	121118	50170	600	620	304	20000	50100	121466	121406	121519	121441	121236
60204	121300	907	0	0	0	0	0	0	0	0	2445	2263	1	1392	0	196	121278	2196	0	212	228	100040	110851	25	80442	50282	10113	20000	40100	10000	20000	13990058	5792092	3497878	0	121073	0	121232	121378	113470	3	113705	70100	30200	20000	10000	60200	20000	10000	121069	121241	1	1	50201	100	99	100	40100	10000	10000	0	100	22420	0	382	2300	22217	350	116	2417	244	542	22618	103	206	266	0	0	0	0	0	3210	1	16	1	1	121127	50228	785	583	370	20000	50100	121374	121086	121218	121432	121391
60204	121242	909	1	0	0	1	0	0	0	0	2844	2245	1	1392	1	116	121323	2263	0	232	236	100215	111014	25	80466	50320	10119	20000	40100	10000	20000	13976385	5792716	3499732	0	121431	0	121291	121473	113526	3	113592	70100	30200	20000	10000	60200	20000	10000	121282	121004	1	1	50201	100	99	100	40100	10000	10000	0	100	22428	8	382	2303	22290	404	117	2430	150	537	22642	104	212	326	0	1	2	0	0	3210	1	16	1	1	121384	50240	780	534	298	20000	50100	121307	121417	121406	121436	121201
60204	121399	908	1	0	0	0	0	0	0	0	2820	2278	1	1400	1	504	121323	2228	0	188	192	99938	110894	25	80466	50296	10106	20000	40100	10000	20000	13986397	5797420	3503304	0	121018	0	121175	121198	113470	3	113790	70100	30200	20000	10000	60200	20000	10000	121559	121320	1	1	50201	100	99	100	40100	10000	10000	0	100	22430	1	376	2300	22248	403	115	2435	256	536	22620	122	212	341	0	0	0	0	0	3210	1	16	1	1	121152	50200	628	598	363	20000	50100	121245	121205	121219	121310	121123
60204	121368	909	1	0	0	0	0	0	0	0	2504	2238	1	1168	1	112	121440	2216	0	206	234	100030	111055	25	80460	50322	10113	20000	40100	10000	20000	14010724	5788396	3502660	0	121046	0	121196	121183	113565	3	113999	70100	30200	20000	10000	60200	20000	10000	121450	121541	1	1	50201	100	99	100	40100	10000	10000	0	100	22432	8	380	2328	22266	402	116	2425	50	542	22628	111	168	314	0	0	0	0	0	3210	1	16	1	1	121053	50246	751	608	401	20000	50100	121349	121283	121323	121393	121460
60204	121458	909	1	0	0	0	0	0	0	0	2564	2225	1	1264	1	196	121288	2184	0	232	232	99775	110809	25	80439	50276	10088	20000	40100	10000	20000	13976089	5789212	3496871	0	121255	0	121272	121306	113280	3	113791	70100	30296	20000	10000	60200	20000	10000	121366	121370	1	1	50201	100	99	100	40100	10000	10000	0	100	22423	9	386	2223	22275	324	114	2422	50	544	22630	113	202	365	0	0	0	0	0	3210	1	16	1	1	121267	50234	783	644	290	20000	50100	121179	121298	121343	121215	121087
60204	121301	909	1	0	1	0	0	1	0	0	2534	2235	1	1376	1	216	121046	2213	0	206	196	99861	111077	25	80361	50322	10115	20000	40100	10000	20000	14017155	5798860	3499916	0	121413	0	121353	121213	113512	3	113638	70100	30200	20000	10000	60200	20000	10000	121250	121295	1	1	50201	100	99	100	40100	10000	10000	0	100	22406	8	349	2335	22278	358	112	2417	56	569	22639	120	198	290	0	0	1	0	0	3210	1	16	1	1	121193	50220	789	599	337	20000	50100	121272	121312	121413	121164	121270

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1249

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	18	19	1e	1f	20	22	29	3a	3e	3f	40	43	46	49	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60043	121436	907	1	1	0	0	0	0	0	2808	0	2337	1	1400	0	148	121271	2185	0	206	242	97571	110449	25	80295	50192	10098	20000	40010	10000	20000	13992749	5803276	3500519	0	0	121287	0	121164	121421	113234	3	113802	70010	30020	20000	10000	60020	20000	10000	120983	120754	1	1	50021	10	9	10	40010	10000	10000	0	10	22488	1	390	2297	22212	407	113	2481	120	666	22610	108	92	83	0	0	0	0	0	3140	0	0	0	18	17	0	14	5	120956	50210	650	571	334	20000	50010	121372	121428	121348	121328	121195
60024	121369	909	0	0	0	0	0	0	0	2818	0	2209	1	1400	1	232	121302	2216	0	202	180	97690	111032	25	80337	50208	10110	20000	40010	10000	20000	14017761	5784796	3479385	1	0	121341	0	120664	121142	113486	3	112911	70010	30204	20000	10000	60020	20000	10000	121401	121132	1	1	50021	10	9	10	40010	10000	10000	0	10	22437	8	333	2163	22272	402	110	2394	58	508	22611	40	234	293	0	0	2	0	0	3140	0	0	0	4	17	0	14	5	120904	50194	626	562	394	20000	50010	121202	121275	121233	121296	121071
60024	121281	911	1	0	0	0	0	0	0	2560	0	2250	1	1440	1	276	120612	2200	0	202	262	97594	111034	25	80331	50246	10035	20000	40010	10000	20000	14022721	5792188	3501487	1	0	121348	0	121269	121262	112748	3	113959	70010	30020	20000	10000	60020	20000	10000	121315	121119	1	1	50021	10	9	10	40010	10000	10000	0	10	22421	0	334	2310	22221	521	113	2416	66	541	22603	111	178	287	0	0	0	0	0	3140	0	0	0	6	17	0	6	17	121194	50164	405	662	280	20000	50010	121200	121128	121242	120437	121505
60024	121095	908	0	0	0	0	0	0	0	2829	0	2243	1	1424	2	260	121469	2239	2	74	72	96894	110966	25	80388	50242	10136	20016	40496	10000	20000	13982088	5770156	3500165	1	0	121193	0	120964	121423	113323	3	113888	70010	30020	20000	10000	60020	20000	10000	121208	120642	1	1	50021	10	9	10	40010	10000	10000	0	10	22410	0	382	2323	22192	420	112	2414	264	420	22608	63	208	323	0	0	0	0	0	3140	0	0	0	17	17	0	17	6	120341	50210	587	568	303	20000	50010	120679	121310	121149	121159	121369
60024	120524	904	0	0	0	0	0	0	0	2537	0	2288	1	1400	2	192	121250	2212	1	224	172	97681	111055	25	80382	50222	10126	20000	40010	10000	20000	13957861	5798812	3504495	0	0	121266	0	121418	121246	113670	3	113784	70010	30020	20068	10000	60020	20000	10000	121345	121126	1	1	50021	10	9	10	40010	10000	10000	0	10	22419	8	365	2299	22220	417	112	2432	58	562	22632	95	213	362	0	1	0	0	0	3140	0	0	0	17	17	0	17	17	121208	50204	604	180	142	20000	50010	120566	120666	121200	121430	121032
60024	121536	902	2	1	0	0	0	0	0	2417	0	2333	1	1216	0	264	121258	2280	0	218	177	97716	110863	25	80229	50070	10096	20000	40010	10000	20000	13909274	5753212	3500374	1	0	121082	0	121227	120731	113521	3	113849	70010	30020	20000	10000	60020	20000	10000	121184	121345	1	1	50021	10	9	10	40010	10000	10000	0	10	22490	16	395	2257	22229	409	109	2479	60	538	22620	116	222	347	0	4	2	0	0	3140	0	0	0	4	17	0	17	17	121224	50256	825	170	273	20000	50010	121257	121120	121436	121666	121369
60024	121286	908	1	0	0	1	0	0	0	2806	0	2274	1	1320	2	196	121346	2202	1	212	198	97558	110230	25	80379	50222	10119	20000	40010	10000	20000	13989833	5787244	3499619	1	0	121188	0	121349	121404	113605	3	113103	70010	30020	20000	10000	60020	20000	10000	121103	121195	1	1	50021	10	9	10	40010	10000	10000	0	10	22483	8	367	2254	22241	402	110	2424	270	536	22622	99	180	269	0	0	0	0	0	3140	0	0	0	14	17	0	5	17	120996	50228	612	597	312	20000	50010	120687	121365	121240	121358	120465
60024	121492	907	1	0	0	0	0	0	0	2851	0	2253	1	1248	2	168	121144	2299	3	76	234	97043	111136	25	80313	50198	10103	20000	40010	10033	20000	14015799	5792716	3501744	1	0	121202	0	121331	121626	113234	3	113937	70010	30020	20000	10000	60020	20250	10000	121323	121487	1	1	50021	10	9	10	40010	10000	10000	0	10	22432	10	413	2282	22287	405	113	2445	50	538	22646	97	210	302	1	0	0	0	0	3140	0	0	1	15	17	0	17	7	120899	50142	225	500	83	20000	50010	121053	120465	121490	121395	120930
60024	121118	908	0	0	0	0	0	0	0	2511	0	2238	1	1392	1	96	121285	2212	0	94	198	97568	111141	25	80322	50226	10101	20000	40010	10000	20000	13989690	5794684	3502047	1	0	121173	0	121612	121042	113478	3	113725	70010	30020	20000	10000	60020	20000	10000	121057	121204	1	1	50021	10	9	10	40010	10000	10000	0	10	22437	8	375	2253	22242	407	112	2415	60	492	22590	91	241	158	1	1	3	0	0	3140	0	0	0	15	17	0	15	7	121049	50190	127	491	324	20000	50010	120991	121370	121008	121425	121463
60024	121333	910	0	0	0	0	0	0	0	2810	0	2339	1	1232	2	172	120825	2262	0	194	222	97807	110313	25	80325	50236	10093	20000	40010	10000	20000	13974095	5787388	3501916	0	0	121332	0	121178	121042	113386	3	113937	70010	30020	20000	10000	60020	20000	10000	121200	121405	1	1	50021	10	9	10	40010	10000	10000	0	10	22443	8	385	2283	22187	398	115	2412	66	497	22636	104	253	314	0	0	0	0	0	3140	0	0	0	15	17	0	17	17	120949	50160	740	572	354	20000	50010	120758	121215	121238	120509	121229

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp q0, q1, [x6, #0x10]!
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1795

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	1e	20	22	24	29	3a	3e	3f	40	43	49	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60223	121525	913	2	0	0	0	0	2489	2223	1	0	1424	4	184	121706	2211	1	1	100328	111779	25	80475	50304	10115	20000	40100	10000	20000	14051313	5775340	3496630	0	122201	0	121769	122045	113206	3	114043	70100	30200	20000	10000	60200	20000	10000	121119	121887	1	1	50201	100	99	100	40100	10000	10000	0	100	22437	33	378	2077	22030	407	114	2445	132	341	22379	110	1	86	2	6	2	0	3210	2	16	3	3	121515	50276	759	627	772	20000	50100	121779	120850	121216	121452	121650
60204	121091	906	4	4	0	0	0	2423	2248	1	0	1472	5	176	121811	2216	0	0	100400	111610	25	80502	50328	10103	20000	40100	10000	20000	14048482	5814076	3519496	1	120616	0	121546	121574	113789	3	114077	70100	30200	20064	10000	60200	20000	10000	121875	122034	1	1	50201	100	99	100	40100	10000	10000	0	100	22451	40	381	2058	22069	358	114	2433	62	300	22402	21	1	56	0	6	2	0	3210	3	16	2	2	121274	50112	636	662	903	20000	50100	120951	121769	122034	121588	121779
60204	121617	911	3	0	0	3	0	2462	2290	1	0	1272	3	184	121539	2291	1	0	99438	111776	25	80463	50282	10114	20000	40100	10000	20000	13946910	5831020	3487958	0	121819	0	121659	121564	113776	3	113773	70100	30200	20000	10000	60200	20000	10000	122071	121893	1	1	50201	100	99	100	40100	10000	10000	0	100	22433	17	353	2101	22029	393	115	2408	64	331	22392	105	0	50	0	0	5	0	3210	2	16	3	3	121429	50244	614	710	754	20000	50100	122066	121790	121677	121855	121896
60204	122010	912	3	3	0	0	0	2432	2255	1	0	1432	2	148	121503	2223	0	1	100303	111721	25	80379	50356	10118	20000	40100	10000	20000	14025582	5823724	3511861	0	121516	0	121890	121875	113813	3	113426	70100	30200	20000	10000	60200	20000	10000	121505	120444	1	1	50201	100	99	100	40100	10000	10000	1	100	22399	18	379	2068	22360	365	116	2485	258	327	22404	93	0	101	0	0	0	0	3210	2	16	2	2	120698	50206	581	570	712	20000	50100	121751	121836	121726	121709	121577
60204	120994	911	2	0	0	2	0	2649	2346	1	0	1152	4	212	122014	2216	0	0	100343	111434	25	80454	50228	10124	20000	40100	10000	20000	14040088	5788444	3514104	0	120933	0	121963	120800	114083	3	114183	70100	30200	20000	10000	60200	20000	10000	121806	121162	1	1	50201	100	99	100	40100	10000	10000	0	100	22492	19	375	2081	22022	368	111	2486	500	339	22401	91	0	105	0	0	0	0	3210	3	16	2	3	121634	50238	623	718	764	20000	50100	121900	121505	121731	121746	121891
60204	121118	915	3	3	0	0	0	2545	2257	1	0	1416	3	124	121842	2297	1	1	100443	111565	25	80400	50206	10097	20000	40100	10000	20000	14023272	5772892	3515682	0	121679	0	121694	121653	114061	3	114189	70100	30200	20000	10000	60200	20000	10000	121757	120958	1	1	50201	100	99	100	40100	10000	10000	0	100	22446	24	338	2113	22046	323	113	2427	132	336	22397	135	1	69	1	0	0	0	3210	3	16	2	2	121367	50262	818	595	902	20000	50100	121049	120925	121736	121903	121776
60204	121786	912	3	3	0	4	0	2012	2247	1	0	1368	3	192	121048	2261	0	0	100197	111663	25	80496	50328	10111	20000	40100	10000	20000	14051367	5800156	3513908	0	121809	0	121657	124502	114600	191	116242	75784	32952	22070	10883	66070	21816	10886	124135	124573	30	1	50201	100	99	100	40100	10000	10000	0	100	22469	17	523	1877	21894	567	112	2401	94	68669	22453	119	1	130	1	0	1	0	3210	3	34	3	2	122154	50274	761	348	595	20000	50100	121765	121634	121939	121825	121767
60204	121556	912	3	0	0	3	0	3352	2236	1	0	1248	4	96	122335	2214	0	0	100569	111771	25	80412	50334	10135	20000	40100	10031	20254	14088445	5812876	3518759	0	121470	0	121709	121838	113862	3	114363	70100	30200	20000	10000	60200	20000	10000	121922	121640	2	1	50201	100	99	100	40100	10000	10000	0	100	22406	27	393	2058	22059	402	111	2396	50	306	22446	107	0	114	1	0	0	0	3238	3	16	2	2	121513	50693	913	419	923	20000	50100	121770	121766	122033	121925	124115
60204	120901	912	4	0	0	1	1	2323	2240	0	1	1440	4	324	122008	2207	0	0	100413	111445	25	80427	50292	10121	20000	40100	10000	20000	14070716	5819740	3513893	0	121769	0	121905	121639	113664	3	114231	70100	30200	20000	10000	60200	20000	10000	122006	122050	1	1	50201	100	99	100	40100	10000	10000	0	100	22429	32	383	2067	22081	402	117	2404	58	330	22388	117	0	72	0	0	0	0	3210	3	16	2	3	121381	50226	800	779	829	20000	50100	122017	122185	121875	121712	121736
60204	122002	913	4	4	0	1	0	2396	2254	0	1	1400	4	252	120825	2228	0	0	100441	111453	25	80394	50282	10137	20000	40100	10032	20000	14024011	5820604	3521014	0	121824	0	121801	122032	114250	3	114387	70100	30200	20188	11107	60950	20000	10000	121418	122271	1	1	50202	100	99	100	40100	10000	10000	0	100	22422	30	375	2063	22061	376	110	2443	262	323	22402	113	2	130	1	6	3	0	3210	3	16	3	3	121668	50246	727	710	826	20000	50100	121557	122288	121637	121795	121698

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1522

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60043	120600	915	3	0	0	0	3	1	0	0	0	2217	0	2296	2	1208	2	304	121476	2346	0	0	97811	111157	25	80286	50230	10085	20000	40010	10000	20000	14004756	5812518	3509081	121288	0	121684	121346	113422	3	113751	70220	30020	20000	10000	60020	20000	10000	121631	121053	1	1	50021	10	9	10	40010	10000	10000	0	10	22426	5	315	2086	22126	387	110	2434	206	311	22445	94	3	96	2	0	2	0	3140	7	17	1	1	121679	50166	638	597	647	20000	50010	121450	121751	121506	121527	121558
60024	121530	910	4	0	4	0	4	0	0	0	0	2148	0	2339	2	1032	3	636	121880	2220	1	1	97560	111241	25	80379	50180	10104	20000	40010	10000	20000	14011232	5790412	3514133	121925	0	121374	121566	113657	3	114186	70010	30020	20000	10000	60020	20000	10000	121498	121257	1	1	50021	10	9	10	40010	10000	10000	0	10	22426	14	389	2065	22097	444	111	2430	648	330	22427	112	3	77	2	0	5	0	3140	1	17	1	1	121644	50192	712	304	727	20000	50010	121242	121441	121462	121813	121435
60024	121355	911	2	0	0	0	0	0	0	0	0	1861	0	2376	2	1048	2	308	121838	2301	0	0	97655	111491	25	80304	50176	10108	20000	40010	10000	20000	13979442	5807548	3495199	121644	0	121447	121768	113588	3	114154	70010	30020	20000	10000	60020	20000	10000	121645	121431	1	1	50021	10	9	10	40010	10000	10000	0	10	22444	17	357	2077	22077	397	109	2442	622	316	22408	85	4	65	2	3	0	0	3140	1	17	2	1	121371	50234	651	637	666	20000	50010	121873	121534	121606	120919	121745
60024	121477	913	4	0	4	0	0	0	0	0	0	1619	0	2260	2	944	1	612	121460	2327	1	1	97943	111313	25	80313	50166	10115	20000	40010	10000	20000	14009910	5813452	3509989	121607	0	121235	121391	113668	3	114492	70010	30020	20000	10000	60020	20000	10000	121516	121527	1	1	50021	10	9	10	40010	10000	10000	0	10	22437	16	342	2071	22080	373	112	2436	622	337	22404	96	3	110	2	0	0	0	3140	1	17	2	1	121696	50238	884	431	835	20000	50010	121583	121887	121529	121766	121584
60024	122029	911	2	0	0	0	0	0	0	0	0	1799	88	2263	2	920	3	364	121606	2229	1	1	97994	111279	25	80274	50208	10100	20000	40010	10000	20000	14013508	5811340	3502534	121379	0	121223	121569	113529	3	114191	70010	30020	20000	10000	60020	20000	10000	121860	121691	1	1	50021	10	9	10	40010	10000	10000	0	10	22450	5	341	2075	22061	396	106	2448	574	310	22431	104	0	97	0	0	23	0	3140	2	17	2	2	121468	50158	527	492	609	20000	50010	121452	120683	121386	121458	121390
60024	121197	911	2	0	0	0	0	0	0	0	0	1892	0	2366	2	1024	2	456	121556	2280	0	0	97740	111333	25	80328	50194	10113	20000	40010	10000	20000	14050242	5813308	3517575	121339	0	121904	121528	113651	3	114075	70010	30020	20000	10000	60020	20000	10000	121534	121559	1	1	50021	10	9	10	40010	10000	10000	0	10	22448	15	310	2089	22080	358	107	2442	560	328	22422	92	3	99	2	9	0	0	3140	2	17	2	2	121381	50208	627	506	827	20000	50010	121964	121255	121602	121799	121548
60024	121810	912	3	0	0	0	0	0	0	0	0	1969	0	2298	2	1016	2	460	121642	2294	1	1	97730	111522	25	80292	50164	10111	20000	40010	10000	20000	14031522	5805436	3518197	121547	0	121762	121943	113571	3	114135	70010	30020	20000	10000	60020	20000	10000	121620	121460	1	1	50021	10	9	10	40010	10000	10000	0	10	22447	6	352	2077	22100	324	110	2430	216	320	22445	68	2	79	2	0	0	0	3140	2	17	2	2	121231	50236	821	511	732	20000	50010	121309	121440	121716	121619	121493
60024	120746	911	2	0	1	0	2	0	0	0	0	1811	0	2348	2	1176	1	468	121888	2210	0	0	97659	111305	25	80247	50206	10105	20000	40010	10000	20000	14009590	5809516	3515976	121489	0	121490	121310	113587	3	114152	70010	30020	20000	10000	60020	20000	10000	121613	121488	1	1	50021	10	9	10	40010	10000	10000	0	10	22429	17	344	2092	22081	378	107	2450	664	309	22408	111	3	95	2	0	0	0	3140	2	17	2	2	121411	50170	698	598	648	20000	50010	121233	121308	121506	121291	121512
60024	121495	910	3	0	2	0	3	0	0	0	0	2059	0	2354	2	1304	1	408	121609	2228	1	1	97880	111579	25	80265	50194	10100	20000	40010	10000	20000	14017604	5801020	3507409	121356	0	121530	121483	113641	3	114055	70010	30020	20000	10000	60020	20000	10000	121826	121998	1	1	50021	10	9	10	40010	10000	10000	0	10	22447	17	364	2073	22089	367	109	2431	618	312	22414	87	3	82	2	14	4	0	3142	2	17	2	2	122105	50174	647	626	823	20000	50010	121663	121454	121362	121613	122180
60024	121629	911	4	0	3	0	3	0	0	0	0	2618	0	2381	2	1072	4	904	121585	2233	1	2	97724	111159	25	80316	50208	10090	20000	40010	10000	20000	13997639	5814364	3514590	121515	0	121680	121764	113752	3	113997	70010	30020	20000	10000	60020	20000	10125	121763	122033	1	1	50021	10	9	10	40010	10000	10000	0	10	22419	17	338	2084	22062	398	111	2454	652	316	22415	121	3	77	2	0	2	0	3140	2	17	3	1	121073	50254	723	523	646	20000	50010	121585	121521	121612	121522	121423

Test 4: throughput

Count: 8

Code:

  ldp q0, q1, [x6, #0x10]!
  ldp q0, q1, [x7, #0x10]!
  ldp q0, q1, [x8, #0x10]!
  ldp q0, q1, [x9, #0x10]!
  ldp q0, q1, [x10, #0x10]!
  ldp q0, q1, [x11, #0x10]!
  ldp q0, q1, [x12, #0x10]!
  ldp q0, q1, [x13, #0x10]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7157

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	1e	1f	20	22	23	24	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160223	57161	429	7	0	0	1	0	0	10842	0	2246	1	0	0	1408	65	180	57568	2198	260	1811	1694	2259	25	241753	81762	160000	80100	160000	403997	2523432	1	1643	57185	0	57111	57180	37042	3	37356	240100	200	160000	200	160000	57368	57237	1	1	80201	100	99	5	100	100	80000	80000	0	100	162436	27	2259	3979	0	163656	2334	107	2435	258	4421	166176	655	93	3305	3445	12	0	0	5110	1	16	1	1	57154	23	81558	415	406	118	160000	80100	57171	57303	57524	57358	57408
160204	57391	428	5	0	5	0	0	0	11540	0	2211	1	0	0	1664	71	176	57364	2175	233	1755	1853	2262	25	241747	81747	160000	80100	160000	403774	2526295	1	1663	57536	0	57380	57338	37411	3	37176	240100	200	160000	200	160000	57480	57264	1	1	80201	100	99	8	100	100	80000	80000	0	100	162431	23	2224	4726	0	163679	2342	110	2436	258	4135	166733	741	101	3225	3944	0	5	0	5110	1	16	1	1	57286	29	81620	418	348	101	160000	80100	57420	57263	57366	57293	57223
160204	57066	431	5	5	0	0	0	0	11108	0	2245	1	0	0	1536	63	184	57164	2249	250	1386	1625	1936	25	241706	81735	160000	80100	160000	403885	2510077	1	1621	57251	0	57277	57119	37203	3	37072	240100	200	160000	200	160000	57315	57292	1	1	80201	100	99	3	100	100	80000	80000	0	100	162577	44	2265	3972	0	163690	2416	112	2433	250	4118	165811	548	113	3457	3662	19	0	0	5110	1	16	1	1	57065	11	81971	440	456	129	160000	80100	57298	57281	57191	57202	57191
160204	57255	430	5	0	0	1	0	0	11279	0	2235	1	0	0	1400	88	164	57254	2209	325	1755	1730	2029	25	241693	81677	160000	80100	160000	404034	2518608	1	1691	57283	0	57304	57195	37153	3	37236	240100	200	160000	200	160000	57136	57242	1	1	80201	100	99	4	100	100	80000	80000	0	100	162445	40	2265	3985	0	163468	2362	110	2430	232	4316	165373	645	76	3444	3351	42	0	0	5110	1	16	1	1	57278	21	81818	314	402	116	160000	80100	57266	57044	57210	57403	57202
160204	57478	429	5	0	0	0	0	0	11110	0	2229	1	0	0	1408	89	116	57158	2183	282	1734	1425	1984	25	241673	81819	160000	80100	160000	403990	2515352	1	1617	57297	0	57303	57390	37050	3	37480	240100	200	160000	200	160000	57002	57222	1	1	80201	100	99	10	100	100	80000	80000	0	100	162443	44	2317	3914	0	163364	2321	113	2432	258	3685	166121	542	129	3776	3735	19	0	0	5110	1	16	1	1	57287	19	81654	448	412	113	160000	80100	57140	57032	57117	57167	57300
160204	57135	428	5	0	5	0	0	0	11171	0	2253	2	0	0	1400	71	136	57210	2220	231	1766	1686	2257	25	241723	81677	160000	80100	160000	404710	2515593	1	1651	57364	0	56894	57376	37025	3	37052	240100	200	160000	200	160000	57033	57182	1	1	80201	100	99	7	100	100	80000	80000	0	100	162459	43	2277	4974	0	163968	2328	112	2414	250	3922	165416	634	117	4124	3707	19	1	0	5110	1	16	1	1	57248	20	81728	544	452	116	160000	80100	57158	57294	57219	57324	57178
160204	57234	429	5	5	0	0	0	0	11018	0	2244	1	0	0	1472	83	272	57318	2202	218	2053	1709	1912	25	241640	81957	160000	80100	160000	404165	2517109	1	1625	57119	0	57154	57237	37153	3	37126	240100	200	160000	200	160000	57211	57318	1	1	80201	100	99	3	100	100	80000	80000	0	100	162459	36	2232	4644	0	164216	2346	112	2408	232	3675	165792	717	125	3524	3235	30	5	0	5110	1	16	1	1	57182	22	81626	449	433	118	160000	80100	57417	57258	57048	56864	57441
160204	57054	428	5	0	5	0	0	0	11161	0	2236	1	0	0	1400	56	252	57263	2202	241	1757	2081	2124	25	241771	81741	160000	80100	160712	403818	2519656	1	1680	57486	0	57233	57351	37110	3	37302	240100	200	160000	200	160000	57138	57270	1	1	80201	100	99	2	100	100	80000	80000	0	100	162448	34	2267	4085	0	163596	2366	113	2420	254	3388	166143	525	149	3828	3622	19	0	0	5110	1	16	1	1	57383	18	81666	495	356	93	160000	80100	56965	57327	57224	57269	57036
160204	57067	428	5	0	0	0	0	0	11327	0	2260	1	0	0	1456	62	252	57304	2203	284	1883	1557	2262	25	241816	81902	160000	80100	160000	404748	2529400	0	1621	57244	0	57339	57136	37195	3	37143	240100	200	160000	200	160000	57420	57343	1	1	80201	100	99	3	100	100	80000	80000	0	100	162439	39	2262	4199	0	162876	2337	115	2439	222	4012	165660	744	104	3407	4520	19	10	0	5110	1	16	1	1	57178	32	81546	389	387	93	160000	80100	57035	57275	57201	57242	57063
160204	57120	428	4	0	4	0	0	0	11247	0	2212	1	0	0	1640	63	228	57212	2204	197	1885	1660	2035	25	241778	81682	160000	80100	160000	403995	2523156	1	1534	57403	0	57189	57101	37121	3	37194	240100	200	160000	200	160000	57262	57038	1	1	80201	100	99	3	100	100	80000	80000	0	100	162518	38	2260	4636	0	163686	2361	113	2428	180	4251	166419	712	100	4135	3660	19	0	0	5126	1	16	1	1	57249	21	81838	456	460	107	160000	80100	56979	57345	56966	57300	57171

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7199

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	23	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	67	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160043	57107	432	6	6	0	0	0	0	0	0	11614	0	2218	1	0	1416	104	244	57848	2168	572	2220	1988	2446	25	241743	81571	160000	80010	160000	403406	2553141	0	0	1633	57744	0	58015	57872	37518	3	37710	240010	20	160000	20	160000	57686	57959	1	1	80021	10	9	6	10	10	80000	80000	0	10	162398	40	2174	4719	0	164292	2349	108	2396	230	5577	166838	766	116	5096	5182	0	0	0	5020	0	0	11	15	11	12	57208	28	81888	374	496	142	160000	80010	57544	57671	57491	57732	57462
160024	57139	430	4	4	4	0	0	0	0	0	11819	0	2230	1	0	1688	70	260	57771	2178	432	2183	1992	1889	25	242054	81665	160000	80010	160000	403299	2550904	0	1	1573	57703	0	57672	57647	37420	3	37526	240010	20	160000	20	160000	57318	57525	1	1	80021	10	9	4	10	10	80000	80000	0	10	162429	26	2194	4601	0	164526	2320	107	2399	258	4788	167127	820	134	3493	3788	24	12	0	5020	0	0	10	15	11	11	57673	29	81542	615	479	141	160000	80010	57731	57399	57653	57601	57688
160024	57428	431	4	0	0	4	0	0	0	0	11686	0	2248	1	0	1480	72	104	57402	2208	456	2276	2177	2728	25	241626	81457	160000	80010	160000	403470	2534881	0	1	1864	57298	0	57445	57655	37329	3	37698	240010	20	160000	20	160000	57745	57683	1	1	80021	10	9	7	10	10	80000	80000	0	10	162416	25	2138	5246	0	164814	2291	109	2391	246	4753	167243	847	132	3970	3871	0	0	0	5020	0	0	12	15	13	13	57342	22	81810	417	569	141	160000	80010	57463	57573	57626	57670	57532
160024	57491	432	4	4	0	4	0	0	0	0	12721	0	2197	1	0	1408	72	268	57835	2173	461	1912	2361	2329	25	241632	81546	160000	80010	160000	403399	2528486	0	1	1711	57264	0	57626	57595	37356	3	37615	240010	20	160000	20	160000	56667	57762	1	1	80021	10	9	8	10	10	80000	80000	0	10	162414	32	2094	4895	0	164340	2279	111	2387	232	4686	166759	768	119	4737	4529	13	4	0	5020	0	0	15	16	14	12	57726	31	81556	546	489	128	160000	80010	57351	57249	57446	57580	57826
160024	57584	431	5	5	0	0	0	0	0	0	11359	0	2227	1	0	1408	98	244	57826	2192	569	1752	2539	2288	25	241733	81639	160000	80010	160000	403548	2539609	0	1	1565	57447	0	57665	57698	37534	3	37635	240010	20	160000	20	160000	57796	57478	1	1	80021	10	9	8	10	10	80000	80000	0	10	162412	40	2184	4540	0	164914	2295	108	2394	510	4543	166837	770	121	3922	5428	24	0	0	5020	0	0	14	16	14	12	57420	23	81619	379	487	149	160000	80010	57532	57468	57553	57658	57716
160024	57300	431	5	0	0	0	0	0	0	0	11782	0	2202	1	0	1616	85	244	57371	2192	516	2079	2183	2544	25	241633	81583	160000	80010	160000	403464	2529621	0	1	1604	57493	0	58034	57670	37562	3	37454	240010	20	160000	20	160000	57528	57832	1	1	80021	10	9	20	10	10	80000	80000	0	10	162423	42	2208	5883	0	165440	2306	109	2383	272	4779	167507	751	67	5809	4839	21	5	6	5020	0	0	12	16	13	11	57648	27	81646	435	482	132	160000	80010	57607	57587	57333	57596	57510
160024	57568	431	5	0	0	0	0	0	0	0	12595	0	2232	1	0	1632	64	196	57640	2179	555	2139	2396	2314	25	241680	81626	160000	80010	160000	405291	2559539	0	0	1350	57234	0	57543	57568	37447	3	37747	240010	20	160000	20	160000	57322	57687	1	1	80021	10	9	5	10	10	80000	80000	0	10	162438	32	2205	5282	0	164439	2303	111	2404	254	5144	167431	746	138	3990	5667	11	0	0	5020	0	0	11	15	12	14	57395	22	81664	542	523	170	160000	80010	57302	57333	57477	57681	57820
160024	57578	429	5	0	5	0	0	0	0	0	12696	0	2206	1	0	1568	90	504	57569	2199	479	2384	2517	2278	25	241759	81711	160000	80010	160000	403434	2539206	0	1	1565	57747	0	57223	57716	37653	3	37662	240010	20	160000	20	160000	56563	57496	1	1	80021	10	9	6	10	10	80000	80000	0	10	162401	36	2213	4977	0	164636	2292	113	2402	254	4826	167097	870	133	4732	4673	13	0	0	5020	0	0	10	15	14	14	57858	18	81604	611	452	122	160000	80010	57640	57403	57415	57549	57546
160024	57593	434	5	0	0	0	0	0	0	0	11974	0	2192	1	0	1144	77	256	57733	2211	485	1875	2248	2029	25	241651	81603	160000	80010	160000	403601	2532878	0	0	1882	57509	0	57589	57919	37519	3	37622	240010	20	160000	20	160000	57780	57358	1	1	80021	10	9	4	10	10	80000	80000	0	10	162547	36	2253	4623	0	164914	2283	107	2424	266	5142	167227	800	169	5294	4583	13	0	0	5020	0	0	11	16	10	13	57764	22	81648	464	543	174	160000	80010	57756	57545	57504	57655	57444
160024	57608	431	4	0	0	0	0	0	0	0	12223	0	2239	1	0	1496	71	252	57391	2196	444	1907	2329	2207	25	241652	81672	160000	80010	160000	403361	2535446	0	1	1693	57759	0	56969	57663	37555	3	37485	240010	20	160000	20	160000	57402	57431	1	1	80021	10	9	0	10	10	80000	80000	0	10	162422	39	2169	4146	0	164717	2306	107	2409	132	5250	166588	898	148	4349	4637	19	0	0	5020	0	0	12	16	14	10	57331	32	81678	394	429	135	160000	80010	57478	57506	57594	57450	57657

LDP (pre-index, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations