Firestorm: LDP (pre-index, S) measurements

Code:

  ldp s0, s1, [x6, #0x10]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1050	8	1	1	1	0	0	39	12	1	0	0	4	1025	6	0	1	1	14	25	2000	1000	1000	1000	1000	52844	45824	1015	1040	1040	699	3	773	2000	2000	2000	1040	1040	1	1	1001	1000	1000	1032	0	1	41	1026	2	1	16	8	0	1016	58	0	6	19	6	1	0	73	2	16	2	2	1037	1000	26	29	1000	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	0	0	19	15	1	0	0	8	1025	23	0	1	1	13	25	2000	1000	1000	1000	1000	52868	45824	1015	1040	1040	699	3	773	2000	2000	2000	1040	1040	1	1	1001	1000	1000	1016	0	0	16	1016	0	0	16	8	0	1032	35	0	0	23	0	0	0	73	2	16	2	2	1037	1000	32	29	1000	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	0	0	41	42	1	0	1	0	1025	9	0	3	1	7	25	2000	1000	1000	1000	1000	52852	45824	1015	1040	1040	699	3	773	2000	2000	2000	1040	1040	1	1	1001	1000	1000	1030	0	0	42	1014	3	0	24	16	0	1026	19	0	0	15	0	0	0	73	2	16	2	2	1037	1000	26	24	1000	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	1	0	0	18	16	1	0	1	0	1025	6	0	1	2	8	25	2000	1000	1000	1000	1000	52852	45825	1015	1040	1040	699	3	773	2000	2000	2000	1040	1040	1	1	1001	1000	1000	1024	7	0	34	1026	0	0	27	8	7	1026	35	0	6	31	6	1	0	73	2	16	2	2	1037	1000	29	25	1000	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	1	0	0	29	16	1	0	1	0	1025	10	0	1	3	8	25	2000	1000	1000	1000	1000	52860	45824	1015	1040	1040	699	3	773	2000	2000	2000	1040	1040	1	1	1001	1000	1000	1025	7	0	29	1030	1	1	26	16	6	1016	19	0	7	39	7	0	0	73	2	16	2	2	1037	1000	33	33	1000	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	1	0	0	38	16	1	0	2	0	1025	12	0	1	1	8	25	2000	1000	1000	1000	1000	52864	45824	1015	1040	1040	699	3	773	2000	2000	2000	1040	1040	1	1	1001	1000	1000	1023	9	0	31	1064	0	0	17	8	9	1016	15	0	7	19	7	1	0	73	2	16	2	2	1037	1000	48	32	1000	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	0	1	0	0	30	22	1	0	1	0	1025	7	0	1	3	4	25	2000	1000	1000	1000	1000	52848	45825	1015	1040	1040	699	3	773	2000	2000	2000	1040	1040	1	1	1001	1000	1000	1024	7	0	21	1024	2	0	17	8	10	1024	23	0	6	19	7	1	0	73	2	16	2	2	1037	1000	28	42	1000	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	0	0	0	0	42	32	1	0	1	12	1025	19	0	1	1	5	25	2000	1000	1000	1000	1000	52848	45825	1015	1040	1040	699	3	773	2000	2000	2000	1040	1040	1	1	1001	1000	1000	1023	8	0	52	1028	1	0	17	10	7	1016	23	0	6	23	7	0	0	73	2	16	2	2	1037	1000	26	29	1000	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	0	0	0	0	35	18	1	0	2	0	1025	8	0	3	1	7	25	2000	1000	1000	1000	1000	52860	45824	1015	1040	1040	699	3	773	2000	2000	2000	1040	1040	1	1	1001	1000	1000	1024	8	0	56	1029	3	0	28	8	6	1016	27	0	7	19	7	0	0	73	2	16	2	2	1037	1000	45	35	1000	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	0	0	0	28	32	1	0	0	0	1025	3	0	1	2	8	25	2000	1000	1000	1000	1000	52856	45824	1015	1040	1040	699	3	773	2000	2000	2000	1040	1040	1	1	1001	1000	1000	1024	8	0	24	1061	0	0	17	8	7	1022	19	0	6	39	6	1	0	73	2	16	2	2	1037	1000	33	27	1000	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp s0, s1, [x6, #0x10]!
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	24	29	3a	3e	3f	40	43	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60214	120626	906	0	0	0	0	0	0	0	1	0	0	2150	352	2280	1	0	1240	2	132	121556	2217	0	121156	25	70322	50254	10099	10000	40100	10000	10000	1074110	4590983	4587790	1	121420	121305	121462	113699	3	113985	60100	30200	20000	10000	60200	20000	10000	121440	121589	1	1	50201	100	99	100	40100	10000	10000	0	100	12420	0	339	2061	12009	347	113	2431	218	318	12432	89	0	101	0	17	0	0	0	0	3244	4	83	4	4	121232	50230	885	721	739	10000	10000	50100	121261	121897	121390	121459	121290
60204	121415	910	0	0	0	0	0	0	0	0	0	0	2205	0	2269	1	0	1368	2	96	121785	2249	0	121037	25	70424	50270	10108	10000	40100	10000	10000	1078203	4609431	4630804	0	121311	121410	121622	113401	3	113595	60100	30200	20000	10000	60200	20000	10000	121661	121660	1	1	50201	100	99	100	40100	10000	10000	0	100	12434	1	331	2101	12034	354	110	2424	218	328	12426	112	1	106	1	0	0	0	0	0	3233	5	83	4	4	121195	50246	825	744	613	10000	10000	50100	121424	121899	121582	121525	121707
60204	121730	910	1	0	0	0	0	0	0	0	0	0	2139	686	2257	1	0	1344	2	228	121507	2191	0	121786	25	70441	50162	10115	10000	40100	10000	10000	1075503	4607175	4631624	0	121679	121285	121611	113864	3	114149	60100	30200	20000	10000	60200	20000	10000	121620	121882	1	1	50201	100	99	100	40100	10000	10000	0	100	12417	11	390	2089	12086	363	113	2422	182	331	12396	109	1	84	1	9	0	0	0	0	3210	4	83	4	4	121148	50164	850	838	664	10000	10000	50100	121212	121560	121408	121317	121375
60204	121198	906	0	0	0	0	0	0	0	0	0	0	2426	0	2239	1	0	1248	1	236	121442	2231	0	121531	25	70334	50296	10081	10000	40100	10000	10000	1075550	4593158	4624373	0	121530	121419	121460	113258	3	113567	60100	30200	20000	10000	60200	20000	10000	121635	121361	1	1	50201	100	99	100	40100	10000	10000	0	100	12435	2	298	2082	12070	369	114	2479	86	339	12410	85	0	90	0	0	0	0	0	0	3210	4	83	4	4	121572	50196	832	869	764	10000	10000	50100	121328	121619	121435	121569	121484
60204	121570	910	0	0	0	0	0	0	0	0	0	0	2247	0	2287	1	0	1232	1	128	121403	2191	0	121125	25	70385	50312	10101	10000	40100	10000	10000	1079017	4606484	4627931	1	121505	121749	121678	113383	3	114066	60100	30200	20000	10000	60200	20000	10000	121328	121419	1	1	50201	100	99	100	40100	10000	10000	0	100	12418	8	352	2101	12017	357	111	2422	226	315	12437	112	0	83	0	0	1	0	0	1	3210	4	83	4	4	121324	50194	832	552	855	10000	10000	50100	121621	121255	121333	121532	122039
60204	121356	911	0	0	0	0	0	0	0	0	0	0	2227	352	2262	1	0	1240	0	316	121338	2203	0	121022	25	70334	50334	10116	10000	40100	10000	10000	1076297	4602314	4624441	0	121337	121841	121580	113490	3	113936	60100	30200	20000	10000	60200	20000	10000	121440	121676	1	1	50201	100	99	100	40100	10000	10000	1	100	12433	8	343	2095	12058	333	113	2413	184	324	12419	106	0	85	0	0	0	0	0	0	3210	4	83	4	4	121438	50218	739	728	559	10000	10000	50100	121574	121434	121354	121603	121539
60204	121300	911	1	0	1	0	0	0	0	0	0	0	2372	0	2236	1	0	1328	0	236	121575	2208	0	120892	25	70428	50332	10098	10000	40100	10000	10000	1074495	4599517	4626612	0	121484	121525	121309	113360	3	113646	60100	30200	20000	10000	60488	20000	10000	121373	121275	1	1	50201	100	99	100	40100	10000	10000	0	100	12404	0	347	2087	12059	403	113	2427	56	330	12411	110	0	95	0	0	0	0	0	0	3212	4	83	4	4	121005	50190	708	783	327	10000	10000	50100	121441	121376	121352	121208	121288
60204	121572	912	0	0	0	0	0	0	1	1	0	0	2415	0	2271	1	0	1200	0	176	121531	2221	0	121001	25	70403	50284	10094	10000	40100	10000	10000	1074497	4607105	4631267	0	121369	121547	121102	113522	3	113985	60100	30200	20000	10000	60200	20000	10000	121333	121471	1	1	50201	100	99	100	40100	10000	10000	0	100	12406	0	330	2082	12056	359	111	2403	92	330	12422	95	0	96	0	30	2	0	0	0	3210	4	83	4	4	120912	50224	757	776	853	10000	10000	50100	121321	121587	121279	121329	121515
60204	121578	910	0	0	0	0	0	0	0	0	0	0	2330	0	2261	1	0	1352	0	236	121581	2233	0	121248	25	70457	50264	10083	10000	40100	10046	10000	1075739	4609468	4621530	0	121324	121310	121302	113232	3	113944	60100	30200	20000	10000	60200	20000	10000	121487	121486	1	1	50201	100	99	100	40100	10000	10000	0	100	12429	0	340	2107	12091	356	108	2415	204	327	12444	98	0	104	0	0	2	0	0	0	3210	4	83	4	4	121036	50236	790	928	661	10000	10000	50100	121575	121487	121600	121452	121694
60204	121688	911	0	0	0	0	0	0	0	0	0	0	2344	0	2251	1	0	1208	1	144	121341	2197	0	121014	25	70421	50296	10095	10000	40100	10000	10000	1074308	4579451	4641158	0	121462	121701	121727	113426	3	113970	60100	30200	20000	10000	60200	20000	10000	121219	121594	1	1	50202	100	99	100	40100	10000	10000	0	100	12434	0	368	2106	12004	345	111	2422	170	318	12419	118	0	105	0	0	0	0	0	0	3210	4	83	4	4	121345	50198	807	818	648	10000	10000	50100	121314	121741	121321	121495	121324

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1574

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cd	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60034	120358	907	2	0	0	0	0	0	0	2394	0	2259	1	1248	2	200	121854	2204	6	0	120442	25	70379	50270	10133	10000	40010	10000	10000	1075845	4613896	4639756	1	1	121844	121876	121538	112860	3	113432	60010	30020	20000	10000	60020	20000	10000	121728	121740	1	1	50021	10	9	10	40010	10000	10000	0	10	12425	10	371	2089	12081	405	111	2438	228	311	12480	103	4	92	0	0	4	0	3140	0	0	4	78	2	2	121374	50236	945	783	692	10000	10000	50010	121587	121618	121812	120963	121624
60024	121840	912	3	0	0	0	0	0	0	2279	0	2301	1	1200	1	152	121588	2197	5	0	120431	25	70292	50240	10117	10000	40010	10000	10000	1074432	4609304	4651330	0	0	121318	121612	121645	113586	3	114141	60010	30020	20000	10000	60020	20000	10000	121607	121465	1	1	50021	10	9	10	40010	10000	10000	0	10	12434	8	380	2057	12007	402	105	2424	50	318	12422	111	0	77	0	0	0	0	3140	0	0	1	78	2	2	121094	50250	404	860	692	10000	10000	50010	121823	121584	121452	121506	121712
60024	121628	909	1	0	0	0	0	0	0	2376	0	2226	1	1416	1	204	121556	2249	6	0	120928	25	70409	50214	10104	10000	40010	10000	10000	1076844	4605260	4598799	0	1	121501	121670	121046	113787	3	114270	60010	30020	20000	10000	60020	20000	10050	120968	121385	1	1	50021	10	9	10	40010	10000	10000	1	10	12428	16	372	2055	12071	366	108	2416	174	330	12407	90	2	119	0	0	0	0	3172	0	0	2	78	2	2	121162	50174	627	756	760	10000	10000	50010	121512	121361	121700	121359	121662
60024	121606	912	1	0	0	0	0	0	0	2475	0	2262	1	1256	1	280	121537	2216	0	2	121144	25	70289	50130	10123	10000	40010	10000	10000	1076331	4610757	4641433	0	1	121423	121937	121863	113401	3	113962	60010	30020	20000	10000	60020	20000	10050	121570	121861	1	1	50021	10	9	10	40010	10000	10000	0	10	12436	9	350	2097	12019	404	107	2423	254	319	12431	126	4	107	0	0	0	0	3140	0	0	2	78	2	2	121546	50200	936	795	841	10000	10000	50010	121717	121588	121493	120744	120994
60024	121084	910	1	0	1	0	0	0	0	2481	352	2255	1	1248	3	124	121418	2238	2	3	121308	25	70340	50246	10102	10000	40010	10000	10000	1069482	4617074	4641255	0	0	121499	121372	121565	113462	3	114468	60010	30020	20000	10000	60020	20000	10000	121585	121548	1	1	50021	10	9	10	40010	10000	10000	0	10	12488	16	333	2046	12030	372	107	2440	282	326	12424	105	2	105	0	0	0	0	3140	0	0	2	78	2	2	121695	50214	917	890	917	10000	10000	50010	121547	121720	121639	121016	121896
60024	121558	911	2	0	0	0	0	0	0	2204	0	2300	1	1424	2	248	121718	2202	2	1	121177	25	70352	50206	10116	10000	40010	10000	10000	1074693	4620359	4651818	0	0	121601	121696	120893	113078	3	114001	60010	30020	20096	10000	60020	20000	10000	121942	121666	1	1	50021	10	9	10	40010	10000	10000	0	10	12413	18	377	2062	12016	392	110	2444	50	295	12425	51	6	100	0	0	0	0	3140	0	0	2	78	2	2	121518	50162	882	725	732	10000	10000	50010	121532	121398	121031	121983	121475
60024	121634	912	2	2	0	0	0	0	0	2417	0	2294	1	1416	2	240	121625	2255	4	2	121350	25	70382	50284	10104	10000	40010	10000	10000	1079985	4599200	4648292	0	0	121794	121559	121824	113879	3	114041	60010	30020	20000	10000	60020	20000	10000	121460	121378	1	1	50021	10	9	10	40010	10000	10000	0	10	12425	16	369	2054	12033	404	109	2432	254	309	12461	111	1	101	0	0	1	0	3140	0	0	3	78	2	2	121613	50210	795	1078	683	10000	10000	50010	121572	121378	121560	121415	122003
60024	121855	912	2	0	2	0	0	0	0	2354	0	2270	1	1416	3	424	121070	2341	3	2	121300	25	70169	50272	10132	10000	40010	10000	10000	1076133	4604361	4630218	0	1	120912	121887	121235	113710	3	114017	60010	30020	20000	10000	60020	20000	10000	121918	121620	1	1	50021	10	9	10	40010	10000	10000	0	10	12420	18	368	2085	12091	399	108	2414	66	296	12427	106	4	47	0	0	0	0	3140	0	0	2	78	2	2	120720	50228	981	483	931	10000	10000	50010	121714	121757	121445	121296	121589
60024	121442	911	2	0	0	0	0	0	0	2349	0	2275	1	1232	2	100	121081	2202	1	5	121482	25	70364	50252	10099	10000	40010	10000	10000	1071768	4606548	4635800	0	0	121647	121380	121716	113432	3	114378	60010	30020	20000	10000	60020	20000	10000	121747	121517	1	1	50021	10	9	10	40010	10000	10000	0	10	12432	16	336	2048	12091	361	109	2426	210	322	12404	115	5	102	0	0	0	0	3140	0	0	2	78	2	2	121038	50202	396	965	714	10000	10000	50010	121661	121758	121867	121595	120816
60024	121564	911	1	0	0	0	0	0	0	2482	88	2266	1	1248	1	292	121720	2190	6	0	121146	25	70358	50230	10106	10000	40010	10000	10000	1076277	4610874	4645692	0	1	121767	120838	121379	113619	3	113899	60010	30020	20000	10000	60020	20000	10000	121525	121623	1	1	50021	10	9	10	40010	10000	10000	0	10	12416	1	374	2101	11990	368	108	2396	56	300	12398	104	2	97	0	1	8	0	3140	0	0	2	78	2	2	121362	50160	822	917	782	10000	10000	50010	121716	121713	121543	121706	121541

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp s0, s1, [x6, #0x10]!
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1614

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	19	1e	1f	20	22	24	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60214	121270	913	0	2	0	2	2	0	0	2379	0	2257	1	0	1424	0	508	121533	2219	0	0	120338	25	70445	50317	10113	10000	40100	10000	10000	1075703	4573841	4639198	0	121660	0	121495	121722	113788	3	113915	60100	30200	20000	10000	60200	20000	10000	120767	121320	1	1	50201	100	99	100	40100	10000	10000	0	100	12483	5	383	2116	12044	389	110	2406	56	339	12406	98	0	113	0	0	0	3211	3	83	3	3	121303	50254	872	330	341	10000	10000	50100	121471	121666	121689	121613	121781
60204	121483	911	0	1	0	0	0	0	0	2329	0	2223	1	0	1416	0	224	121411	2235	0	0	121368	25	70358	50322	10055	10000	40100	10000	10000	1077161	4601971	4630496	0	121627	0	121408	121616	112675	3	113998	60100	30200	20000	10000	60200	20000	10000	121715	121858	1	1	50201	100	99	100	40100	10000	10000	0	100	12414	2	381	2151	12012	389	110	2424	76	330	12405	42	0	99	0	0	0	3211	2	83	2	2	121350	50188	636	270	669	10000	10000	50100	121695	121507	121589	120655	121492
60204	121285	909	0	1	0	0	0	0	0	2471	0	2273	1	0	1400	1	212	121557	2197	0	0	121211	25	70418	50188	10096	10000	40100	10000	10000	1077314	4576551	4633266	0	120715	0	121696	121771	113410	3	114131	60100	30200	20000	10000	60200	20000	10000	121481	121389	1	1	50201	100	99	100	40100	10000	10000	0	100	12418	14	370	2058	12017	404	117	2434	50	336	12392	111	0	100	0	0	0	3211	3	83	2	3	121366	50222	802	857	682	10000	10000	50100	120741	121556	121943	121527	121589
60204	121727	910	0	2	0	2	0	0	0	2500	0	2258	1	0	1192	1	228	121810	2225	0	0	121295	25	70292	50274	10112	10000	40100	10000	10000	1076216	4605787	4635734	0	121248	0	121655	121674	113675	3	113727	60100	30200	20000	10000	60200	20000	10000	121800	121805	1	1	50201	100	99	100	40100	10000	10000	0	100	12389	14	383	2063	12013	407	113	2416	46	327	12487	118	0	102	0	0	0	3211	3	17	3	3	121301	50206	300	830	698	10000	10000	50100	120807	120499	121410	121588	121447
60204	121894	911	0	1	0	0	0	0	0	2514	0	2294	1	0	1392	0	248	121467	2205	0	0	121111	25	70442	50318	10104	10000	40100	10000	10000	1075550	4603076	4630927	0	121449	0	121444	120648	113494	3	113675	60100	30200	20000	10000	60200	20000	10000	121402	121487	1	1	50201	100	99	100	40100	10000	10000	0	100	12421	2	378	2095	12063	352	113	2419	52	309	12432	79	0	89	0	0	1	3211	3	83	3	3	120318	50214	690	736	634	10000	10000	50100	121699	121632	121661	120669	121687
60204	121245	908	0	2	0	2	0	0	0	2414	0	2262	1	0	1368	0	272	120791	2189	0	1	123077	736	70891	50611	10201	10055	43954	11109	11063	1138154	4677548	4703525	0	124141	0	124790	124945	114995	299	115808	65643	33596	22260	11146	67046	22180	11145	124538	124415	29	1	50201	100	99	100	40100	10000	10000	0	100	12472	3	356	2134	12001	404	110	2414	64	325	12480	138	1	135	2	0	4	3732	8	197	5	5	123088	50623	1255	898	911	10000	10000	50100	124922	124030	124936	124698	124109
60204	124717	935	1	2	0	2	2	1	1	6685	3164	2139	1	0	1288	2	216	125103	2215	0	0	122684	744	70863	50723	10175	10046	43675	10991	10000	1074974	4604953	4628629	0	121609	0	121364	121565	114872	3	113808	60100	31687	20724	10245	63392	22094	10204	123589	122750	2	1	50201	100	99	100	40100	10000	10000	1	100	12458	4	401	2128	12008	399	110	2434	334	334	12415	109	1	98	1	0	0	3211	3	83	2	2	121677	50206	857	762	687	10000	10000	50100	121720	121920	121431	121705	121767
60204	121855	912	0	3	0	3	0	0	0	2509	0	2257	0	1	1256	2	188	121566	2265	0	0	121087	25	70466	50376	10117	10000	40100	10000	10000	1077107	4601949	4636024	0	121512	3	121456	121706	113853	23	113861	60100	30200	20000	10000	60200	20000	10000	121647	120795	1	1	50201	100	99	100	40100	10000	10000	0	100	12420	11	376	2140	12109	366	111	2423	50	331	12410	134	1	97	1	2	0	3211	3	83	3	3	121458	50236	630	800	729	10000	10000	50100	122013	121611	121334	121919	121647
60204	121786	912	0	3	0	0	3	0	0	2581	0	2333	0	1	1240	2	208	122009	2215	0	0	121420	25	70202	50322	10100	10002	40100	10000	10000	1087553	4596557	4637773	0	121699	0	121557	121632	112624	3	113927	60100	30200	20000	10000	60200	20000	10000	121551	121393	1	1	50201	100	99	100	40100	10000	10000	0	100	12407	11	371	2051	12009	392	112	2415	64	328	12396	118	1	118	1	10	0	3211	2	83	2	2	121280	50220	727	806	735	10000	10000	50100	121634	121771	121689	121686	121570
60204	121585	914	0	3	0	3	0	0	0	2470	0	2236	0	1	1248	2	480	121528	2230	0	0	120884	25	70442	50336	10098	10000	40100	10000	10000	1075280	4604678	4635933	0	121605	0	121668	121521	113550	3	114303	60100	30200	20000	10000	60200	20000	10000	121477	121447	1	1	50201	100	99	100	40100	10000	10000	0	100	12437	11	380	2056	12007	399	110	2435	50	220	12408	45	1	118	1	0	0	3211	3	83	2	2	121509	50232	736	588	678	10000	10000	50100	121818	121877	121475	121635	121045

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.1545

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60034	121235	910	2	2	0	0	0	2262	2228	1	1448	6	200	121437	2207	1	1	121209	25	70289	50216	10115	10000	40010	10000	10000	1074828	4603881	4633527	121617	0	121151	122065	113957	0	3	113961	60010	30020	20000	10000	60020	20000	10000	121343	121340	1	1	50021	10	9	10	40010	10000	10000	0	10	12424	0	386	2094	12013	407	107	2420	76	315	12392	130	0	97	0	0	0	0	3140	3	78	3	3	121393	50222	760	873	877	10000	10000	50010	121542	121694	121575	121380	121344
60024	121918	911	1	0	0	0	0	2350	2263	1	1400	6	384	121266	2194	0	0	121207	25	70322	50194	10105	10000	40010	10000	10000	1076736	4594746	4640435	121715	0	121709	121625	113249	0	3	114113	60010	30020	20000	10000	60020	20000	10000	121830	121659	1	1	50021	10	9	10	40010	10000	10000	0	10	12418	8	347	2102	12019	397	110	2403	222	319	12410	123	2	117	0	0	0	0	3140	3	78	3	2	120952	50266	951	669	729	10000	10000	50010	121654	121893	121428	121573	121641
60024	121912	909	1	0	0	0	0	2345	2250	1	1328	2	472	121712	2242	0	0	121221	25	70337	50220	10083	10000	40010	10000	10000	1077177	4605377	4639884	121455	0	121420	121839	113773	0	3	114191	60010	30020	20000	10000	60020	20000	10000	121788	121338	1	1	50021	10	9	10	40010	10000	10000	0	10	12428	8	383	2039	12012	400	110	2440	74	330	12416	84	0	106	0	2	0	0	3140	3	78	3	3	121456	50204	878	859	685	10000	10000	50010	121724	121871	121636	121605	121825
60024	121504	911	1	0	0	0	0	2353	2240	1	1208	2	176	121611	2248	1	0	121575	25	70379	50194	10102	10000	40010	10000	10000	1074702	4604637	4644272	121686	0	121661	121710	113427	0	3	113928	60010	30020	20000	10000	60020	20000	10000	121780	121491	1	1	50021	10	9	10	40010	10000	10000	0	10	12408	8	352	2066	12026	395	108	2420	318	341	12431	100	1	96	2	3	0	0	3140	3	78	3	3	121052	50238	837	758	600	10000	10000	50010	121366	121755	121861	121592	121727
60024	121844	908	0	0	0	0	0	2231	2251	1	1472	1	144	121439	2205	1	0	120715	25	70337	50172	10109	10000	40010	10000	10000	1075458	4603633	4633968	121134	0	121674	121375	113675	0	3	113830	60010	30020	20000	10000	60020	20000	10000	121418	121619	1	1	50021	10	9	10	40010	10000	10000	0	10	12425	0	388	2113	12027	403	109	2432	458	315	12420	97	1	115	0	0	0	0	3140	3	78	2	3	120430	50202	746	645	670	10000	10000	50010	121607	121343	121577	121718	121442
60024	121506	910	0	0	0	0	0	2394	2252	1	1416	2	132	121701	2236	1	0	121033	25	70151	50204	10099	10000	40152	10000	10000	1076862	4613983	4639852	121902	0	121436	121469	113349	0	3	114028	60010	30020	20000	10000	60020	20000	10000	121351	121429	1	1	50021	10	9	10	40010	10000	10000	1	10	12422	0	382	2066	12039	348	108	2419	52	325	12410	86	1	90	0	0	0	0	3140	3	78	3	2	121279	50188	885	809	694	10000	10000	50010	120635	121626	121421	121549	121175
60024	121240	909	0	0	0	0	0	2394	2270	1	1240	1	132	121388	2266	1	0	120904	25	70295	50220	10089	10000	40010	10000	10000	1071921	4609837	4623210	121473	0	121194	121594	113301	0	3	113717	60010	30020	20000	10000	60020	20000	10000	121677	121694	1	1	50021	10	9	10	40010	10000	10000	0	10	12412	0	357	2065	11999	406	111	2418	134	438	12416	115	1	128	0	2	0	0	3140	3	78	3	2	121483	50208	661	795	647	10000	10000	50010	121520	121411	121431	121630	121684
60025	121545	912	1	0	0	0	0	2085	2228	1	1024	3	224	121759	2240	0	0	120870	25	70331	50242	10114	10000	40010	10000	10000	1074909	4606285	4635352	121685	0	121551	121580	113450	0	3	114032	60010	30020	20000	10000	60020	20000	10000	121950	121516	1	1	50021	10	9	10	40010	10000	10000	0	10	12436	8	386	2069	12018	379	107	2407	424	333	12420	76	1	107	0	1	0	0	3140	3	78	2	3	121402	50202	981	749	691	10000	10000	50010	121713	121442	121719	121686	121431
60024	121398	912	1	0	0	0	0	2317	2237	1	1240	2	96	121511	2197	0	1	121633	25	70340	50166	10118	10000	40010	10000	10000	1078680	4615517	4630190	121859	0	121836	121640	113670	0	3	114061	60010	30020	20000	10000	60020	20000	10000	121339	121900	1	1	50021	10	9	10	40010	10000	10000	0	10	12435	0	377	2062	12007	402	113	2410	184	318	12433	109	1	115	0	0	0	0	3140	3	78	3	3	121524	50206	901	903	645	10000	10000	50010	121633	121485	121360	121330	121432
60024	121447	912	0	0	0	0	0	2322	2226	1	1400	1	244	121152	2229	1	2	120898	25	70289	50172	10119	10000	40010	10000	10000	1075881	4608120	4629351	121167	0	121205	120990	113853	0	3	114096	60010	30020	20000	10000	60020	20000	10000	121391	121843	1	1	50021	10	9	10	40010	10000	10000	0	10	12430	0	395	2064	12007	396	111	2423	256	319	12400	95	1	107	0	0	0	0	3140	3	24	3	3	121367	50200	734	748	553	10000	10000	50010	121795	121576	121596	121350	121813

Test 4: throughput

Count: 8

Code:

  ldp s0, s1, [x6, #0x10]!
  ldp s0, s1, [x7, #0x10]!
  ldp s0, s1, [x8, #0x10]!
  ldp s0, s1, [x9, #0x10]!
  ldp s0, s1, [x10, #0x10]!
  ldp s0, s1, [x11, #0x10]!
  ldp s0, s1, [x12, #0x10]!
  ldp s0, s1, [x13, #0x10]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3784

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	62	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160214	30036	227	3	3	0	0	0	0	10245	2205	1	1872	76	248	30228	2195	149	917	744	2140	25	160213	80221	80000	80100	80000	400949	1345259	0	0	118	30336	30375	30261	10263	3	10134	160100	200	160000	200	160000	30123	30143	1	1	80201	100	99	10	100	100	80000	80000	1	100	82408	16	2229	3101	0	82520	2308	112	2353	730	3384	85071	769	122	2982	3089	0	0	2	5110	1	16	1	1	30303	22	80116	326	340	110	80000	80000	80100	30411	30394	30372	30390	30189
160204	30138	227	3	0	0	0	1	1	10077	2202	1	1832	70	488	30487	2150	138	898	824	2135	25	160202	80396	80000	80100	80000	401013	1346240	0	0	117	30310	30181	30322	10147	3	10232	160100	200	160000	200	160000	30405	30211	1	1	80201	100	99	4	100	100	80000	80000	1	100	82408	9	2166	3573	0	82752	2312	107	2380	740	3469	85378	723	97	2998	3088	0	2	2	5110	1	16	1	1	30378	25	80122	375	349	82	80000	80000	80100	30236	30133	30099	30226	30229
160204	30299	228	1	0	0	0	1	0	9960	2273	1	1776	65	556	30268	2141	158	860	994	1767	25	160207	80212	80000	80100	80000	400969	1332867	1	0	122	30147	30162	30262	10051	3	10115	160100	200	160000	200	160000	30155	30295	1	1	80201	100	99	8	100	100	80000	80000	1	100	82392	9	2247	3016	0	82790	2371	106	2404	462	2872	85122	795	114	2373	2930	0	0	2	5110	1	17	1	1	30199	23	80107	340	329	94	80000	80000	80100	30166	30002	30370	30192	30265
160204	30070	226	1	0	1	0	1	0	9839	2240	1	1656	74	272	30192	2164	154	746	872	1739	25	160219	80205	80000	80100	80000	400894	1338298	1	0	111	30071	30414	30223	10119	3	10250	160100	200	160000	200	160000	30144	30234	1	1	80201	100	99	5	100	100	80000	80000	0	100	82401	18	2221	2019	0	82949	2311	109	2406	248	3233	85216	710	114	2483	3383	0	0	2	5110	1	16	1	1	30459	28	80109	325	219	81	80000	80000	80100	30251	30139	29994	30247	30301
160204	30274	226	1	2	1	0	1	0	10197	2141	1	1656	67	340	30151	2134	169	791	724	1479	25	160219	80194	80000	80100	80000	401008	1340782	1	0	105	30217	30260	30160	10168	3	10245	160100	200	160000	200	160000	30185	30049	1	1	80201	100	99	4	100	100	80000	80000	0	100	82384	24	2217	3118	0	82388	2364	111	2403	504	3729	84854	930	135	2425	2909	0	0	2	5110	1	17	1	1	30239	29	80108	340	283	95	80000	80000	80100	30125	30355	30317	30269	30252
160204	30283	226	3	0	0	0	1	0	10521	2246	1	1648	89	240	30234	2111	133	862	775	1976	25	160219	80208	80000	80100	80000	400980	1342886	1	0	107	30165	30355	30121	10150	3	10206	160100	200	160000	200	160000	30466	30171	1	1	80201	100	99	10	100	100	80000	80000	0	100	82376	24	2224	3190	0	82387	2322	107	2404	544	3935	85252	896	122	2639	3316	0	1	2	5110	1	16	1	1	30311	21	80109	251	372	110	80000	80000	80100	30163	30100	30059	30076	30384
160204	30331	226	3	0	0	0	1	0	10587	2203	1	1416	74	132	30234	2150	198	908	978	1919	25	160214	80207	80000	80100	80000	400920	1338039	1	0	101	30101	30448	30356	10080	3	10381	160100	200	160000	200	160000	30295	30302	1	1	80201	100	99	8	100	100	80000	80000	0	100	82412	24	2208	2872	0	82963	2330	113	2400	238	4168	85383	839	116	3175	3023	0	0	2	5110	1	16	1	1	30328	20	80136	313	350	78	80000	80000	80100	30226	30411	30450	30301	30206
160204	30403	227	3	0	0	0	1	0	9901	2206	1	1824	71	504	30287	2115	178	997	1079	1973	25	160208	80207	80000	80100	80000	401009	1342703	1	0	123	30292	30210	29896	10345	3	10170	160100	200	160000	200	160000	30390	30405	1	1	80201	100	99	11	100	100	80000	80000	0	100	82419	33	2224	3211	0	82497	2365	107	2406	318	3477	84947	721	86	3171	3408	0	0	1	5110	1	16	1	1	30356	16	80105	334	374	95	80000	80000	80100	30344	30288	30278	30264	30160
160204	30261	226	3	0	0	0	1	0	10615	2166	1	1584	70	256	30214	2155	133	1075	1109	2046	25	160230	80227	80000	80100	80000	400941	1346453	1	0	106	30359	30244	30298	10268	3	10348	160100	200	160000	200	160000	30264	30315	1	1	80201	100	99	4	100	100	80000	80000	1	100	82406	27	2248	3892	0	82514	2354	107	2404	246	4059	85408	921	133	3500	3142	15	0	2	5110	1	16	1	1	30461	22	80100	324	346	44	80000	80000	80100	30447	30421	30449	30244	30299
160204	30311	228	3	3	0	0	0	0	10538	2200	1	1848	84	516	30346	2186	94	925	894	2035	25	160216	80220	80000	80100	80000	401051	1333331	1	0	130	30192	30453	30144	10240	3	10320	160100	200	160000	200	160000	30440	30156	1	1	80201	100	99	3	100	100	80000	80000	0	100	82414	27	2274	3962	0	82618	2344	113	2412	230	3501	85330	865	117	2717	3573	16	0	1	5110	1	16	1	1	30118	26	80130	418	294	123	80000	80000	80100	30325	30503	30168	30350	30400

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3779

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160034	30159	227	3	0	3	3	0	0	9835	0	2216	1	1376	91	132	30343	2219	172	848	696	1862	25	160118	80122	80000	80010	80000	400599	1335540	0	0	112	30424	30277	30488	10254	3	10149	160010	20	160000	20	160000	30275	30147	1	1	80021	10	9	18	10	10	80000	80000	0	10	82428	20	2212	3042	82455	2321	110	2427	742	2920	85235	752	95	2439	3004	0	3	4	5020	3	16	2	1	1	7	4	30377	27	80133	429	327	91	80000	80000	80010	30317	30198	30404	30363	30358
160024	30304	226	3	0	0	0	1	0	10475	0	2181	1	1648	72	148	30257	2201	160	707	690	2054	25	160117	80269	80000	80010	80000	400564	1344179	0	0	90	30207	30301	30170	10248	3	10214	160010	20	160000	20	160000	30138	30369	1	1	80021	10	9	29	10	10	80000	80000	0	10	82415	12	2257	3067	82385	2335	113	2433	506	2945	84938	725	117	2564	3059	0	3	4	5020	4	16	0	0	0	5	6	30368	20	80118	384	363	100	80000	80000	80010	30315	30146	30242	30181	30152
160024	30319	227	2	1	0	2	0	0	9495	0	2236	1	1448	79	256	30165	2220	173	716	725	1942	25	160109	80121	80000	80010	80000	400505	1344211	0	0	105	30374	30311	30374	10292	3	10356	160010	20	160000	20	160000	30524	30313	1	1	80021	10	9	27	10	10	80000	80000	0	10	82419	24	2280	3198	82507	2338	113	2385	506	3138	84946	775	133	2145	3715	0	3	4	5020	7	16	0	0	0	7	6	30482	19	80100	386	380	104	80000	80000	80010	30280	30185	30276	30296	30304
160024	30220	227	3	0	0	0	0	0	10337	0	2202	1	1656	74	280	30215	2197	149	704	769	1941	71	160114	80117	80000	80010	80000	400493	1334819	0	0	108	30417	30238	30155	10095	3	10316	160010	20	160000	20	160000	30244	30376	1	1	80021	10	9	15	10	10	80000	80000	0	10	82438	20	2197	2787	82731	2277	108	2417	752	2939	85145	691	118	2154	2629	0	0	4	5020	7	16	0	0	0	6	7	30111	29	80100	321	303	91	80000	80000	80010	30272	30199	30272	30296	30141
160024	30154	226	1	0	0	0	0	0	9755	0	2237	1	1616	88	244	30100	2194	158	749	720	1908	25	160122	80117	80000	80010	80000	400510	1336828	0	0	119	30278	30105	30353	10175	3	10098	160010	20	160000	20	160000	30184	30379	1	1	80021	10	9	15	10	10	80000	80000	0	10	82403	16	2248	3357	82590	2340	114	2409	756	2618	84724	722	118	2308	2688	0	3	4	5020	7	16	0	0	0	7	6	30303	27	80120	381	333	74	80000	80000	80010	30210	30127	30239	30246	30194
160024	30258	225	1	0	0	0	0	0	9766	0	2220	1	1424	80	252	30350	2203	187	534	779	1907	25	160127	80109	80000	80010	80000	400449	1341040	0	0	137	30453	30391	30160	10317	3	10213	160010	20	160000	20	160000	30242	30109	1	1	80021	10	9	10	10	10	80000	80000	0	10	82440	16	2267	2483	82474	2285	111	2406	750	2843	85052	714	104	2413	2984	0	0	4	5020	6	16	0	0	0	6	6	30148	9	80116	301	397	87	80000	80000	80010	30217	30029	30087	30086	30221
160024	30150	225	1	0	0	1	0	0	9587	0	2185	1	1608	58	184	30245	2197	131	392	486	1681	25	160128	80118	80000	80010	80000	400528	1339759	1	1	123	30171	30147	30251	10241	3	10194	160010	20	160000	20	160000	30279	30468	1	1	80021	10	9	16	10	10	80000	80000	0	10	82444	8	2254	3111	82391	2340	112	2418	788	2885	84646	810	123	2419	2538	0	3	4	5020	7	16	0	0	0	4	5	30269	19	80118	390	383	114	80000	80000	80010	30502	30401	30253	30301	30290
160024	30225	226	3	0	0	3	0	0	9988	0	2199	1	1624	99	260	30295	2168	170	591	801	2004	25	160114	80137	80000	80010	80000	400558	1329080	0	0	109	30344	30194	30282	10123	3	10204	160010	20	160000	20	160000	30215	30230	1	1	80021	10	9	21	10	10	80000	80000	0	10	82420	18	2225	3617	82693	2330	110	2424	506	2936	85235	737	125	2366	3150	0	3	4	5020	9	16	0	0	0	6	5	30132	28	80122	372	308	104	80000	80000	80010	30358	30241	30081	30093	30263
160024	30185	226	2	0	0	0	0	0	10196	0	2224	1	1640	78	260	30399	2164	174	788	747	2092	25	160126	80132	80000	80010	80000	400516	1348259	0	0	125	30307	30278	30169	10267	3	10351	160010	20	160000	20	160000	30370	30318	1	1	80021	10	9	19	10	10	80000	80000	0	10	82419	22	2214	2974	82724	2359	109	2417	508	3220	85073	701	121	2713	2937	15	3	4	5020	7	15	0	0	0	7	7	30198	14	80089	392	333	96	80000	80000	80010	30269	30289	30304	30307	30198
160024	30205	225	2	0	2	0	0	1	10024	0	2214	1	1656	74	260	30295	2181	202	684	740	2040	25	160118	80109	80000	80010	80000	400493	1346316	0	0	106	30181	30148	30358	10296	3	10300	160010	20	160000	20	160000	30241	30244	1	1	80021	10	9	9	10	10	80000	80000	0	10	82417	17	2250	3169	82468	2294	111	2409	506	3078	84797	852	116	2518	2784	0	4	4	5020	7	16	0	0	0	3	7	30215	25	80112	379	425	86	80000	80000	80010	30341	30311	30179	30289	30169

LDP (pre-index, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations