Firestorm: LDP (signed offset, D) measurements

Code:

  ldp d0, d1, [x6, #0x10]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
2005	403	3	1	0	1	1	1	1	70	1	0	3	388	3	7	7	21	25	1000	1000	1000	15535	0	378	404	403	102	3	136	1000	2000	1000	403	403	1	1	1001	0	1000	1000	0	1020	20	43	1061	0	0	0	61	1039	6	1	58	43	19	0	73	2	16	1	1	402	13	13	5	1000	1000	403	403	403	404	404
2004	403	3	1	1	1	1	0	0	66	1	0	3	388	3	6	7	19	25	1000	1000	1000	15486	0	377	402	403	101	3	135	1000	2000	1000	405	403	1	1	1001	0	1000	1000	0	1019	20	43	1060	1	0	1	60	1039	6	1	59	43	19	2	73	1	16	1	1	399	13	13	5	1000	1000	404	404	406	404	403
2004	402	2	1	0	0	1	0	0	66	1	0	3	387	3	7	7	19	25	1000	1000	1000	15521	1	378	403	403	100	3	135	1000	2000	1000	404	403	1	1	1001	0	1000	1000	0	1019	20	43	1059	0	0	1	60	1039	6	1	59	43	19	2	73	1	16	1	1	399	13	13	5	1000	1000	404	403	404	403	404
2004	402	3	1	1	1	0	1	0	85	0	0	3	388	3	7	7	19	25	1000	1000	1000	15486	0	377	407	404	105	3	136	1000	2000	1000	403	402	1	1	1001	0	1000	1000	0	1019	19	43	1059	1	1	1	61	1040	6	1	58	43	19	1	73	1	16	1	1	399	13	13	5	1000	1000	403	404	403	404	404
2004	403	3	1	1	1	0	0	0	69	0	0	2	388	2	7	7	20	25	1000	1000	1000	15559	0	378	403	403	100	3	136	1000	2000	1000	403	403	1	1	1001	0	1000	1000	0	1020	21	43	1059	1	0	1	61	1040	6	1	58	43	19	1	73	1	16	1	1	399	13	13	5	1000	1000	406	403	403	404	404
2004	403	3	1	0	1	0	0	0	66	0	0	2	387	2	7	7	19	25	1000	1000	1000	15554	0	377	402	403	101	3	136	1000	2000	1000	402	402	1	1	1001	1	1000	1000	1	1019	21	45	1058	0	0	1	61	1040	6	1	59	43	19	0	73	1	16	1	1	400	13	13	5	1000	1000	403	403	404	404	403
2004	402	3	1	0	1	1	0	0	67	1	0	3	388	3	9	7	20	25	1000	1000	1000	15560	0	378	403	402	100	3	135	1000	2000	1000	402	403	1	1	1001	0	1000	1000	0	1019	21	43	1059	1	0	0	60	1039	6	1	59	43	19	0	73	1	16	1	1	399	13	10	5	1000	1000	403	404	404	403	403
2004	403	3	1	0	1	0	0	0	66	1	0	3	387	3	9	7	19	25	1000	1000	1000	15554	0	377	402	403	101	3	136	1000	2000	1000	402	402	1	1	1001	0	1000	1000	0	1020	19	43	1058	0	0	0	61	1040	6	1	58	43	19	2	73	1	16	1	1	399	13	13	5	1000	1000	404	403	404	403	405
2004	402	3	1	1	1	0	0	0	67	1	0	2	388	2	7	7	19	25	1000	1000	1000	15554	1	377	402	403	101	3	136	1000	2000	1000	402	403	1	1	1001	0	1000	1000	0	1020	19	43	1059	1	0	1	60	1040	6	1	58	43	19	1	73	1	16	1	1	400	13	13	5	1000	1000	404	403	404	404	404
2004	403	3	1	1	0	0	0	0	67	0	0	2	387	3	7	7	19	25	1000	1000	1000	15535	1	378	403	402	100	3	135	1000	2000	1000	403	403	1	1	1001	0	1000	1000	0	1020	20	43	1062	0	0	1	60	1039	6	1	58	44	19	2	73	1	16	1	1	400	13	13	5	1000	1000	404	403	404	404	404

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp d0, d1, [x6, #0x10]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120053	899	0	0	0	0	0	1	1	0	0	2	0	1	0	0	120026	119494	109458	25	60103	40102	10001	10000	30100	10000	10000	1079368	5736182	6118297	0	120026	0	120050	120047	111881	0	3	112490	50100	30200	20000	10000	60200	10000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	1	0	0	10000	1	0	0	0	0	3210	2	121	3	3	119668	40004	0	6	0	10000	10000	40100	120057	120042	120054	120054	120057
60204	120056	899	0	1	0	0	1	1	1	0	0	2	0	1	0	0	120020	119494	109443	25	60103	40102	10000	10000	30100	10000	10055	1079681	5736659	6118656	1	120026	0	120035	120050	111895	0	3	112374	50100	30200	20000	10000	60200	10000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	6	10000	1	0	1	0	0	3210	2	135	3	3	119657	40002	6	9	0	10000	10000	40100	120051	120036	120036	120051	120036
60204	120050	899	0	0	0	0	0	0	0	0	0	1	0	1	0	0	120035	119503	109443	25	60100	40100	10000	10000	30100	10000	10000	1079648	5736272	6118399	1	120026	3	120035	120051	111881	0	3	112421	50100	30200	20000	10000	60200	10000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	10000	1	0	1	0	0	3210	3	135	3	3	119655	40002	0	6	5	10000	10000	40100	120051	120051	120036	120048	120051
60204	120050	899	0	0	0	0	0	0	0	0	0	10	0	1	0	0	120020	119494	109458	25	60103	40100	10000	10000	30100	10000	10000	1079387	5736323	6117882	1	120026	0	120035	120050	111895	0	3	112416	50100	30200	20000	10000	60200	10000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	0	1	10000	0	0	0	10000	0	1	1	1	2	3210	3	100	3	3	119670	40004	0	9	0	10000	10000	40100	120057	120057	120051	120036	120051
60204	120050	899	0	0	0	0	0	0	0	0	0	0	0	1	0	0	120020	119494	109443	25	60103	40102	10000	10000	30100	10000	10000	1079351	5736566	6117518	1	120032	0	120041	120056	111897	0	3	112409	50100	30200	20000	10000	60200	10000	10000	120041	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	1	0	10001	0	1	1	10000	1	1	1	1	2	3210	3	100	3	2	119668	40002	0	9	0	10000	10000	40100	120065	120051	120051	120036	120054
60204	120050	899	0	0	1	1	1	0	0	0	0	1	0	0	0	0	120043	119530	109449	25	60103	40104	10001	10000	30100	10000	10000	1079827	5739254	6118554	1	120032	0	120041	120053	111900	0	3	112409	50100	30200	20000	10000	60200	10000	10000	120053	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10002	0	0	4	10000	0	0	1	0	0	3210	3	108	3	3	119646	40002	6	9	8	10000	10000	40100	120051	120051	120036	120051	120051
60204	120035	899	0	0	0	0	0	0	0	0	0	1	0	0	0	0	120035	119494	109455	25	60100	40102	10001	10000	30100	10000	10000	1081941	5736227	6117882	0	120021	0	120035	120050	111903	0	3	112416	50100	30200	20000	10000	60200	10000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3210	3	100	3	3	119662	40004	9	9	0	10000	10000	40100	120057	120057	120042	120057	120042
60204	120050	899	0	0	0	0	0	1	0	0	0	1	0	0	0	0	120020	119503	109458	25	60103	40108	10000	10001	30100	10000	10000	1079177	5736131	6117882	1	120026	0	120050	120050	111903	0	3	112416	50100	30200	20000	10000	60200	10000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	0	1	0	1	1	3210	3	108	3	2	119646	40002	0	9	5	10000	10000	40100	120051	120051	120049	120036	120048
60204	120047	899	0	0	0	0	0	0	0	0	0	0	0	0	0	0	120036	119494	109455	25	60103	40102	10001	10000	30100	10000	10000	1079999	5736464	6118557	0	120026	0	120050	120050	111903	0	3	112374	50100	30200	20000	10000	60200	10000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	10000	0	1	1	1	0	3210	3	121	2	3	119651	40004	9	9	0	10000	10000	40100	120062	120057	120057	120042	120042
60204	120041	899	0	1	0	0	1	0	0	0	0	7	0	0	0	0	120038	119530	109461	25	60106	40104	10002	10000	30100	10000	10000	1079995	5737334	6119224	1	120029	0	120056	120041	111902	0	3	112409	50100	30200	20000	10000	60200	10000	10000	120056	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	0	10003	0	0	4	10000	0	1	1	1	1	3210	3	121	3	3	119668	40004	9	6	0	10000	10000	40100	120042	120057	120042	120057	120057

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	60	69	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120052	900	1	0	1	1	0	0	0	2	0	1	0	0	120041	119489	109463	25	60016	40014	10001	10000	30010	10000	10000	1079870	5736326	6125852	0	0	120047	120057	120041	111909	0	3	112453	50010	30020	20000	10000	60020	10000	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10001	0	0	0	1	10000	1	1	1	1	1	0	3140	1	99	1	1	119665	40000	0	6	8	10000	10000	40010	120048	120048	120036	120036	120036
60024	120035	899	0	0	0	0	0	1	0	2	0	1	0	1	120041	119489	109463	25	60016	40014	10002	10000	30010	10000	10000	1079878	5735593	6125852	0	0	120056	120047	120047	111903	0	3	112444	50010	30020	20000	10000	60020	10000	10000	120035	120047	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	0	10000	1	1	1	1	2	0	3140	1	99	1	1	119671	40004	0	6	0	10000	10000	40010	120054	120054	120054	120054	120054
60024	120053	899	1	1	1	0	0	0	0	2	0	1	0	0	120038	119486	109461	25	60016	40014	10002	10000	30158	10000	10000	1079878	5735593	6126679	0	0	120029	120053	120053	111909	0	3	112438	50010	30020	20000	10000	60020	10000	10000	120056	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10002	0	1	0	1	10000	1	1	1	0	0	0	3140	1	99	1	1	119650	40002	9	0	8	10000	10000	40010	120056	120051	120051	120051	120051
60024	120047	899	0	0	0	0	0	0	0	2	0	0	0	0	120038	119486	109461	25	60016	40012	10001	10000	30010	10000	10000	1079870	5736182	6125852	0	0	120027	120035	120047	111903	0	3	112444	50010	30020	20000	10000	60020	10000	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10001	0	0	1	4	10000	1	1	0	1	1	0	3140	1	99	1	1	119671	40004	6	6	5	10000	10000	40010	120137	120606	120054	120042	120042
60024	120057	899	1	0	1	1	0	0	3	10	108	1	0	0	120041	119489	109449	25	60013	40012	10002	10000	30010	10000	10000	1079906	5735593	6123500	0	0	120034	120041	120053	111924	0	3	112453	50010	30020	20000	10000	60020	10000	10000	120059	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	0	10001	0	0	0	4	10000	1	1	1	1	1	0	3140	2	99	3	1	119973	40004	0	6	5	10000	10000	40010	120248	120057	120046	120057	120042
60024	120056	899	1	1	0	1	0	0	0	1	0	1	0	1	120038	119490	109463	25	60016	40014	10002	10000	30010	10000	10000	1079915	5736182	6125852	0	0	120061	120053	120041	111922	0	3	112450	50010	30020	20000	10000	60020	10000	10000	120054	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10001	0	0	2	1	10000	1	1	1	1	1	0	3140	1	99	1	1	119659	40004	9	6	0	10000	10000	40010	120057	120042	120057	120042	120042
60024	120041	899	1	1	1	0	0	0	0	2	0	1	0	1	120041	119484	109449	25	60016	40014	10001	10000	30010	10000	10000	1079878	5735593	6125852	0	0	120049	120041	120056	111924	0	3	112438	50010	30020	20000	10000	60020	10000	10000	120056	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10001	0	14	1	1	10000	1	1	0	1	0	0	3140	1	99	1	1	119674	40002	9	6	5	10000	10000	40010	120042	120057	120057	120057	120042
60024	120056	900	1	1	0	1	0	0	0	2	0	0	0	0	120026	119489	109449	25	60016	40014	10002	10000	30010	10000	10000	1079870	5736326	6125852	0	0	120039	120056	120056	111924	0	3	112453	50010	30020	20000	10000	60020	10000	10000	120053	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	3	1	10001	0	0	2	1	10000	1	1	1	1	1	0	3140	1	99	1	1	119671	40004	9	6	8	10000	10000	40010	120057	120057	120057	120057	120057
60024	120056	899	1	0	1	1	0	0	0	2	0	0	0	0	120041	119489	109463	25	60016	40014	10002	10000	30010	10000	10000	1079906	5736326	6125985	0	0	120070	120056	120053	111909	0	3	112453	50010	30020	20000	10000	60020	10000	10000	120041	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10001	0	0	0	1	10000	1	1	1	1	1	0	3140	1	99	1	1	119671	40004	9	6	8	10000	10000	40010	120057	120057	120057	120057	120057
60024	120056	899	1	1	1	1	1	0	0	1	0	1	0	0	120041	119489	109463	25	60016	40014	10002	10000	30010	10000	10000	1079870	5736182	6123500	0	0	120106	120061	120060	111930	0	3	112453	50010	30020	20000	10000	60020	10000	10000	120056	120053	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10002	0	0	0	1	10000	1	1	1	1	2	0	3140	1	99	1	1	119671	40004	6	6	8	10000	10000	40010	120057	120054	120042	120042	120057

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp d0, d1, [x6, #0x10]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120053	900	1	0	0	0	1	0	0	0	1	0	0	0	1	120041	119530	109461	25	60106	40104	10001	10000	30100	10000	10000	1079414	5736914	6118297	1	120029	120041	120056	111897	0	3	112409	50100	30200	20000	10000	60200	10000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10001	0	0	1	10000	1	1	1	1	1	1	3210	1	110	3	1	119664	40004	0	6	8	10000	10000	40100	120057	120042	120054	120042	120042
60204	120056	899	1	0	1	0	0	0	0	0	2	0	1	0	1	120038	119530	109461	25	60106	40104	10002	10000	30100	10000	10000	1079414	5736326	6119122	0	120017	120056	120041	111897	0	3	112409	50100	30200	20000	10000	60200	10000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	1	1	10002	0	1	1	10000	1	1	1	1	0	0	3210	1	121	3	1	119673	40004	0	9	8	10000	10000	40100	120057	120057	120042	120042	120057
60204	120053	899	1	1	1	1	0	0	0	0	7	0	0	0	1	120041	119530	109451	25	60106	40104	10002	10000	30100	10000	10000	1079414	5735593	6118297	0	120029	120056	120056	111897	0	3	112409	50100	30200	20000	10000	60200	10000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	3	1	10002	0	2	1	10000	1	1	1	1	2	0	3210	1	110	3	2	119665	40004	0	6	8	10000	10000	40100	120057	120057	120054	120054	120057
60204	120056	899	1	1	1	0	0	0	0	0	2	0	0	0	1	120041	119530	109461	25	60103	40104	10002	10000	30100	10000	10000	1079464	5736326	6117518	0	120017	120056	120041	111897	0	3	112409	50100	30200	20000	10000	60200	10000	10000	120053	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10001	0	1	1	10000	1	1	1	1	0	0	3210	1	110	2	1	119961	40004	9	9	5	10000	10000	40100	120059	120057	120057	120057	120042
60204	120054	899	1	1	1	1	0	0	0	0	7	0	0	0	1	120041	119511	109463	25	60106	40104	10001	10000	30100	10000	10000	1079414	5736182	6118297	0	120032	120056	120056	111902	0	3	112417	50100	30200	20000	10000	60200	10000	10000	120053	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10003	0	1	1	10000	0	1	1	1	1	0	3210	1	121	2	1	119668	40004	6	9	0	10000	10000	40100	120042	120042	120054	120042	120054
60204	120041	899	1	1	1	0	0	0	0	0	1	0	1	0	0	120038	119530	109463	25	60103	40104	10002	10000	30100	10000	10000	1079414	5736326	6118297	0	120032	120056	120056	111902	0	3	112415	50100	30200	20000	10000	60200	10000	10000	120056	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10003	0	2	1	10000	1	1	0	1	0	0	3210	1	121	3	1	119668	40004	0	0	8	10000	10000	40100	120057	120057	120042	120057	120042
60204	120041	899	1	0	1	0	0	0	0	0	5	0	0	0	1	120041	119530	109463	25	60106	40104	10002	10000	30100	10000	10000	1079414	5737910	6118912	0	120032	120056	120056	111899	0	3	112409	50100	30200	20000	10000	60200	10000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	0	10003	0	1	1	10000	0	1	1	1	0	0	3210	1	100	3	1	119669	40004	0	9	5	10000	10000	40100	120054	120057	120057	120042	120054
60204	120056	899	1	0	0	0	0	0	0	0	1	0	0	0	0	120041	119497	109563	25	60106	40104	10001	10000	30100	10000	10000	1079414	5736326	6118297	0	120032	120056	120067	111902	0	3	112417	50100	30200	20000	10000	60200	10000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	2	0	10003	0	1	1	10000	1	1	1	1	0	0	3210	0	100	2	1	119662	40004	0	6	0	10000	10000	40100	120057	120057	120057	120054	120054
60204	120053	899	1	1	1	0	0	0	0	0	2	0	0	0	1	120038	119511	109463	25	60106	40104	10001	10000	30100	10000	10000	1079414	5736182	6118297	0	120032	120056	120056	111902	0	3	112409	50100	30200	20000	10000	60200	10000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10001	1	0	1	10000	0	1	1	1	0	0	3210	1	121	3	1	119662	40002	0	6	0	10000	10000	40100	120042	120054	120042	120054	120054
60204	120053	899	1	0	1	0	1	0	0	0	7	0	0	0	0	120041	119511	109449	25	60106	40102	10002	10000	30100	10000	10000	1079414	5735593	6118297	0	120032	120041	120053	111902	0	3	112409	50100	30200	20000	10000	60200	10000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10001	0	1	1	10000	1	1	0	1	2	0	3210	1	100	3	1	119664	40004	9	0	0	10000	10000	40100	120057	120057	120057	120042	120042

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	1e	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120041	899	1	1	0	0	2	0	0	0	0	120045	119484	109467	25	60013	40014	10001	10000	30010	10000	10000	1079942	5736374	6126051	1	120040	0	120152	120060	111928	3	112438	50010	30020	20000	10000	60020	10000	10000	120060	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10001	9	0	4	10000	1	1	0	1	0	0	0	3140	1	99	1	1	119678	40004	0	10	12	10000	10000	40010	120061	120061	120042	120061	120061
60024	120060	899	1	1	1	0	2	0	0	0	1	120042	119484	109467	25	60016	40014	10001	10000	30010	10000	10000	1079870	5736518	6126051	0	120036	0	120060	120041	111909	3	112454	50010	30020	20000	10000	60020	10000	10000	120041	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10002	0	2	178	10000	0	1	1	1	2	0	0	3140	1	99	1	1	119659	40004	13	0	12	10000	10000	40010	120061	120061	120042	120058	120061
60024	120041	899	1	1	1	0	1	1	0	0	1	120045	119490	109467	25	60016	40014	10001	10000	30010	10000	10000	1079942	5736374	6126051	1	120036	0	120060	120060	111928	3	112438	50010	30020	20000	10000	60020	10000	10000	120060	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	2	1	10001	0	1	1	10000	0	1	1	1	2	0	0	3140	1	99	1	1	119678	40002	13	0	12	10000	10000	40010	120058	120061	120061	120061	120058
60024	120057	900	1	0	1	0	2	0	0	0	1	120026	119490	109465	25	60016	40014	10002	10000	30010	10000	10000	1079942	5736518	6123500	0	120027	0	120054	120035	111922	3	112451	50010	30020	20000	10000	60020	10000	10000	120054	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	0	10002	1	2	1	10000	1	1	1	1	0	0	0	3140	1	99	1	1	119678	40004	13	13	0	10000	10000	40010	120061	120061	120061	120061	120058
60024	120060	900	1	1	1	0	2	0	0	0	0	120045	119493	109464	25	60016	40014	10001	10000	30010	10000	10000	1079915	5735593	6126051	0	120036	0	120060	120060	111928	3	112457	50010	30020	20000	10000	60020	10000	10000	120060	120057	1	1	50021	10	9	10	40010	10000	10000	1	10	10001	1	1	10001	0	2	4	10000	1	1	1	1	1	0	0	3140	1	99	1	1	119659	40004	13	10	0	10000	10000	40010	120058	120058	120061	120042	120064
60024	120060	903	1	1	1	0	2	0	0	0	0	120045	119493	109467	25	60016	40014	10002	10000	30010	10000	10000	1079870	5736518	6126051	0	120017	0	120060	120060	111928	3	112457	50010	30020	20000	10000	60020	10000	10000	120060	120057	1	1	50021	10	9	10	40010	10000	10000	1	10	10002	1	1	10002	0	1	1	10001	1	1	1	1	1	0	0	3140	1	99	1	1	119659	40002	13	13	12	10000	10000	40010	120061	120061	120061	120061	120061
60024	120060	900	1	0	0	0	1	0	0	0	0	120042	119493	109449	25	60016	40014	10002	10000	30010	10000	10000	1079942	5736374	6126051	1	120036	0	120057	120057	111928	3	112454	50010	30020	20000	10000	60020	10000	10000	120060	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	0	10001	0	1	7	10000	0	1	1	1	1	0	0	3140	1	99	1	1	119675	40004	13	0	0	10000	10000	40010	120042	120043	120042	120061	120042
60024	120060	899	1	1	1	0	2	0	0	0	1	120045	119493	109467	25	60016	40014	10002	10000	30010	10000	10000	1079870	5736374	6126051	0	120036	0	120060	120057	111909	3	112454	50010	30020	20000	10000	60020	10000	10000	120057	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10003	0	1	1	10000	1	1	1	1	1	0	0	3140	1	99	1	1	119678	40004	13	0	0	10000	10000	40010	120042	120061	120058	120061	120058
60024	120057	899	1	0	1	0	2	0	0	0	0	120026	119493	109467	25	60016	40014	10001	10000	30010	10000	10000	1079942	5736518	6126051	0	120017	0	120060	120041	111928	3	112454	50010	30020	20000	10000	60020	10000	10000	120060	120041	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	2	1	10001	0	1	1	10000	0	1	1	1	2	0	0	3140	1	99	1	1	119678	40004	13	13	9	10000	10000	40010	120061	120058	120063	120058	120058
60024	120057	899	1	0	1	0	2	1	0	0	1	120042	119493	109464	25	60016	40014	10002	10000	30010	10000	10000	1079942	5736374	6123500	0	120036	0	120041	120057	111909	3	112457	50010	30020	20000	10000	60020	10000	10000	120041	120058	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10002	0	0	1	10000	1	1	0	1	1	0	0	3140	1	99	1	1	119659	40004	13	10	12	10000	10000	40010	120058	120061	120042	120042	120112

Test 4: throughput

Count: 8

Code:

  ldp d0, d1, [x6, #0x10]
  ldp d0, d1, [x6, #0x10]
  ldp d0, d1, [x6, #0x10]
  ldp d0, d1, [x6, #0x10]
  ldp d0, d1, [x6, #0x10]
  ldp d0, d1, [x6, #0x10]
  ldp d0, d1, [x6, #0x10]
  ldp d0, d1, [x6, #0x10]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160205	26725	200	0	0	0	1	1	0	0	74	0	0	2	26712	2	12	12	16	25	80100	100	80000	100	80000	500	1169387	26702	0	26707	26707	6650	0	3	6666	80100	200	160000	200	80000	26722	26722	1	1	80201	100	99	100	100	80000	80000	100	80000	0	39	0	80039	0	0	42	80000	6	0	0	43	0	5110	2	16	2	2	26704	0	10	6	4	80000	80000	100	26728	26728	26728	26728	26723
160204	26732	201	0	0	0	0	0	0	0	45	0	0	0	26707	0	0	18	12	25	80100	100	80000	100	80000	500	1169305	26702	0	26727	26722	6650	0	3	6685	80100	200	160000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	100	80000	0	39	0	80000	0	0	42	80000	6	1	35	0	0	5110	2	16	2	2	26724	0	10	0	0	80000	80000	100	26728	26708	26708	26723	26723
160204	26723	200	0	0	0	1	1	0	0	0	0	0	0	26712	2	12	12	16	25	80100	100	80000	100	80000	500	1176185	26682	0	26722	26707	6650	0	3	6665	80100	200	160000	200	80000	26727	26707	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	80000	0	0	3	80035	6	1	0	39	0	5110	2	16	2	2	26724	0	10	0	2	80000	80000	100	26728	26708	26728	26708	26723
160204	26730	200	0	0	0	0	0	0	0	0	0	0	2	26712	2	12	12	16	25	80100	100	80000	100	80000	500	1175837	26682	0	26707	26727	6645	0	3	6685	80100	200	160000	200	80000	26707	26722	1	1	80201	100	99	100	100	80000	80000	100	80000	0	39	0	80035	0	0	42	80035	6	0	35	39	0	5110	2	16	2	2	26704	0	10	6	4	80000	80000	100	26728	26728	26723	26728	26723
160204	26727	200	0	0	0	0	0	0	0	45	0	1	2	26712	2	12	0	16	25	80100	100	80000	100	80000	500	1174724	26702	0	26707	26727	6650	0	3	6685	80100	200	160000	200	80000	26707	26722	1	1	80201	100	99	100	100	80000	80000	100	80000	0	39	0	80039	0	0	39	80039	6	0	35	43	0	5110	2	16	3	2	26724	0	0	10	4	80000	80000	100	26728	26728	26728	26728	26728
160204	26730	200	0	0	0	0	0	0	0	41	0	1	2	26692	2	0	0	128	25	80100	100	80000	100	80000	500	1173231	26682	0	26727	26707	6650	0	3	6685	80100	200	160000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	80035	0	0	0	80039	0	0	39	43	0	5110	2	16	2	2	26719	0	6	0	0	80000	80000	100	26728	26723	26723	26728	26708
160204	26714	200	0	0	0	0	0	0	0	45	0	0	2	26712	2	18	18	16	25	80100	100	80000	100	80000	500	1170107	26697	0	26727	26707	6645	0	3	6665	80100	200	160000	200	80000	26707	26707	1	1	80201	100	99	100	100	80000	80000	100	80000	0	39	0	80035	0	0	39	80039	6	1	35	43	0	5110	2	16	2	2	26719	0	0	0	0	80000	80000	100	26728	26728	26708	26708	26723
160204	26730	200	0	0	0	0	0	0	0	48	0	1	0	27126	0	12	0	16	25	80100	100	80000	100	80000	500	1173183	26682	0	26707	26727	6630	0	3	6685	80100	200	160000	200	80000	26707	26707	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	80039	0	0	3	80035	6	1	0	43	0	5110	2	16	2	2	26724	0	0	6	4	80000	80000	100	26728	26708	26728	26728	26723
160204	26739	201	0	0	0	0	0	0	0	45	0	1	2	26712	2	0	12	16	25	80100	100	80000	100	80000	500	1170107	26697	0	26707	26727	6645	0	3	6685	80100	200	160000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	80000	0	0	42	80039	6	0	35	43	0	5110	2	16	2	2	26724	0	0	10	0	80000	80000	100	26723	26728	26708	26723	26723
160204	26711	201	0	0	0	1	0	0	0	41	0	0	1	26712	2	0	18	0	25	80100	100	80000	100	80000	500	1170203	26702	0	26707	26722	6650	0	3	6685	80100	200	160000	200	80000	26727	26722	1	1	80201	100	99	100	100	80000	80000	100	80000	0	0	0	80039	0	0	38	80035	6	1	35	43	0	5110	2	16	2	2	26704	0	10	6	0	80000	80000	100	26723	26708	26723	26723	26723

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160025	26728	200	0	0	0	45	0	0	1	26712	2	12	0	16	25	80010	10	80000	10	80000	50	1176117	0	26702	26727	26727	6672	3	6707	80010	20	160000	20	80000	26727	26727	1	1	80021	10	9	10	10	80000	80000	10	80000	43	0	80039	0	39	80039	6	1	39	43	0	5020	0	3	16	3	3	26728	14	10	4	80000	80000	10	26728	26732	26728	26733	26728
160024	26727	200	0	0	0	45	0	0	1	26712	3	12	1	16	25	80010	10	80000	10	80000	50	1176923	0	26702	26727	26727	6673	3	6707	80010	20	160000	20	80000	26727	26727	1	1	80021	10	9	10	10	80000	80000	10	80000	43	32	80171	11	186	80039	6	1	39	43	0	5020	0	4	16	3	5	26725	10	10	4	80000	80000	10	26728	26728	26728	26728	26728
160024	26707	200	0	0	0	45	1	0	1	26712	2	0	12	16	25	80010	10	80000	10	80000	50	1169463	1	26702	26727	26727	6672	3	6707	80010	20	160000	20	80000	26727	26727	1	1	80021	10	9	10	10	80000	80000	10	80000	43	0	80039	0	39	80039	6	1	39	43	0	5020	0	5	16	3	3	26724	10	10	4	80000	80000	10	26728	26728	26728	26728	26728
160024	26733	200	0	0	0	45	0	0	1	26712	2	12	12	16	25	80010	10	80000	10	80000	50	1168157	1	26706	26727	26727	6676	3	6707	80010	20	160000	20	80000	26727	26727	1	1	80021	10	9	10	10	80000	80000	10	80000	43	0	80039	0	38	80039	6	1	39	43	0	5020	0	5	16	3	4	26724	10	10	7	80000	80000	10	26728	26728	26732	26728	26864
160024	26731	200	0	1	0	45	0	0	1	26712	2	12	12	0	25	80010	10	80000	10	80000	50	1168824	0	26702	26727	26727	6672	3	6707	80010	20	160000	20	80000	26731	26727	1	1	80021	10	9	10	10	80000	80000	10	80000	43	0	80039	0	39	80039	6	1	39	43	0	5020	0	5	16	5	5	26724	10	10	7	80000	80000	10	26732	26728	26728	26728	26728
160024	26729	200	0	0	0	0	0	0	1	26712	2	12	12	0	25	80010	10	80000	10	80000	50	1168805	0	26682	26727	26727	6673	3	6707	80010	20	160000	20	80000	26727	26727	1	1	80021	10	9	10	10	80000	80000	10	80000	0	0	80039	8	141	80039	6	1	39	43	0	5020	0	4	16	4	4	26724	10	10	4	80000	80000	10	26732	26898	26735	26728	26728
160024	26727	200	0	0	0	45	0	0	1	26712	2	12	1	16	25	80010	10	80000	10	80000	50	1170266	1	26706	26727	26727	6672	3	6707	80010	20	160000	20	80000	26731	26727	1	1	80021	10	9	10	10	80000	80000	10	80000	43	0	80040	0	39	80039	6	1	39	43	0	5020	0	4	16	4	4	26724	10	10	4	80000	80000	10	26728	26728	26728	26728	26728
160024	26729	200	0	1	0	45	0	0	1	26712	2	1	12	16	25	80010	10	80000	10	80000	50	1172684	1	26702	26727	26727	6676	3	6707	80010	20	160000	20	80000	26727	26727	1	1	80021	10	9	10	10	80000	80000	10	80000	43	0	80038	1	39	80039	6	1	39	44	0	5020	0	4	16	3	4	26724	14	10	4	80000	80000	10	26728	26728	26728	26728	26728
160024	26727	200	0	0	0	44	0	0	1	26712	2	12	12	19	25	80010	10	80000	10	80000	50	1173086	1	26708	26740	26707	6672	3	6707	80010	20	160000	20	80000	26727	26729	1	1	80021	10	9	10	10	80000	80000	10	80000	44	0	80040	0	39	80039	6	1	39	43	0	5020	0	5	16	5	5	26704	10	14	4	80000	80000	10	26728	26708	26728	26728	26728
160024	26729	200	0	1	0	44	0	0	1	26712	2	12	12	16	25	80010	10	80000	10	80000	50	1168185	0	26702	26727	26731	6672	3	6707	80010	20	160000	20	80000	26731	26707	1	1	80021	10	9	10	10	80000	80000	10	80000	43	0	80039	0	42	80039	6	1	39	43	0	5020	0	4	17	3	3	26724	10	10	4	80000	80000	10	26728	26728	26728	26728	26728

LDP (signed offset, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations