Firestorm: LDP (signed offset, Q) measurements

Code:

  ldp q0, q1, [x6, #0x10]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
2005	727	6	1	1	45	0	0	1	693	0	12	12	20	25	2000	2000	2000	29597	1	0	702	731	727	405	3	460	2000	2000	2000	728	708	1	1	1001	1000	1000	0	2000	0	2039	0	39	2039	6	1	0	43	73	0	0	2	16	1	1	724	10	0	4	2000	709	709	728	728	728
2004	727	6	0	0	45	1	0	1	712	0	12	12	16	25	2000	2000	2000	29597	0	0	702	727	708	425	3	460	2000	2000	2000	727	727	1	1	1001	1000	1000	0	2000	0	2039	0	40	2039	6	1	39	43	73	0	0	1	16	1	1	773	10	10	4	2000	728	728	729	728	728
2004	708	6	0	0	45	0	0	1	713	2	12	12	16	25	2000	2000	2000	29624	0	0	702	728	708	405	3	460	2000	2000	2000	708	730	1	1	1001	1000	1000	0	2000	43	2039	0	0	2000	6	1	39	43	73	0	0	1	16	1	1	724	10	10	4	2000	728	728	709	709	728
2004	708	6	0	0	45	0	0	1	712	0	12	12	16	25	2000	2000	2000	28591	0	0	702	749	734	408	3	441	2000	2000	2000	708	708	1	1	1001	1000	1000	0	2000	43	2000	0	38	2039	6	1	39	43	73	0	0	1	16	1	1	725	0	0	0	2000	728	728	729	728	709
2004	727	5	0	0	3	0	0	0	693	0	12	12	16	25	2000	2000	2000	28591	0	0	702	731	727	405	3	460	2000	2000	2000	727	727	1	1	1001	1000	1000	0	2000	0	2039	0	42	2039	0	0	39	0	73	0	0	1	16	1	1	724	10	10	4	2000	709	709	728	728	728
2004	727	6	0	0	45	0	0	0	712	2	12	12	16	25	2000	2000	2000	29597	0	0	704	727	732	425	3	441	2000	2000	2000	727	727	1	1	1001	1000	1000	0	2000	0	2039	0	39	2039	6	1	39	43	73	0	0	1	16	1	1	725	10	10	0	2000	709	709	728	709	711
2004	727	5	0	0	0	0	0	1	712	2	12	12	16	25	2000	2000	2000	29597	0	0	683	727	727	425	3	442	2000	2000	2000	728	728	1	1	1001	1000	1000	0	2000	43	2039	0	39	2000	6	1	0	43	73	0	0	1	16	1	1	724	0	10	4	2000	728	728	728	709	728
2004	727	5	0	0	0	1	0	1	712	2	12	12	16	25	2000	2000	2000	29597	0	0	683	736	714	425	3	460	2000	2000	2000	708	727	1	1	1001	1000	1000	0	2000	0	2039	0	39	2040	6	1	39	43	73	0	0	1	16	1	1	724	10	10	4	2000	729	728	709	709	729
2004	728	5	0	0	45	0	0	0	712	2	12	0	0	25	2000	2000	2000	29597	0	0	702	727	727	405	3	460	2000	2000	2000	727	728	1	1	1001	1000	1000	0	2000	0	2039	0	0	2000	6	1	39	43	73	0	0	1	16	1	1	705	10	10	4	2000	728	728	728	729	709
2004	708	5	0	0	45	1	0	0	693	2	12	12	16	25	2000	2000	2000	29574	0	0	702	734	727	405	3	460	2000	2000	2000	727	727	1	1	1001	1000	1000	0	2000	43	2039	0	0	2039	6	1	0	43	73	0	0	1	16	1	1	724	10	0	4	2000	709	728	709	709	709

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp q0, q1, [x6, #0x10]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120053	899	1	0	2	0	0	0	4	0	1	0	1	120038	96718	109730	25	70103	40104	10004	20000	30100	10000	20000	10426946	5733532	3465684	0	120029	0	120042	120053	112141	3	112511	60100	30200	20000	10000	60200	20062	10000	120384	120057	2	1	50201	100	99	100	40100	10000	10000	0	100	20003	3	0	20003	0	2	2	20000	2	2	0	2	2	0	0	3210	1	16	1	1	119826	40002	0	0	5	20000	40100	120054	120054	120054	120042	120042
60204	120053	899	1	0	1	0	0	0	2	0	0	0	1	120038	96718	109742	25	70103	40102	10002	20002	30100	10000	20000	10425873	5733772	3465768	0	120029	0	120053	120041	112141	3	112511	60100	30200	20000	10063	60200	20000	10000	120053	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	20002	4	2	20002	0	3	8	20000	2	2	2	2	1	0	0	3210	1	16	1	1	119826	40004	0	0	5	20000	40100	120054	120054	120054	120042	120042
60204	120041	899	1	0	1	0	0	0	2	0	0	0	0	120026	96718	109746	34	70106	40104	10001	20000	30100	10000	20000	10426917	5733532	3465684	1	120029	0	120053	120041	112129	3	112518	60100	30200	20000	10000	60200	20000	10000	120041	120041	1	1	50201	100	99	100	40100	10000	10000	1	100	20002	2	2	20002	0	0	2	20000	2	2	2	2	0	0	0	3210	1	16	1	1	119826	40004	6	0	5	20000	40100	120054	120042	120054	120054	120054
60204	120041	899	1	0	0	0	0	0	2	0	1	0	0	120026	96718	109742	25	70103	40104	10002	20000	30100	10000	20000	10426917	5733532	3465336	0	120017	0	120053	120053	112129	3	112499	60100	30200	20000	10063	60200	20000	10000	120041	120053	1	1	50201	100	99	100	40100	10000	10000	1	100	20002	2	2	20003	0	0	2	20000	2	2	2	2	2	0	0	3210	1	16	1	1	119814	40004	6	0	5	20000	40100	120143	120054	120042	120054	120054
60204	120041	899	1	1	1	1	1	0	23	0	0	0	1	120038	96718	109742	25	70106	40102	10002	20000	30100	10000	20000	10426917	5733580	3465712	0	120017	0	120059	120053	112141	3	112511	60100	30200	20000	10000	60200	20000	10000	120053	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	20003	2	2	20002	0	1	5	20000	2	2	2	2	0	0	0	3210	1	16	1	1	119877	40002	6	0	5	20000	40100	120054	120056	120054	120042	120042
60204	120053	902	1	0	2	1	0	2	313	352	1	0	1	120038	96718	109730	25	70103	40104	10002	20000	30100	10000	20000	10426917	5733532	3465713	0	120017	0	120041	120041	112141	3	112511	60100	30200	20000	10000	60200	20000	10000	120053	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	20002	2	2	20003	1	0	2	20000	2	2	0	2	1	0	0	3210	1	16	4	2	119814	40004	6	6	5	20000	40100	120042	120042	120042	120054	120042
60204	120053	899	1	1	1	0	0	0	4	0	1	0	1	120038	96706	109730	25	70103	40104	10002	20000	30100	10000	20000	10426917	5733532	3465336	0	120029	0	120041	120053	112141	3	112499	60100	30200	20000	10000	60200	20000	10000	120053	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	20004	3	2	20003	0	0	2	20000	2	2	2	2	0	0	0	3210	1	16	1	1	119826	40004	6	0	5	20000	40100	120054	120054	120054	120042	120054
60204	120041	899	1	1	0	0	0	0	2	0	0	0	1	120043	96718	109742	25	70106	40104	10002	20000	30100	10000	20000	10425873	5733532	3467454	0	120029	0	120053	120041	112129	3	112511	60100	30200	20000	10000	60200	20000	10000	120053	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	20003	2	0	20002	0	1	2	20000	0	2	2	2	0	0	0	3210	1	16	1	1	119826	40004	0	0	5	20000	40100	120042	120042	120054	120058	120054
60204	120053	899	1	0	0	0	0	0	4	0	1	0	1	120043	96706	109730	25	70106	40104	10001	20000	30100	10000	20000	10426917	5733532	3465684	0	120029	0	120053	120053	112129	3	112499	60100	30200	20000	10000	60200	20000	10000	120041	120053	1	1	50201	100	99	100	40100	10000	10000	1	100	20002	2	2	20002	0	0	2	20000	2	2	0	2	0	0	0	3210	1	16	1	1	119826	40004	6	0	0	20000	40100	120054	120042	120054	120054	120042
60204	120053	899	1	1	0	0	0	0	2	0	1	0	0	120061	96718	109730	25	70106	40104	10002	20000	30100	10000	20000	10426917	5732956	3465336	0	120017	0	120053	120053	112141	3	112511	60100	30200	20000	10000	60200	20000	10000	120041	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	20002	2	2	20003	0	0	2	20000	0	2	2	2	2	0	0	3210	1	16	1	1	119826	40004	6	6	5	20000	40100	120042	120042	120054	120054	120054

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0065

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	49	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120059	899	0	0	0	1	0	0	0	0	0	0	2	0	0	0	0	0	120044	2	0	96649	109812	25	70016	40012	10002	20000	30010	10000	20000	10424678	5733052	3465118	0	120035	120043	120059	112170	3	112539	60010	30020	20000	10000	60020	20000	10000	120043	120059	1	1	50021	10	9	10	40010	10000	10000	1	10	20000	0	4	20002	0	0	2	20002	2	2	2	0	0	0	0	0	3140	6	16	8	7	119834	40004	0	10	9	20000	40010	120044	120060	120060	120060	120060
60024	120059	899	0	0	0	0	0	0	1	0	0	0	4	0	0	0	0	0	120044	2	2	96649	109748	25	70019	40016	10003	20000	30010	10000	20000	10426592	5733340	3465292	0	120025	120065	120049	112176	3	112529	60010	30020	20000	10000	60020	20000	10000	120065	120065	1	1	50021	10	9	10	40010	10000	10000	1	10	20002	4	4	20005	0	1	7	20002	2	4	2	2	0	0	0	0	3140	8	16	8	9	119840	40004	10	10	9	20000	40010	120070	120050	120070	120066	120066
60024	120065	900	1	1	0	0	0	1	0	0	0	0	6	0	0	0	0	0	120050	2	2	96655	109754	25	70016	40016	10003	20000	30010	10000	20000	10426592	5734108	3465756	0	120041	120065	120065	112176	3	112545	60010	30020	20000	10000	60020	20000	10000	120065	120065	1	1	50021	10	9	10	40010	10000	10000	0	10	20003	2	4	20006	0	0	4	20002	0	4	2	2	0	0	0	0	3140	8	16	7	8	119824	40004	0	10	0	20000	40010	120066	120066	120066	120066	120066
60024	120065	900	1	0	1	0	0	1	0	0	0	0	4	0	0	0	0	0	120050	2	2	96655	109754	25	70019	40016	10003	20000	30010	10000	20000	10426592	5734108	3465756	0	120041	120065	120065	112176	3	112545	60010	30020	20000	10000	60020	20000	10000	120049	120065	1	1	50021	10	9	10	40010	10000	10000	0	10	20006	4	0	20005	0	0	4	20002	2	4	2	2	0	0	0	0	3140	8	16	7	8	119824	40006	0	10	9	20000	40010	120066	120066	120068	120066	120066
60024	120065	899	1	0	1	0	0	1	0	1	0	1	6	0	0	0	0	0	120034	2	2	96655	109754	25	70019	40016	10003	20000	30010	10000	20000	10426592	5734108	3465756	0	120041	120049	120065	112176	3	112545	60010	30020	20000	10000	60020	20000	10000	120049	120049	1	1	50021	10	9	10	40010	10000	10000	1	10	20002	3	0	20006	0	2	4	20002	2	4	2	2	1	0	0	0	3140	8	16	7	8	119840	40006	10	10	9	20000	40010	120050	120069	120066	120066	120067
60024	120049	899	1	0	1	0	0	0	0	0	0	0	4	0	0	0	0	0	120050	2	2	96639	109738	25	70019	40014	10003	20000	30010	10000	20000	10425200	5734108	3465292	0	120025	120066	120065	112160	3	112529	60010	30020	20000	10000	60020	20000	10000	120049	120065	1	1	50021	10	9	10	40010	10000	10000	0	10	20002	2	4	20004	1	0	4	20002	2	4	2	2	0	0	0	0	3140	8	16	10	7	119840	40006	10	10	9	20000	40010	120066	120066	120066	120066	120066
60024	120065	899	1	0	0	0	0	1	0	0	0	0	4	0	0	0	0	0	120050	2	2	96655	109754	25	70019	40016	10003	20000	30010	10031	20000	10426592	5734108	3465292	1	120041	120065	120065	112176	3	112545	60010	30020	20000	10000	60020	20000	10000	120065	120049	1	1	50021	10	9	10	40010	10000	10000	0	10	20002	2	0	20006	0	2	4	20002	2	4	0	2	1	0	0	0	3140	7	16	7	6	119840	40004	10	10	9	20000	40010	120066	120066	120050	120066	120066
60024	120065	899	1	0	0	0	0	1	0	0	0	0	6	0	1	0	0	0	120050	2	2	96655	109738	25	70016	40016	10003	20000	30010	10000	20000	10426592	5733340	3465756	0	120025	120065	120065	112176	3	112545	60010	30020	20000	10000	60020	20000	10000	120065	120049	1	1	50021	10	9	10	40010	10000	10000	0	10	20002	2	4	20005	0	1	4	20002	2	4	2	2	0	0	0	0	3140	8	16	10	8	119840	40006	10	10	9	20000	40010	120050	120066	120050	120066	120066
60024	120065	900	1	1	0	0	0	0	0	0	0	0	32	0	0	0	0	0	120050	2	2	96655	109754	25	70019	40016	10003	20000	30010	10000	20000	10426592	5734108	3465292	0	120025	120065	120065	112160	3	112529	60010	30020	20000	10000	60020	20000	10000	120065	120049	1	1	50021	10	9	10	40010	10000	10000	0	10	20003	2	4	20005	1	0	4	20002	2	4	2	2	0	0	0	0	3140	7	16	7	8	119840	40006	10	10	9	20000	40010	120069	120066	120066	120050	120050
60024	120049	899	1	1	1	0	0	0	0	0	0	0	4	0	0	0	0	0	120050	2	2	96639	109754	25	70019	40016	10003	20000	30010	10000	20000	10425200	5734108	3465756	0	120041	120065	120065	112176	3	112529	60010	30020	20000	10000	60020	20000	10033	120065	120065	1	1	50021	10	9	10	40010	10000	10000	0	10	20003	2	4	20004	0	0	4	20002	0	4	2	2	2	0	0	0	3140	8	16	7	6	119840	40006	10	0	9	20000	40010	120066	120050	120066	120066	120050

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp q0, q1, [x6, #0x10]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0056

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	49	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120052	899	0	0	0	0	0	0	2	0	1	0	0	1	120028	0	0	96717	109754	25	70103	40102	10001	20000	30100	10000	20000	10426830	5733052	3465655	1	120019	120058	120056	112146	3	112504	60100	30200	20000	10000	60956	20000	10000	120059	120052	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	0	2	20002	0	0	0	0	20000	2	0	2	0	3210	4	16	1	1	119829	40002	10	10	9	20000	40100	120053	120053	120044	120057	120053
60204	120056	899	0	0	0	0	0	0	2	0	0	0	0	1	120041	0	0	96721	109741	25	70166	40102	10001	20000	30100	10000	20000	10426830	5733676	3465887	1	120036	120060	120043	112131	3	112514	60100	30200	20000	10000	60200	20000	10000	120052	120052	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	1	0	0	20000	2	2	2	0	3210	1	16	2	2	119829	40002	0	10	9	20000	40100	120053	120053	120053	120053	120057
60204	120052	899	0	0	0	0	0	0	2	0	0	0	0	1	120041	2	0	96717	109745	25	70103	40102	10001	20000	30100	10000	20000	10427526	5733052	3465771	1	120019	120056	120043	112131	3	112514	60100	30200	20000	10000	60200	20000	10000	120052	120052	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20002	0	0	0	2	20000	0	2	2	0	3210	1	16	1	2	119829	40002	0	14	13	20000	40100	120044	120057	120057	120063	120057
60204	120056	899	0	0	0	0	0	0	2	0	0	1	0	0	120028	0	0	96721	109745	25	70103	40102	10001	20000	30100	10000	20000	10426047	5733676	3465394	1	120030	120052	120052	112144	3	112501	60100	30200	20000	10000	60200	20000	10000	120052	120052	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	2	20000	2	0	2	0	3210	1	16	2	1	119816	40002	14	14	0	20000	40100	120435	120045	120057	120044	120044
60204	120057	902	0	0	0	0	0	0	4	0	0	1	0	1	120028	2	0	96708	109745	25	70106	40102	10001	20000	30100	10000	20000	10426047	5733484	3465394	1	120032	120060	120056	112144	3	112501	60100	30200	20000	10000	60200	20000	10000	120052	120052	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	4	20000	0	3	0	0	20000	2	0	2	0	3210	1	16	1	2	119816	40002	14	10	13	20000	40100	120044	120057	120057	120057	120057
60204	120043	899	0	0	0	0	0	0	2	0	0	0	0	1	120028	2	0	96717	109745	25	70103	40102	10001	20000	30100	10000	20000	10427526	5733676	3465394	1	120032	120052	120043	112144	3	112501	60100	30200	20000	10000	60200	20000	10000	120052	120052	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	0	20002	2	0	2	0	3210	2	49	2	2	119829	40012	10	10	13	20000	40100	120058	120057	120046	120057	120053
60204	120056	900	0	0	0	0	0	0	2	0	0	1	0	0	120041	0	0	96717	109732	25	70103	40102	10001	20000	30100	10000	20200	10426217	5733676	3465655	1	120032	120056	120056	112144	3	112514	60100	30200	20000	10000	60200	20000	10000	120052	120052	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	0	2	20000	0	0	0	3	20000	2	2	0	0	3210	1	16	1	2	119833	40002	0	14	0	20000	40100	120057	120053	120057	120057	120053
60204	120046	899	0	0	0	0	0	0	2	0	0	0	0	1	120037	0	0	96721	109732	25	70103	40102	10001	20000	30100	10000	20000	10427178	5733676	3465655	1	120028	120059	120056	112144	3	112514	60100	30200	20000	10000	60200	20000	10000	120059	120043	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	7	0	0	20000	0	2	2	0	3210	1	16	2	2	119829	40002	10	14	13	20000	40100	120044	120044	120044	120053	120057
60204	120056	899	0	0	0	0	0	0	2	0	0	1	0	0	120045	2	0	96721	109745	25	70103	40102	10002	20000	30100	10000	20000	10426830	5733052	3465771	1	120028	120060	120056	112144	3	112514	60100	30200	20000	10000	60200	20000	10000	120052	120052	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	2	20000	2	0	0	0	3210	1	16	1	2	119829	40002	10	10	13	20000	40100	120057	120053	120057	120057	120057
60204	120052	899	0	0	1	1	0	0	2	0	0	0	0	1	120041	0	0	96725	109745	25	70103	40102	10001	20000	30100	10000	20000	10427178	5733052	3465655	1	120032	120052	120043	112131	3	112501	60100	30200	20000	10000	60382	20000	10000	120056	120043	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20002	0	0	0	0	20000	2	0	0	0	3210	1	16	1	2	119829	40002	10	10	13	20000	40100	120057	120061	120045	120044	120057

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0048

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	0e	18	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120048	899	0	0	0	14	0	0	0	1	120020	96642	109724	25	70013	40012	10001	20000	30010	10000	20000	10425113	5733292	3465263	0	120011	120052	120035	112163	3	112515	60010	30020	20000	10000	60020	20000	10000	120048	120048	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	20000	2	0	0	3140	0	0	0	4	16	2	3	2	119823	40002	0	0	5	20000	40010	120053	120053	120053	120036	120053
60024	120035	899	0	0	0	0	0	0	0	0	120020	96642	109741	25	70013	40010	10001	20000	30010	10000	20000	10425461	5733292	3465263	0	120011	120097	120035	112163	3	112528	60010	30020	20000	10000	60020	20000	10000	120052	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	20000	2	2	0	3140	0	0	0	2	16	0	2	2	119827	40000	10	0	0	20000	40010	120053	120053	120053	120053	120036
60024	120035	899	0	0	0	2	0	0	0	0	120037	96642	109737	25	70013	40012	10001	20000	30010	10000	20000	10425113	5732666	3465263	0	120028	120052	120052	112163	3	112532	60010	30020	20000	10000	60020	20000	10000	120035	120048	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	20000	0	0	20000	0	0	0	3140	0	0	0	2	16	0	2	2	119827	40002	0	10	0	20000	40010	120053	120049	120049	120036	120036
60024	120035	899	0	0	0	2	0	1	0	1	120020	96642	109741	25	70013	40012	10001	20000	30010	10000	20000	10423974	5734374	3466479	0	120028	120035	120052	112146	3	112532	60010	30020	20000	10000	60020	20000	10000	120048	120052	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	20000	0	0	20000	2	2	0	3140	0	0	0	2	16	0	3	3	119823	40002	10	0	9	20000	40010	120049	120036	120036	120049	120053
60024	120052	899	0	0	0	14	0	1	0	1	120020	96642	109737	25	70013	40010	10001	20000	30010	10000	20000	10425461	5732666	3465263	0	120028	120035	120035	112163	3	112515	60010	30020	20000	10000	60020	20000	10000	120052	120048	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	20000	2	2	0	3140	14	0	0	2	16	0	3	3	119827	40000	6	6	0	20000	40010	120036	120036	120036	120036	120036
60024	120035	899	0	0	0	2	0	0	0	0	120037	96638	109737	25	70010	40010	10000	20000	30010	10031	20000	10423974	5733484	3464880	0	120011	120052	120035	112163	3	112532	60010	30020	20000	10000	60020	20000	10000	120052	120048	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	20000	0	2	0	3140	0	0	0	2	16	0	3	2	119810	40000	0	6	5	20000	40010	120036	120053	120053	120053	120049
60024	120035	899	0	0	0	2	0	0	0	1	120037	96642	109741	25	70013	40012	10000	20000	30010	10033	20000	10423974	5732666	3465379	0	120028	120052	120056	112151	3	112532	60010	30020	20000	10000	60020	20000	10000	120035	120048	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	20000	0	3	20000	2	2	0	3140	0	0	0	2	16	1	2	2	119810	40002	0	0	5	20000	40010	120049	120053	120053	120036	120036
60024	120052	899	0	0	0	9	0	1	0	0	120037	93975	109737	25	70013	40012	10000	20000	30010	10000	20000	10423974	5733484	3464880	0	120028	120035	120052	112163	3	112515	60010	30020	20000	10000	60020	20000	10000	120048	120048	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	20000	0	2	0	3140	0	0	0	2	16	1	2	2	119827	40000	10	10	5	20000	40010	120053	120053	120053	120049	120049
60024	120048	899	0	0	0	17	0	0	0	1	120037	93975	109741	25	70010	40012	10001	20000	30010	10000	20000	10425461	5733484	3465263	0	120011	120052	120035	112163	3	112515	60010	30020	20000	10000	60020	20000	10000	120052	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	20000	0	0	20000	2	0	0	3140	0	0	0	2	16	0	2	2	119810	40000	10	10	0	20000	40010	120036	120036	120036	120053	120049
60024	120052	899	0	0	0	2	0	0	0	1	120037	93975	109737	25	70010	40012	10001	20000	30010	10000	20000	10423974	5732666	3464880	0	120024	120035	120035	112159	3	112532	60010	30020	20000	10000	60020	20000	10000	120048	120048	1	1	50021	10	9	10	40010	10000	10000	1	10	20000	2	20000	0	0	20000	2	2	0	3140	0	0	0	2	16	1	2	3	119827	40002	0	6	9	20000	40010	120053	120036	120036	120053	120053

Test 4: throughput

Count: 8

Code:

  ldp q0, q1, [x6, #0x10]
  ldp q0, q1, [x6, #0x10]
  ldp q0, q1, [x6, #0x10]
  ldp q0, q1, [x6, #0x10]
  ldp q0, q1, [x6, #0x10]
  ldp q0, q1, [x6, #0x10]
  ldp q0, q1, [x6, #0x10]
  ldp q0, q1, [x6, #0x10]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6674

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	0e	0f	18	19	1e	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160205	53396	400	0	0	0	0	0	0	44	0	0	0	1	53383	2	12	12	16	25	160100	100	160000	100	160000	500	2334535	1	53384	53394	53374	33296	3	33352	160100	200	160000	200	160000	53398	53394	1	1	80201	100	99	100	100	80000	80000	1	100	160000	43	160038	0	39	160039	6	1	39	43	0	5110	1	16	1	1	53371	0	10	4	160000	100	53395	53375	53395	53395	53395
160204	53398	400	0	0	0	0	0	0	45	0	0	0	0	53379	2	12	12	0	25	160100	100	160000	100	160000	500	2333962	1	53508	53395	53394	33317	3	33352	160100	200	160000	200	160000	53374	53374	1	1	80201	100	99	100	100	80000	80000	0	100	160000	43	160038	0	38	160000	6	1	39	43	0	5110	1	16	1	1	53391	10	10	0	160000	100	53375	53395	53395	53375	53375
160204	53374	400	0	0	0	0	0	0	45	0	0	0	0	53359	2	12	1	16	25	160100	100	160000	100	160000	500	2334535	1	53478	53410	53404	33296	3	33332	160100	200	160000	200	160000	53374	53374	1	1	80201	100	99	100	100	80000	80000	0	100	160000	43	160039	0	42	160039	6	1	39	43	0	5110	1	16	1	1	53391	10	10	4	160000	100	53395	53399	53375	53375	53395
160204	53398	400	0	0	0	0	0	0	45	0	0	0	1	53379	2	12	12	19	25	160100	100	160000	100	160000	500	2333962	1	53438	53394	53395	33317	3	33332	160100	200	160000	200	160000	53398	53374	1	1	80201	100	99	100	100	80000	80000	0	100	160000	43	160000	0	39	160039	6	1	39	43	0	5110	1	16	1	1	53391	10	10	4	160000	100	53378	53399	53375	53395	53569
160204	53394	400	0	0	0	0	0	0	45	0	0	0	1	53379	2	1	12	16	25	160100	100	160000	100	160000	500	2333962	1	53433	53394	53394	33317	3	33332	160100	200	160000	200	160000	53394	53394	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	160039	0	41	160039	6	1	39	0	0	5110	1	16	1	1	53391	10	0	4	160000	100	53395	53375	53375	53395	53375
160204	53394	400	0	0	0	0	0	0	45	0	0	0	1	53379	2	12	12	16	25	160100	100	160000	100	160000	500	2333962	1	53539	53403	53383	33328	3	33352	160100	200	160000	200	160000	53394	53394	1	1	80201	100	99	100	100	80000	80000	0	100	160000	43	160000	0	39	160039	6	0	39	43	0	5110	1	16	1	1	53391	0	10	4	160000	100	53395	53395	53375	53399	53396
160204	53394	400	0	0	0	0	0	0	0	0	0	0	1	53379	2	0	12	0	25	160100	100	160000	100	160000	500	2333962	0	53382	53374	53394	33296	3	33332	160100	200	160000	200	160000	53394	53394	1	1	80201	100	99	100	100	80000	80000	1	100	160000	43	160039	0	39	160039	6	0	39	0	0	5110	1	16	1	1	53391	14	10	0	160000	100	53395	53375	53395	53400	53395
160204	53394	400	0	0	0	0	0	0	45	1	0	0	1	53383	0	12	12	16	25	160100	100	160000	100	160000	500	2332897	0	53515	53394	53394	33296	3	33332	160100	200	160000	200	160000	53374	53394	1	1	80201	100	99	100	100	80000	80000	0	100	160000	43	160039	0	39	160039	6	1	39	43	0	5110	1	16	1	1	53391	10	10	0	160000	100	53395	53375	53375	53399	53395
160204	53394	400	0	0	0	0	0	0	45	1	0	0	0	53379	3	12	0	16	25	160100	100	160000	100	160000	500	2333962	1	53509	53374	53421	33320	3	33332	160100	200	160000	200	160000	53394	53394	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	160000	0	39	160039	6	1	39	0	0	5110	1	16	1	1	53397	10	10	4	160000	100	53395	53403	53548	53545	53399
160204	53394	399	0	0	0	1	0	0	90	0	0	0	1	53359	3	12	0	16	25	160100	100	160000	100	160000	500	2333962	1	53380	53394	53374	33323	3	33360	160100	200	160000	200	160000	53394	53394	1	1	80201	100	99	100	100	80000	80000	1	100	160000	43	160039	0	827	160039	6	1	39	43	0	5110	1	16	1	1	53543	0	10	0	160000	100	53563	53379	53395	53399	53395

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160025	53399	400	1	1	1	0	1	0	0	0	0	65	0	1	0	3	53384	0	18	18	16	25	160010	10	160000	10	160000	50	2333926	1	53356	0	53399	53398	33344	3	33379	160010	20	160000	20	160000	53399	53381	1	1	80021	10	9	10	10	80000	80000	0	10	160019	21	42	0	160059	2	0	1	21	160038	6	1	58	0	19	0	5020	17	16	0	7	13	53396	0	29	6	2	160000	10	53399	53400	53399	53400	53400
160024	53398	400	1	1	0	0	1	0	0	0	0	65	0	1	0	1	53384	2	18	0	16	25	160010	10	160000	10	160000	50	2333926	1	53356	0	53399	53381	33344	3	33361	160010	20	160000	20	160000	53381	53381	1	1	80021	10	9	10	10	80000	80000	0	10	160019	20	0	0	160057	1	0	1	21	160038	6	1	57	40	19	2	5020	13	16	0	12	14	53396	0	0	9	2	160000	10	53400	53382	53400	53399	53400
160024	53399	399	1	1	0	0	0	0	0	0	0	65	0	1	0	3	53383	2	18	18	16	25	160010	10	160000	10	160000	50	2333926	1	53356	0	53399	53398	33344	3	33378	160010	20	160000	20	160000	53398	53398	1	1	80021	10	9	10	10	80000	80000	0	10	160020	20	42	0	160019	0	0	0	59	160038	6	1	55	0	19	0	5089	13	16	0	13	12	53396	0	0	9	2	160000	10	53400	53400	53400	53400	53400
160024	53381	400	1	0	1	0	1	0	0	0	0	21	0	1	0	2	53384	2	18	18	1	25	160010	10	160000	10	160000	50	2332997	1	53356	0	53398	53381	33344	3	33378	160010	20	160000	20	160000	53398	53399	1	1	80021	10	9	10	10	80000	80000	0	10	160020	21	42	0	160056	1	0	2	21	160038	0	1	57	42	19	0	5020	8	16	0	12	11	53396	0	9	9	0	160000	10	53382	53382	53400	53382	53400
160024	53381	400	1	1	1	0	1	0	0	0	0	21	0	0	0	1	53384	2	0	0	0	25	160010	10	160000	10	160000	50	2349817	1	53374	0	53381	53399	33344	3	33379	160010	20	160000	20	160000	53399	53398	1	1	80021	10	9	10	10	80000	80000	0	10	160021	21	42	0	160058	1	0	2	59	160000	0	1	19	42	19	1	5020	12	16	0	10	10	53396	0	0	9	0	160000	10	53399	53383	53400	53399	53399
160024	53399	400	1	1	0	0	0	0	0	0	0	21	0	1	0	0	53383	0	18	18	16	25	160010	10	160000	10	160000	50	2332997	1	53374	0	53381	53398	33344	3	33378	160010	20	160000	20	160000	53398	53398	1	1	80021	10	9	10	10	80000	80000	0	10	160019	20	42	0	160057	0	0	0	59	160038	0	1	57	42	19	1	5020	12	16	0	9	10	53378	0	9	9	0	160000	10	53385	53400	53382	53400	53400
160024	53399	400	1	0	1	0	0	0	0	0	0	21	0	0	0	2	53366	2	0	18	1	25	160010	10	160000	10	160000	50	2355367	1	53374	0	53398	53399	33343	3	33379	160010	20	160000	20	160000	53399	53398	1	1	80021	10	9	10	10	80000	80000	0	10	160019	20	42	0	160019	0	0	0	59	160038	6	0	57	0	19	1	5020	12	16	0	12	12	53378	0	0	0	2	160000	10	53399	53382	53382	53400	53382
160024	53381	400	1	1	0	0	1	0	0	0	0	65	0	0	0	3	53383	0	18	18	17	25	160010	10	160000	10	160000	50	2332997	1	53374	0	53381	53398	33326	3	33378	160010	20	160000	20	160000	53401	53399	1	1	80021	10	9	10	10	80000	80000	0	10	160020	19	42	0	160057	1	0	1	59	160038	0	1	57	42	19	1	5052	12	16	0	11	12	53396	0	0	9	2	160000	10	53382	53400	53400	53399	53399
160024	53381	400	1	1	1	0	1	0	0	0	0	21	0	1	0	1	53366	0	0	18	0	25	160010	10	160000	10	160000	50	2339999	1	53360	0	53399	53382	33343	3	33398	160010	20	160000	20	160000	53399	53381	1	1	80021	10	9	10	10	80000	80000	0	10	160019	20	42	0	160058	0	0	0	24	160038	0	1	18	42	18	1	5037	12	25	0	12	12	53396	0	0	9	0	160000	10	53399	53382	53556	53550	53542
160024	53550	400	1	1	1	0	1	1	0	0	0	77	0	0	0	3	53387	0	18	18	18	49	160140	10	160000	10	160000	50	2345285	1	53374	0	53695	53552	33344	3	33378	160010	20	160000	20	160000	53398	53381	1	1	80021	10	9	10	10	80000	80000	1	10	160020	19	0	0	160019	1	0	0	21	160038	6	1	57	40	19	1	5020	13	16	0	11	13	53381	0	9	9	0	160000	10	53399	53400	53400	53399	53382

LDP (signed offset, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations